Nanoimprint system development and status for high-volume semiconductor manufacturing

Tsuneo Takashima; Yukio Takabayashi; Naosuke Nishimura; Keiji Emoto; Takahiro Matsumoto; Tatsuya Hayashi; Atsushi Kimura; Jin Choi; Philip Schumaker

doi:10.1117/12.2219001

22 March 2016 Nanoimprint system development and status for high-volume semiconductor manufacturing

Tsuneo Takashima, Yukio Takabayashi, Naosuke Nishimura, Keiji Emoto, Takahiro Matsumoto, Tatsuya Hayashi, Atsushi Kimura, Jin Choi, Philip Schumaker

Author Affiliations +

Proceedings Volume 9777, Alternative Lithographic Technologies VIII; 977706 (2016) https://doi.org/10.1117/12.2219001
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made overlay, throughput and defectivity and to introduce the FPA-1200NZ2C cluster system designed for high volume manufacturing of semiconductor devices. in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Overlay results better than 5nm 3sigma have been demonstrated. To further enhance overlay, wafer chucks with improved flatness have been implemented to reduce distortion at the wafer edge. To address higher order corrections, a two part solution is discussed. An array of piezo actuators can be applied to enable linear corrections. Additional reductions in distortion can then be addressed by the local heating of a wafer field. The NZ2C cluster platform for high volume manufacturing is also discussed. System development continues this year with a target for introduction later in 2016. The first application is likely to be NAND Flash memory, and eventual use for DRAM and logic devices as both overlay and defectivity improve.

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Tsuneo Takashima, Yukio Takabayashi, Naosuke Nishimura, Keiji Emoto, Takahiro Matsumoto, Tatsuya Hayashi, Atsushi Kimura, Jin Choi, and Philip Schumaker "Nanoimprint system development and status for high-volume semiconductor manufacturing", Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 977706 (22 March 2016); https://doi.org/10.1117/12.2219001

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