OS friendly microprocessor architecture: Hardware level computer security

Patrick Jungwirth; Patrick La Fratta

doi:10.1117/12.2220777

12 May 2016 OS friendly microprocessor architecture: Hardware level computer security

Patrick Jungwirth, Patrick La Fratta

Proceedings Volume 9826, Cyber Sensing 2016; 982602 (2016) https://doi.org/10.1117/12.2220777
Event: SPIE Defense + Security, 2016, Baltimore, MD, United States

Abstract

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor’s execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor’s execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

Citation Download Citation

Patrick Jungwirth and Patrick La Fratta "OS friendly microprocessor architecture: Hardware level computer security", Proc. SPIE 9826, Cyber Sensing 2016, 982602 (12 May 2016); https://doi.org/10.1117/12.2220777

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