Inhibiting device degradation induced by surface damages during top-down fabrication of semiconductor devices with micro/nano-scale pillars and holes

Ahmed S. Mayet; Hilal Cansizoglu; Yang Gao; Ahmet Kaya; Soroush Ghandiparsi; Toshishige Yamada; Shih-Yuan Wang; M. Saif Islam

doi:10.1117/12.2241736

27 September 2016 Inhibiting device degradation induced by surface damages during top-down fabrication of semiconductor devices with micro/nano-scale pillars and holes

Ahmed S. Mayet, Hilal Cansizoglu, Yang Gao, Ahmet Kaya, Soroush Ghandiparsi, Toshishige Yamada, Shih-Yuan Wang, M. Saif Islam

Author Affiliations +

Proceedings Volume 9924, Low-Dimensional Materials and Devices 2016; 99240C (2016) https://doi.org/10.1117/12.2241736
Event: SPIE Nanoscience + Engineering, 2016, San Diego, California, United States

Abstract

High-aspect ratio semiconductor pillar- and hole-based structures are being investigated for photovoltaics, energy harvesting devices, transistors, and sensors. The fabrication of pillars and holes frequently involves top-down fabrication (such as dry etching) of semiconductors. Such a process contributes to different types of crystalline defects including vacancies, interstitials, dislocations, stacking faults, surface roughness, impurities, and charging effects. These defects contribute to degraded device characteristics impacting detection sensitivity, energy conversion efficiency, etc. In this presentation, we review dry-etched semiconductor devices and demonstrate several possible methods to inhibit device degradation induced by surface damage. These methods include hydrogen passivation, the growth of oxide passivating thin films using wet furnace growth, and low-ion energy etching. These methods contributed to a leakage current reduction by as much as four orders of magnitude.

Conference Presentation

Citation Download Citation

Ahmed S. Mayet, Hilal Cansizoglu, Yang Gao, Ahmet Kaya, Soroush Ghandiparsi, Toshishige Yamada, Shih-Yuan Wang, and M. Saif Islam "Inhibiting device degradation induced by surface damages during top-down fabrication of semiconductor devices with micro/nano-scale pillars and holes", Proc. SPIE 9924, Low-Dimensional Materials and Devices 2016, 99240C (27 September 2016); https://doi.org/10.1117/12.2241736

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