CMOS standard cells characterization for open defects for test pattern generation

Andrzej Wielgus; Witold Pleskacz

doi:10.1117/12.2261887

22 December 2016 CMOS standard cells characterization for open defects for test pattern generation

Andrzej Wielgus, Witold Pleskacz

Proceedings Volume 10175, Electron Technology Conference 2016; 101750I (2016) https://doi.org/10.1117/12.2261887
Event: Electron Technology Conference ELTE 2016, 2016, Wisla, Poland

Abstract

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.

Citation Download Citation

Andrzej Wielgus and Witold Pleskacz "CMOS standard cells characterization for open defects for test pattern generation", Proc. SPIE 10175, Electron Technology Conference 2016, 101750I (22 December 2016); https://doi.org/10.1117/12.2261887

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available