Paper
27 March 2017 EUV process improvement with novel litho track hardware
Author Affiliations +
Abstract
Currently, there are many developments in the field of EUV lithography that are helping to move it towards increased HVM feasibility. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for metrics such as CD uniformity, LWR, and defect density. Of course, our work is focused on EUV process steps that are specifically affected by litho track performance, and consequently, can be improved by litho track design improvement and optimization. In this study we are building on our experience to provide continual improvement for LWR, CDU, and Defects as applied to a standard EUV process by employing novel hardware solutions on our SOKUDO DUO coat develop track system. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that improvements after patterning are a precursor to improvements after etching. We hereby present our work utilizing the SOKUDO DUO coat develop track system with an ASML NXE:3300 in the IMEC (Leuven, Belgium) cleanroom environment to improve aggressive dense L/S patterns.
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Harold Stokes, Masahiko Harumoto, Yuji Tanaka, Koji Kaneyama, Charles Pieczulewski, and Masaya Asai "EUV process improvement with novel litho track hardware", Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 101431Z (27 March 2017); https://doi.org/10.1117/12.2259994
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KEYWORDS
Annealing

Extreme ultraviolet

Line width roughness

Semiconducting wafers

Standards development

Extreme ultraviolet lithography

Lithography

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