Computational scanner wafer mark alignment

Boris Menchtchikov; Robert Socha; Sudharshanan Raghunathan; Irina Lyulina; Hielke Schoonewelle; Patrick Tinnemans; Paul Tuffy; Philippe Leray; Christiane Jehoul

doi:10.1117/12.2259750

30 March 2017 Computational scanner wafer mark alignment

Boris Menchtchikov, Robert Socha, Sudharshanan Raghunathan, Irina Lyulina, Hielke Schoonewelle, Patrick Tinnemans, Paul Tuffy, Philippe Leray, Christiane Jehoul

Author Affiliations +

Proceedings Volume 10147, Optical Microlithography XXX; 101471C (2017) https://doi.org/10.1117/12.2259750
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in order to achieve the required precision and accuracy for wafer alignment performance.

ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of alignment recipe settings.

Citation Download Citation

Boris Menchtchikov, Robert Socha, Sudharshanan Raghunathan, Irina Lyulina, Hielke Schoonewelle, Patrick Tinnemans, Paul Tuffy, Philippe Leray, and Christiane Jehoul "Computational scanner wafer mark alignment", Proc. SPIE 10147, Optical Microlithography XXX, 101471C (30 March 2017); https://doi.org/10.1117/12.2259750

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