Presentation + Paper
1 May 2017 Reconfigurable signal processor designs for advanced digital array radar systems
Author Affiliations +
Abstract
The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera’s devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU’s dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hernan Suarez, Yan (Rockee) Zhang, and Xining Yu "Reconfigurable signal processor designs for advanced digital array radar systems", Proc. SPIE 10188, Radar Sensor Technology XXI, 101880P (1 May 2017); https://doi.org/10.1117/12.2262317
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CITATIONS
Cited by 1 scholarly publication.
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KEYWORDS
Calibration

Radar

Expectation maximization algorithms

Field programmable gate arrays

Signal to noise ratio

Signal processing

Clocks

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