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Proceedings Article

Nanoimprint lithography for semiconductor devices and future patterning innovation

[+] Author Affiliations
Tatsuhiko Higashiki, Tetsuro Nakasugi, Ikuo Yoneda

Toshiba Corp. (Japan)

Proc. SPIE 7970, Alternative Lithographic Technologies III, 797003 (March 17, 2011); doi:10.1117/12.882940
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From Conference Volume 7970

  • Alternative Lithographic Technologies III
  • Daniel J. C. Herr
  • San Jose, California | February 27, 2011

abstract

Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.

© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Citation

Tatsuhiko Higashiki ; Tetsuro Nakasugi and Ikuo Yoneda
"Nanoimprint lithography for semiconductor devices and future patterning innovation", Proc. SPIE 7970, Alternative Lithographic Technologies III, 797003 (March 17, 2011); doi:10.1117/12.882940; http://dx.doi.org/10.1117/12.882940


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