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Proceedings Article

Litho and patterning challenges for memory and logic applications at the 22-nm node

[+] Author Affiliations
Jo Finders, Peter Nikolsky, Youri van Dommelen

ASML (Netherlands)

Mircea Dusa

ASML US Inc. (Netherlands)

Robert Watso

ASML Albany (USA)

Tom Vandeweyer, Joost Beckaert, Bart Laenens, Lieve Van Look

IMEC vzw (Belgium)

Proc. SPIE 7640, Optical Microlithography XXIII, 76400C (March 22, 2010); doi:10.1117/12.848330
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From Conference Volume 7640

  • Optical Microlithography XXIII
  • Mircea V. Dusa; Will Conley
  • San Jose, California | February 21, 2010

abstract

In this paper we look into the litho and patterning challenges at the 22nm node. These challenges are different for memory and logic applications driven by the difference in device layout. In the case of memory, very small pitches and CDs have to be printed, close to the optical diffraction limit (k1) and resist resolution capability. For random logic applications e.g. the printing of SRAM, real pitch splitting techniques have to be applied for the first time at the 22nm node due to the aggressive dimensions of extreme small and compact area and pitch of SRAM bitcell. Common challenges are found for periphery of memory and random logic SRAM cells: here the Best Focus difference per feature type, limits the Usable Depth of Focus.

© (2010) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Citation

Jo Finders ; Mircea Dusa ; Peter Nikolsky ; Youri van Dommelen ; Robert Watso, et al.
"Litho and patterning challenges for memory and logic applications at the 22-nm node", Proc. SPIE 7640, Optical Microlithography XXIII, 76400C (March 22, 2010); doi:10.1117/12.848330; http://dx.doi.org/10.1117/12.848330


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