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Proceedings Article

16nm with 193nm immersion lithography and double exposure

[+] Author Affiliations
Valery Axelrad

Sequoia Design Systems, Inc. (USA)

Michael C. Smayling

Tela Innovations, Inc. (USA)

Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764109 (April 02, 2010); doi:10.1117/12.846677
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From Conference Volume 7641

  • Design for Manufacturability through Design-Process Integration IV
  • Michael L. Rieger; Joerg Thiele
  • San Jose, California | February 21, 2010

abstract

Gridded Design Rules (GDR) in combination with lines/ cuts double patterning allow imaging of 16nm designs with 193nm immersion lithography. Highly regular lines/ cut patterns result in the existence of a well-defined optimal set of lithographic conditions. Since cuts are all of identical shape and relatively sparse, good image quality can be obtained with minimal or simplified pattern correction (OPC equivalent) to compensate for proximity effects. The use of local interconnect (LI) is shown to offer further reduction of the required number of cuts and improves pattern uniformity and image quality. Critical cut patterns of poly and M1 layers in selected worst case standard GDR cells were considered. Simultaneous co-optimization of cut geometry as well as lithographic conditions such as scanner entrance pupil illumination was used to bring all cuts within ~1nm of target CDs at best focus. Optimized conditions significantly reduced the sensitivity of printed patterns to proximity effects. Manufacturability was verified using DOF and NILS metrics before and after co-optimization. Experimental lens entrance pupil illumination and lens aberrations including polarization effects were included in the analysis.

© (2010) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Citation

Valery Axelrad and Michael C. Smayling
"16nm with 193nm immersion lithography and double exposure", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764109 (April 02, 2010); doi:10.1117/12.846677; http://dx.doi.org/10.1117/12.846677


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