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Low density parity check (LDPC) codes are a class of forward-error-correction codes. They are among the best-known
codes capable of achieving low bit error rates (BER) approaching Shannon's capacity limit. Recently, LDPC codes have
been adopted by the European Digital Video Broadcasting (DVB-S2) standard, and have also been proposed for the
emerging IEEE 802.16 fixed and mobile broadband wireless-access standard. The consultative committee for space data
system (CCSDS) has also recommended using LDPC codes in the deep space communications and near-earth
communications. It is obvious that LDPC codes will be widely used in wired and wireless communication, magnetic
recording, optical networking, DVB, and other fields in the near future.
Efficient hardware implementation of LDPC codes is of great interest since LDPC codes are being considered for a wide
range of applications. This paper presents an efficient partially parallel decoder architecture suited for quasi-cyclic (QC)
LDPC codes using Belief propagation algorithm for decoding. Algorithmic transformation and architectural level
optimization are incorporated to reduce the critical path. First, analyze the check matrix of LDPC code, to find out the
relationship between the row weight and the column weight. And then, the sharing level of the check node updating units
(CNU) and the variable node updating units (VNU) are determined according to the relationship. After that, rearrange
the CNU and the VNU, and divide them into several smaller parts, with the help of some assistant logic circuit, these
smaller parts can be grouped into CNU during the check node update processing and grouped into VNU during the
variable node update processing. These smaller parts are called node update kernel units (NKU) and the assistant logic
circuit are called node update auxiliary unit (NAU). With NAUs' help, the two steps of iteration operation are completed
by NKUs, which brings in great hardware resource reduction. Meanwhile, efficient techniques have been developed to
reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing.
This method may be applied not only to regular LDPC codes, but also to the irregular ones.
Based on the proposed architectures, a (7493, 6096) irregular QC-LDPC code decoder is described using verilog
hardware design language and implemented on Altera field programmable gate array (FPGA) StratixII EP2S130. The
implementation results show that over 20% of logic core size can be saved than conventional partially parallel decoder
architectures without any performance degradation. If the decoding clock is 100MHz, the proposed decoder can achieve
a maximum (source data) decoding throughput of 133 Mb/s at 18 iterations.
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