Paper
23 March 2009 Sampling strategy: optimization and correction for high-order overlay control for 45nm process node
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Abstract
The tight overlay budgets required for 45nm and beyond make overlay control a very important topic. With the adoption of immersion lithography, the incremental complexity brings much more difficulty to analyzing the source of variation and optimizing the sampling strategy. In this paper, there will be a discussion about how the use of an advanced sampling methodology and strategy can help to overcome this overlay control problem and insure sufficient overlay information to be captured for effective production lot excursion detection as well as rework decision making. There will also be a demonstration of the different correction methodologies to improve overlay control for dual-stage systems in order to maximize the productivity benef its with minimal impact to overlay performance.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bo Yun Hsueh, George K. C. Huang, Chun-Chi Yu, Chin-Chou Kevin Huang, Chien-Jen Huang, James R. Manka, and David Tien "Sampling strategy: optimization and correction for high-order overlay control for 45nm process node", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 727231 (23 March 2009); https://doi.org/10.1117/12.812929
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Semiconducting wafers

Overlay metrology

Process control

Control systems

Metrology

Error analysis

Lithography

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