Wafer overlay requirement for the 32nm HP node for DRAM volume production is targeted at 6.4nm (single exposure) in 2013. Consequently, this is placing a significantly tighter demand on the pattern placement accuracy on photomasks: at or below 3.8nm (3sigma). In case Double Patterning Lithography (DPL) becomes the manufacturing technique for 32nm and 22nm node devices, the pattern placement specification of dependent layers is less than 3nm, according to the ITRS roadmap. In addition to photomask lithography pattern placement instability, the distortion influence of the pellicle on plate bending is also an error contributor especially when the pellicle distortions are not repeatable substrate to substrate. The combination of increased demand for greater accuracy and the influence of pellicle distortions are key factors in the need for high resolution through-pellicle in-die measurements based on actual device features. A new registration metrology tool dedicated for the 32nm HP node and beyond is under beta testing. Actual status and performance data of the beta evaluation system is provided to verify registration metrology capability for DPL reticle manufacturing; to characterize the reticle contribution to total wafer overlay error; and help keep such error within the required tolerances.© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.