Aggressive CMOS transistor scaling requirements have motivated the IC industry to look beyond simply reducing the film thickness or implementing different gate stack materials towards fundamentally redesigning the transistor architecture by forcing the silicon channel to protrude upwards from the planar (2D) substrate. These 3D transistors, namely FinFETs, ideally offer at least a 2X improvement in the drive current since more than one surface is available, for which the minority carrier population can be adjusted by an applied voltage. However, the ability to modulate this voltage is known to suffer due to the non-uniform film deposition on the three sides of the Si Fin. This concern is of immediate interest because it impedes device performance and future integration since subtle differences among the thicknesses on each side of the Fin will negatively impact threshold voltage and the capability to tune the effective work function. It is therefore necessary to have an in-line metrology capability that can properly characterize and understand the deposition of both the high-k and metal gate film on the sidewalls of the Fin in order for FinFETs to ultimately replace planar CMOS devices. We will report on the ability of scatterometry to accurately measure the high-k and metal film thickness on the sidewall of the FinFET. The results will be discussed in detail with emphasis on sensitivity towards fin critical dimension (CD) and sidewall thickness, and comparison of the conclusions reached from the analysis with cross-sectional transmission electron microscopy (TEM) data.© (2008) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.