Chip manufacturing with multilayer reticles offers the possibility to reduce reticle cost at the expense of scanner throughput, and is therefore an attractive option for small-volume production and test chips. Since 2010, GLOBALFOUNDRIES Fab 1 uses this option for the 28nm IP shuttles and test chips offered to their customers for development and advance testing of their products. This paper discusses the advantages and challenges of this approach and the practical experience gained during implementation. One issue that must be considered is the influence of the small image field and the asymmetric reticle illumination on the lithographic key parameters, namely layer to layer overlay. Theoretical considerations and experimental data concerning the effects of lens distortion, lens heating, and reticle heating on overlay performance are presented, and concepts to address the specific challenges of multilayer reticles for high-end chip production are discussed.© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.