ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies

Reinhard März; Kai Peter; Monika Gschöderer; Eduard Ratai; Alexander Nielsen; Sascha Siegler; Rosi Deppe; Anton Huber

doi:10.1117/12.771885

4 March 2008 ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies

Reinhard März, Kai Peter, Monika Gschöderer, Eduard Ratai, Alexander Nielsen, Sascha Siegler, Rosi Deppe, Anton Huber

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Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 692510 (2008) https://doi.org/10.1117/12.771885
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

With the upcoming technology generations, it will become increasingly challenging to provide a good yield and/or yield ramp. In addition, we observe yield detractors migrating from defects via systematic effects such as litho and CMP to out-of-spec scenarios, i.e. a slow, but continuous migration into an typical environment for analog devices. Preparing for such scenarios, worldwide activities are ongoing to extract the device parameters not from the drawn layout, but from the resist image or, at best, from etched contours. The litho-aware approach allows to detect devices of high variability and to reduce the variations on the critical paths based on this analysis. We report in this paper the analysis of MOSFET parameters from printed PC contours of standard cell libraries based on litho simulation (LfD). It will be shown how to extract gate lengths and -widths from print images, how to backannotate the gate parameters into a litho-aware spice netlist and to finally analyse the effect of across chip line width variations (ACLV) and process window influence based on litho-aware spice netlist.

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Reinhard März, Kai Peter, Monika Gschöderer, Eduard Ratai, Alexander Nielsen, Sascha Siegler, Rosi Deppe, and Anton Huber "ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692510 (4 March 2008); https://doi.org/10.1117/12.771885

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KEYWORDS

Transistors

Calibration

Field effect transistors

Lithography

Chemical mechanical planarization

Doping

Resolution enhancement technologies

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