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Proceedings Article

40Gbit/s interface conversion circuit for 40GbE, STM-256/OC-768 and OTU3 serial signal transport

[+] Author Affiliations
Shigeki Aisawa, Masahito Tomizawa

NTT Network Innovation Labs. (Japan) and Photonics Electronics Technology Research Association (Japan)

Proc. SPIE 7988, Optical Transmission Systems, Switching, and Subsystems VIII, 79880L (February 18, 2011); doi:10.1117/12.888248
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From Conference Volume 7988

  • Optical Transmission Systems, Switching, and Subsystems VIII
  • Yikai Su; Ernesto Ciaramella; Xiang Liu; Naoya Wada
  • Shanghai, China | December 08, 2010

abstract

We use a 65nm CMOS process technology to develop 40Gbit/s interface conversion prototype circuits for 40GbE, STM- 256/OC-768 and OTU3 tri-rate serial signal transport. For the first time, interface conversion functions from SFI-5.1 to SFI-5.2/XLAUI are demonstrated on a 16:4 MUX prototype chip, and from SFI-5.2/XLAUI to SFI-5.1 on a 4:16 DEMUX prototype chip. The 16:4 MUX and 4:16 DEMUX prototype chips show excellent jitter performance and consume 1.6 and 1.7 W, respectively.

© (2010) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Citation

Shigeki Aisawa and Masahito Tomizawa
"40Gbit/s interface conversion circuit for 40GbE, STM-256/OC-768 and OTU3 serial signal transport", Proc. SPIE 7988, Optical Transmission Systems, Switching, and Subsystems VIII, 79880L (February 18, 2011); doi:10.1117/12.888248; http://dx.doi.org/10.1117/12.888248


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