40Gbit/s interface conversion circuit for 40GbE, STM-256/OC-768 and OTU3 serial signal transport

Shigeki Aisawa; Masahito Tomizawa

doi:10.1117/12.888248

18 February 2011 40Gbit/s interface conversion circuit for 40GbE, STM-256/OC-768 and OTU3 serial signal transport

Shigeki Aisawa, Masahito Tomizawa

Proceedings Volume 7988, Optical Transmission Systems, Switching, and Subsystems VIII; 79880L (2011) https://doi.org/10.1117/12.888248
Event: Asia Communications and Photonics Conference and Exhibition, 2010, Shanghai, Shanghai, China

Abstract

We use a 65nm CMOS process technology to develop 40Gbit/s interface conversion prototype circuits for 40GbE, STM- 256/OC-768 and OTU3 tri-rate serial signal transport. For the first time, interface conversion functions from SFI-5.1 to SFI-5.2/XLAUI are demonstrated on a 16:4 MUX prototype chip, and from SFI-5.2/XLAUI to SFI-5.1 on a 4:16 DEMUX prototype chip. The 16:4 MUX and 4:16 DEMUX prototype chips show excellent jitter performance and consume 1.6 and 1.7 W, respectively.

Citation Download Citation

Shigeki Aisawa and Masahito Tomizawa "40Gbit/s interface conversion circuit for 40GbE, STM-256/OC-768 and OTU3 serial signal transport", Proc. SPIE 7988, Optical Transmission Systems, Switching, and Subsystems VIII, 79880L (18 February 2011); https://doi.org/10.1117/12.888248

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