First via-hole TEG fabricated by using 90-nm CMOS technology and proximity electron lithography: electric and lithographic results

Tetsuya Kitagawa; Masaki Yoshizawa; Kazuya Iwase; Shinji Omori; Shoji Nohama; Hiroyuki Nakano; Shigeru Moriya; Hiroichi Kawahira

doi:10.1117/12.534423

20 May 2004 First via-hole TEG fabricated by using 90-nm CMOS technology and proximity electron lithography: electric and lithographic results

Tetsuya Kitagawa, Masaki Yoshizawa, Kazuya Iwase, Shinji Omori, Shoji Nohama, Hiroyuki Nakano, Shigeru Moriya, Hiroichi Kawahira

Author Affiliations +

Proceedings Volume 5374, Emerging Lithographic Technologies VIII; (2004) https://doi.org/10.1117/12.534423
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

Low-energy electron-beam proximity-projection lithography (LEEPL) is considered the best candidate for the next-generation lithography (NGL) tool because a production tool will be available for 65nm-node mass production. Resolution capability has already exceeded the 65nm-node requirement and possibly also the 45nm-node requirement. Although LEEPL requires a resist less than 100nm thick to obtain the resolution, our tri-layer resist process provides the critical-dimension (CD) uniformity and dry-etching resistance necessary for fabricating 90nm-node via holes. As regards an overlay, a LEEPL tool aligned to an under layer printed by an ArF scanner attained 21.3nm (three sigma) overlay error, which exceeds the requirement for the 65nm node. Another concern with LEEPL application is mask contamination growth during exposure, however the contamination growth rate is gradual that the CD shift due to the contamination is under control. We applied LEEPL to 90nm-node via hole fabrication to examine whether it provides a higher resolution than an ArF scanner. We determined that the electrical-resistance limit for LEEPL is approximately 100nm diameter for a via hole and the limit for an ArF scanner is approximately 125nm diameter. Even without process optimization, LEEPL showed its advantages for via-hole fabrication over an ArF scanner.

Citation Download Citation

Tetsuya Kitagawa, Masaki Yoshizawa, Kazuya Iwase, Shinji Omori, Shoji Nohama, Hiroyuki Nakano, Shigeru Moriya, and Hiroichi Kawahira "First via-hole TEG fabricated by using 90-nm CMOS technology and proximity electron lithography: electric and lithographic results", Proc. SPIE 5374, Emerging Lithographic Technologies VIII, (20 May 2004); https://doi.org/10.1117/12.534423

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available