Recent advances in CMOS read-out integrated circuit (ROIC) design have helped achieve 10e- of read noise with single read and down to 5e- read noise with 32-pair Fowler sampling at slower astronomical frame rates. However, applications like adaptive optics pose even more stringent performance requirements on ROICs for visible and IR focal plane arrays (FPAs). Traditional pixel designs use circuits such as source followers, capacitive trans-impedance amplifiers (CTIA), and buffered-direct injection (BDI) for detector charge integration and readout. Currently these techniques by themselves do not achieve sub 10e- read noise at high readout bandwidths. This paper describes circuit design advances and measured performance that enable ROICs with ultra-low noise readout (3-10e-) at signal bandwidths allowing KHz frame rate on 128x128 and larger arrays. Using deep sub-micron CMOS, high conversion gain has been designed in a small unit-cell area while keeping high bandwidth for reset and readout, and sufficiently low power dissipation to avoid MOSFET self-emission for background-limited sensitivity at ultra-low scene backgrounds. Measured performance of one of the pixel designs reported in detail shows a noise floor of 7e- with HgCdTe detector array, near identical to the design value.© (2004) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.