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Proceedings Article

Nanoimprint lithography: the path toward high-tech, low-cost devices (Keynote Paper)

[+] Author Affiliations
William M. Tong

Hewlett-Packard Co. (USA) and Hewlett-Packard Labs. (USA)

Scott D. Hector

SEMATECH (USA)

Gun-Young Jung, Wei Wu, R. S. Williams

Hewlett-Packard Labs. (USA)

James Ellenson, Kenneth Kramer, Timothy Hostetler, Susan K. Richards

Hewlett-Packard Co. (USA)

Proc. SPIE 5751, Emerging Lithographic Technologies IX, 46 (May 6, 2005); doi:10.1117/12.607236
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From Conference Volume 5751

  • Emerging Lithographic Technologies IX
  • R. Scott Mackay
  • San Jose, CA | February 27, 2005

abstract

Nanoimprint lithography is a contact-lithography technology invented in 1996 as a low-cost alternative to photolithography for researchers who need high resolution patterning. Initially perceived as a trailing-edge technology for low-cost device fabrication, it has been recently demonstrated to achieve sub-10 nm resolution and alignment, which equal or surpass even the most advanced photolithography today. At Hewlett-Packard, we have successfully used it to fabricate switchable molecular memory arrays with a dimension of 65 nm half pitch. Nanoimprint has been placed on the International Technology Roadmap for Semiconductors (ITRS) as a candidate for next-generation lithography (NGL) for insertion in the 32 nm node in Y2013. The switch from using light to using contact to pattern will indeed bring new challenges, the most important of which are alignment and the 1x mask/template. For alignment, one imprint tool maker has achieved alignment of +/-7 nm 3 sigma using Moire patterns. For template fabrication, the lack of OPC and other sub-resolution features produced large savings in patterning, but it is nearly cancelled out by the need for more aggressive inspection because of the smaller tolerable defect size. The two combined to make the predicted cost of nanoimprint template to be similar to photomasks for 45-nm half pitch. At 32-nm half pitch, EUVL masks do not have complicated sub-resolution features and are predicted to be cheaper than comparable nanoimprint templates provided that the former"s defect levels can be reduced to what is required for economical manufacturing. In both cases, the challenges are not insurmountable and solutions are being actively pursued. However, if nanoimprint is indeed the disruptive technology to photolithography, it needs to take its initial aim at the low-end market rather than mount a frontal challenge at semiconductor manufacturing, which is the high-margin customers that photolithography will pursue and protect at all cost. The recent development in nanotechnology will lead to the commercialization of a new class of nanoscale devices requiring a high-resolution lithographic technique that does not have all the functionalities of photolithography. This approach will provide an initial customer base for nanoimprint to develop and improve and position it to challenge photolithography in the distant future.

© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Citation

William M. Tong ; Scott D. Hector ; Gun-Young Jung ; Wei Wu ; James Ellenson, et al.
"Nanoimprint lithography: the path toward high-tech, low-cost devices (Keynote Paper)", Proc. SPIE 5751, Emerging Lithographic Technologies IX, 46 (May 6, 2005); doi:10.1117/12.607236; http://dx.doi.org/10.1117/12.607236


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