Applications of CPL mask technology for sub-65nm gate imaging

Lloyd C. Litt; Will Conley; Wei Wu; Richie Peters; Colita Parker; Jonathan Cobb; Bryan S. Kasprowicz; Doug van den Broeke; J. C. Park; Ramkumar Karur-Shanmugam

doi:10.1117/12.600912

12 May 2005 Applications of CPL mask technology for sub-65nm gate imaging

Lloyd C. Litt, Will Conley, Wei Wu, Richie Peters, Colita Parker, Jonathan Cobb, Bryan S. Kasprowicz, Doug van den Broeke, J. C. Park, Ramkumar Karur-Shanmugam

Author Affiliations +

Proceedings Volume 5754, Optical Microlithography XVIII; (2005) https://doi.org/10.1117/12.600912
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater critical dimension (CD) control if properly applied. Unfortunately, the application of hard shifter technology to production requires significant effort in layout and optical proximity correction (OPC) application. Chromeless Phase Lithography (CPL) has several advantages over complementary phase mask (c:PSM) such as use of a single mask, and lack of phase placement 'coloring' conflicts and phase imbalance issues. CPL does have implementation issues that must be resolved before it can be used in full-scale production. CPL mask designs can be approached by separating features into three zones based on several parameters, including size relative to the lithographic resolution of the stepper lens, wavelength, and illumination conditions defined. Features are placed into buckets for different treatment zones. Zone 1 features are constructed with 100% transmission phase shifted structures and Zone 3 features are chrome (binary) structures. Features that fall into Zone 2, which are too wide to be defined using the 100% transmission of pure CPL (i.e. have negative mask error factor, MEEF) are the most troublesome and can be approached in several ways. The authors have investigated the application of zebra structures of various sizes to product type layouts. Previous work to investigate CPL using test structures set the groundwork for the more difficult task of applying CPL rules to actual random logic design layouts, which include many zone transitions. Mask making limitations have been identified that play a role in the zebra sizing that can be applied to Zone 2 features. The elimination of Zone 2 regions was also investigated in an effort to simplify the application of CPL and improve manufacturability of reticle through data enhancements.

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Lloyd C. Litt, Will Conley, Wei Wu, Richie Peters, Colita Parker, Jonathan Cobb, Bryan S. Kasprowicz, Doug van den Broeke, J. C. Park, and Ramkumar Karur-Shanmugam "Applications of CPL mask technology for sub-65nm gate imaging", Proc. SPIE 5754, Optical Microlithography XVIII, (12 May 2005); https://doi.org/10.1117/12.600912

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