Hardware/software codesign for embedded RISC core

Peng Liu

doi:10.1117/12.451073

20 December 2001 Hardware/software codesign for embedded RISC core

Peng Liu

Proceedings Volume 4674, Media Processors 2002; (2001) https://doi.org/10.1117/12.451073
Event: Electronic Imaging, 2002, San Jose, California, United States

Abstract

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls the pipeline stage status and cooperation among the pipeline phase. Since description use high level language and structure is distributed, VIRGO core has highly extension that can meet the requirements of application. We take look at the high-definition television MPEG2 MPHL decoder chip, constructed the hardware/software codesign virtual prototyping machine that can research on VIRGO core instruction set architecture, and system on chip memory size requirements, and system on chip software, etc. We also can evaluate the system on chip design and RISC instruction set based on the virtual prototyping machine platform.

Citation Download Citation

Peng Liu "Hardware/software codesign for embedded RISC core", Proc. SPIE 4674, Media Processors 2002, (20 December 2001); https://doi.org/10.1117/12.451073

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