Low-power serial-parallel bootstrapped dynamic shift register

Leo Lee; Said F. Al-Sarawi; Derek Abbott

doi:10.1117/12.472851

14 November 2002 Low-power serial-parallel bootstrapped dynamic shift register

Leo Lee, Said F. Al-Sarawi, Derek Abbott

Proceedings Volume 4935, Smart Structures, Devices, and Systems; (2002) https://doi.org/10.1117/12.472851
Event: SPIE's International Symposium on Smart Materials, Nano-, and Micro- Smart Systems, 2002, Melbourne, Australia

Abstract

In this paper a new low power area efficient serial-to-parallel shift register design is presented. The design of the register only contains 4 transistors per stage and uses a capacitive bootstrapping technique to offset the threshold voltage drop of MOSFETs. We shall refer to this logic family as Non-Ratioed Bootstrap Logic (NRBL). The intended target applications are in smart sensor arrays and image sensors for use in the select registers to control the photo diode array.

Citation Download Citation

Leo Lee, Said F. Al-Sarawi, and Derek Abbott "Low-power serial-parallel bootstrapped dynamic shift register", Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); https://doi.org/10.1117/12.472851

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