Maximizing poling efficiency of a 3-layer NLO polymer-based structure using conductive polymer cladding layers

Jeremy B. Huddleston; James G. Grote; Robert L. Nelson; John S. Zetts; Frank Kenneth Hopkins

doi:10.1117/12.426918

16 May 2001 Maximizing poling efficiency of a 3-layer NLO polymer-based structure using conductive polymer cladding layers

Jeremy B. Huddleston, James G. Grote, Robert L. Nelson, John S. Zetts, Frank Kenneth Hopkins

Author Affiliations +

Proceedings Volume 4290, Optoelectronic Integrated Circuits and Packaging V; (2001) https://doi.org/10.1117/12.426918
Event: Symposium on Integrated Optics, 2001, San Jose, CA, United States

Abstract

Conductive cladding layers for electrode poled nonlinear optic (NLO) polymer waveguides have been investigated for use in electro-optic (EO) switching devices. Dropping most of the poling field across the NLO core material optimized poling efficiencies, which in turn allows for lower poling voltages and in-situ poling. In addition, this method has the potential for realizing higher EO coefficients, shorter devices, and lower operating voltages than conventional devices with passive claddings. Poling efficiency enhancement has been achieved for 2-layer structures resulting in the lowest poling voltage to date, 300 V, for a 2 micrometers thick NLO polymer core layer and a 2 micrometers thick Baytron P/PVA)polyethylene dioxythiphene/polystyrene sulfonate in polyvinyl alcohol) conductive cladding layer. This has rendered up to 13 times increase in the effective EO coefficient. New results are presented from extending the concept to 3-layer device structures using the conductive polymer material for both the top and bottom cladding. Our results show that conductive claddings for NLO polymer waveguides will be realizable in actual devices.

Citation Download Citation

Jeremy B. Huddleston, James G. Grote, Robert L. Nelson, John S. Zetts, and Frank Kenneth Hopkins "Maximizing poling efficiency of a 3-layer NLO polymer-based structure using conductive polymer cladding layers", Proc. SPIE 4290, Optoelectronic Integrated Circuits and Packaging V, (16 May 2001); https://doi.org/10.1117/12.426918

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