Paper
26 July 1999 Method to budget and optimize total device overlay
Author Affiliations +
Abstract
We combine lithographic simulation, experimental data and statistical modeling to build a predictive estimator of total device overlay. To generate accurate predictions of total overlay, we include error estimates on lens image placement, CD control, reticle and exposure tool alignment. Instead of combining these errors in ad hoc root sum square fashion to make overlay estimates, we construct a physical model of the device and metrology marker edge placement processes. The model comprehends the differential placement of metrology structures and device features due to lens and illumination system asymmetries and is therefore applicable to the evaluation of arbitrary illumination and pattern geometry conditions. Since we attempt to model the relative placement distribution of specific device features, the model produces overlay estimates that are directly relevant for device performance. The comparison of our total overlay estimate to device overlay sensitivity data allows a projection of the overlay related yield loss for a given device, process and tools et. Finally, our model allows the process engineer to made informative choices on the optimum error sources to pursue for improving overlay.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christopher J. Progler, Scott J. Bukofsky, and Donald C. Wheeler "Method to budget and optimize total device overlay", Proc. SPIE 3679, Optical Microlithography XII, (26 July 1999); https://doi.org/10.1117/12.354331
Lens.org Logo
CITATIONS
Cited by 8 scholarly publications and 13 patents.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Overlay metrology

Error analysis

Instrument modeling

Critical dimension metrology

Semiconducting wafers

Reticles

Lithography

RELATED CONTENT

Micrascan II overlay error analysis
Proceedings of SPIE (May 17 1994)
Evaluating device design rules based on lithographic capability
Proceedings of SPIE (September 14 2001)
Advanced mix and match using a high NA i line...
Proceedings of SPIE (July 05 2000)
0.10-um overlay for DRAM production using step and scan
Proceedings of SPIE (June 01 1990)

Back to Top