Paper
27 February 2015 Customized Nios II multi-cycle instructions to accelerate block-matching techniques
Diego González, Guillermo Botella, Carlos García, Anke Meyer Bäse, Uwe Meyer Bäse, Manuel Prieto-Matías
Author Affiliations +
Proceedings Volume 9400, Real-Time Image and Video Processing 2015; 940002 (2015) https://doi.org/10.1117/12.2077104
Event: SPIE/IS&T Electronic Imaging, 2015, San Francisco, California, United States
Abstract
This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Diego González, Guillermo Botella, Carlos García, Anke Meyer Bäse, Uwe Meyer Bäse, and Manuel Prieto-Matías "Customized Nios II multi-cycle instructions to accelerate block-matching techniques", Proc. SPIE 9400, Real-Time Image and Video Processing 2015, 940002 (27 February 2015); https://doi.org/10.1117/12.2077104
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Cited by 2 scholarly publications.
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KEYWORDS
Information operations

Field programmable gate arrays

Logic

Motion estimation

Embedded systems

Profiling

Video coding

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