Mr. Aswin Sreedhar Profile

Aswin Sreedhar

SPIE Involvement:

Author

Publications (2)

This will count as one of your downloads.

You will have access to both the presentation and article (if available).

DOWNLOAD NOW

This content is available for download via your institution's subscription. To access this item, please sign in to your personal account.

Email or Username Forgot your username?

Password Forgot your password?

Show

Keep me signed in

No SPIE account? Create an account

Proceedings Article | 3 April 2010 Paper

EM calibration based on Post OPC layout analysis

Aswin Sreedhar, Sandip Kundu

Proceedings Volume 7641, 764113 (2010) https://doi.org/10.1117/12.846567

KEYWORDS: Calibration, Metals, Reliability, Resistance, Photomasks, Optical proximity correction, Lithography, Manufacturing, Computer aided design, Electrons

Read Abstract +

Design for Manufacturability (DFM) involves changes to the design and CAD tools to help increase pattern printability and improve process control. Design for Reliability (DFR) performs the same to improve reliability of devices from failures such as Electromigration (EM), gate-oxide break down, hot carrier injection (HCI), Negative Bias Temperature Insatiability (NBTI) and mechanical stress effects. Electromigration (EM) occurs due to migration or displacement of atoms as a result of the movement of electrons through a conducting medium. The rate of migration determines the Mean Time to Failure (MTTF) which is modeled as a function of temperature and current density. The model itself is calibrated through failure analysis (FA) of parts that are deemed to have failed due to EM against design parameters such as linewidth. Reliability Verification (RV) of a design involves verifying that every conducting line in a design meets certain MTTF threshold. In order to perform RV, current density for each wire must be computed. Current itself is a function of the parasitics that are determined through RC extraction. The standard practice is to perform the RC extraction and current density calculation on drawn, pre-OPC layouts. If a wire fails to meet threshold for MTTF, it may be resized. Subsequently, mask preparation steps such as OPC and PSM introduce extra features such as SRAFs, jogs,hammerheads and serifs that change their resistance, capacitance and current density values. Hence, calibrating EM model based on pre-OPC layouts will lead to different results compared to post-OPC layouts. In this work, we compare EM model calibration and reliability check based on drawn layout versus predicted layout, where the drawn layout is pre-OPC layout and predicted layout is based on litho simulation of post-OPC layout. Results show significant divergence between these two approaches, making a case for methodology based on predicted layout.

Proceedings Article | 3 April 2010 Paper

Stat-LRC: statistical rules check for variational lithography

Aswin Sreedhar, Sandip Kundu

Proceedings Volume 7641, 76410P (2010) https://doi.org/10.1117/12.846606

KEYWORDS: Photomasks, Lithography, Metals, Line width roughness, Error analysis, Image segmentation, Yield improvement, Optical proximity correction, Monte Carlo methods, Databases

Read Abstract +

As interconnect densities increase with each technology generation, the lithographic processes required to print all features with acceptable irregularities have become more complex. Restricted design rules (RDR) and modelbased Design for Manufacturability (DFM) guidelines have been added to the existing Design Rule Check (DRC) software to prevent unprintable patterns to be drawn on the mask by predicting their imprint on the wafer. It is evident from analyses of predicted patterns that edge placement errors have a continuous distribution, hence a pass/fail cut-off is somewhat arbitrary. In this paper, we describe a methodology to perform Statistical Lithography Rules Check (Stat-LRC) involving design yield based on interconnect linewidth distribution for variation in lithographic input error sources. In this scheme, a list of error locations indicating polygons that have yield below a user specified threshold are listed. The overall design yield is recovered by trading-off slightly poorer EPE distributions for lines with short runs with excellent ones. The simulation/analysis environment is fully automated and yield recovery improvement has been demonstrated.

My Library

You currently do not have any folders to save your paper to! Create a new folder below.

Folder Name

Folder Description

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks. You are receiving this notice because your organization may not have SPIE eBooks access.*

*Shibboleth/Open Athens users─please sign in to access your institution's subscriptions.

To obtain this item, you may purchase the complete book in print or electronic format on SPIE.org.

ORGANIZATIONAL
Sign in with credentials provided by your organization.

Organizational Username

Organizational Password

Show/Hide Password

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members:

Non-members: ADD TO CART

Keywords/Phrases

Search In:

Publication Years