Dr. Derren N. Dunn Profile

Dr. Derren N. Dunn

Advisory Engineers at IBM Thomas J Watson Research Ctr

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Author

Publications (24)

SPIE Journal Paper | 8 November 2022 Open Access

Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning

Scott Halle, Derren Dunn, Allen Gabor, Max Bloomfield, Mark Shephard

JM3, Vol. 21, Issue 04, 041604, (November 2022) https://doi.org/10.1117/12.10.1117/1.JMM.21.4.041604

KEYWORDS: Reactive ion etching, Neural networks, Surface plasmons, Semiconducting wafers, Optical lithography, Data modeling, Stochastic processes, Etching, Data processing, Chaos

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Proceedings Article | 13 June 2022 Presentation

Feasibility study of machine learning modeling for full chip optical proximity correction

Yuping Cui, Jing Xue, Jing Sha, Zheng Guo Chen, Larry Zhuang, Derren Dunn, Jeffrery Shearer, Li-Jin Chen, Rich Wu, Charlie King

Proceedings Volume 12052, 120520R (2022) https://doi.org/10.1117/12.2614060

KEYWORDS: Optical proximity correction, Machine learning, Data modeling, Neural networks, Process modeling, Photomasks, Wafer-level optics, Semiconducting wafers, Lithography, Photoresist processing

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Proceedings Article | 22 April 2021 Presentation + Paper

Speeding up OPC by leveraging existing designs with machine learning

Cheng Chi, Julian Dolby, Jeffrery Shearer, Derren Dunn, Sean Burns

Proceedings Volume 11614, 116140N (2021) https://doi.org/10.1117/12.2584621

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Proceedings Article | 6 May 2020 Presentation + Paper

Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning

Scott Halle, Max Bloomfield, Allen Gabor, Derren Dunn, Mark Shephard

Proceedings Volume 11329, 113290B (2020) https://doi.org/10.1117/12.2551649

KEYWORDS: Neural networks, Surface plasmons, Reactive ion etching, Optical lithography, Semiconducting wafers, Data modeling, Metrology, Bayesian inference, Stochastic processes, Etching

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Proceedings Article | 23 March 2020 Presentation + Paper

EUVL mask process development and verification using advanced modeling and characterization techniques

Michael Green, Romain Lallement, Mohamed Ramadan, Derren Dunn, Henry Kamberian, Stuart Sieg, Young Ham, Chris Progler

Proceedings Volume 11323, 113230Q (2020) https://doi.org/10.1117/12.2560545

KEYWORDS: Photomasks, Semiconducting wafers, Extreme ultraviolet lithography, Scanning electron microscopy, Line edge roughness, Stochastic processes, Optical proximity correction, SRAF, Metals, Lithography

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Mask technology is key to enabling the progression of advanced IC technology nodes into the realm beyond 7nm node logic. In particular, extreme ultraviolet lithography (EUVL) relies heavily on the mask in order to achieve adequate process window (PW) and final yields. In the EUVL environment, mask process development and verification becomes increasingly more difficult and costly. The mask manufacture costs are driven by multiple factors including significantly more expensive mask blanks and increased ebeam write times. Wafer verification of mask process improvements is very difficult with the relatively low number of early adopters of EUVL and high cost associated with processing non-product wafers with that technology. It is therefore useful for mask manufacturers and wafer lithographers to collaborate to develop low cost mask process screening techniques as a precursor to committing valuable EUV exposure time for final verification. Previously, we demonstrated that by utilizing a toolkit of mask and wafer analytical techniques known as advanced mask characterization and optimization (AMCO) [2], we were able to predict wafer defectivity on 1D and 2D metal structures and optimize a mask process to enable 30nm pitch interconnect in a single exposure step using EUVL [1]. In this study, we use similar methodology to develop a mask process for beyond 7nm node logic contact and via layers. These structures pose a different set of challenges than the metal layer. Contact hole area loss, corner rounding (CR), and mask process-induced x-y error on asymmetric holes must be optimized to deliver the required capability. Additionally, sub-resolution assist features (SRAFs) become relevant at this node. Resolving these on the mask is critical. Here, we describe the development of a mask process to overcome these challenges. We use advanced modeling techniques including AMCO to characterize the process improvements and predict wafer performance. Mask process improvements that are characterized include both physical mask process components as well as write data optimization techniques, i.e. mask process correction (MPC).

Proceedings Article | 26 March 2019 Presentation + Paper

EUV mask challenges and requirements for ultimate single exposure interconnects

Chris Progler, Michael Green, Ravi Bonam, Henry Kamberian, Mohamed Ramadan, Derren Dunn, Young Ham, Yohan Choi, Luciana Meli, Nelson Felix, Daniel Corliss, Bryan Kasprowicz

Proceedings Volume 10957, 109570L (2019) https://doi.org/10.1117/12.2515071

KEYWORDS: Photomasks, Semiconducting wafers, Image processing, Extreme ultraviolet lithography, Electron beam lithography, Stochastic processes, Inspection, Line edge roughness, Extreme ultraviolet, Optical proximity correction

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Proceedings Article | 6 September 2018 Paper

Computational enablement for designs with sub-20nm metal tip to tip using cut shapes from grapho-epitaxy directed self-assembly

Balint Meliorisz, Kafai Lai, Ulrich Welling, Hans-Jürgen Stock, Sajan Marokkey, Thomas Muelders, Jing Sha, Chi-chun Liu, Cheng Chi, Jing Guo, Clifford Osborn, Jaime Morillo, Wolfgang Demmerle, Derren Dunn

Proceedings Volume 10586, 105860R (2018) https://doi.org/10.1117/12.2297344

KEYWORDS: Metals, Directed self assembly, Critical dimension metrology, Calibration, Error analysis, Etching, Computer simulations, Process modeling, Optical lithography, Extreme ultraviolet lithography

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Proceedings Article | 30 March 2017 Presentation + Paper

Design intent optimization at the beyond 7nm node: the intersection of DTCO and EUVL stochastic mitigation techniques

Michael Crouse, Lars Liebmann, Vince Plachecki, Mohamed Salama, Yulu Chen, Nicole Saulnier, Derren Dunn, Itty Matthew, Stephen Hsu, Keith Gronlund, Francis Goodwin

Proceedings Volume 10148, 101480H (2017) https://doi.org/10.1117/12.2260865

KEYWORDS: Extreme ultraviolet, Extreme ultraviolet lithography, Stochastic processes, Optical lithography, Lithography, Tolerancing, Computational lithography, Design for manufacturability, Manufacturing, Back end of line, Source mask optimization, Photomasks, Logic, Optical proximity correction, Nanoimprint lithography

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The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical part of technology enablement as scaling has become more challenging and the industry pushes the limits of EUV lithography. The working partnership between the design teams and the process development teams typically involves an iterative approach to evaluate the manufacturability of proposed designs, subsequent modifications to those designs and finally a design manual for the technology. While this approach has served the industry well for many generations, the challenges at the Beyond 7nm node require a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout optimization where we remove the iterative component of DTCO and replace it with an optimization that achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects. Solved together, this “design intent” approach can more quickly achieve superior lithographic results while still meeting the original device’s functional specifications.

Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall optimization. We will show the benefit of the “design intent approach” on both bidirectional and unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO approach. Thus demonstrating the benefit of allowing the design to float within the specified range. Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on some minimal set of functional requirements and process constraints.

Proceedings Article | 21 March 2017 Paper

Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond

Derren Dunn, John Sporre, Vaibhav Deshpande, Mohamed Oulmane, Ronald Gull, Peter Ventzek, Alok Ranjan

Proceedings Volume 10149, 101490Q (2017) https://doi.org/10.1117/12.2271389

KEYWORDS: Etching, Process modeling, Ions, Image processing, Oxides, Monte Carlo methods, 3D modeling, Plasma etching, Chemical elements, Interfaces, Optical lithography, Plasma, Bromine, Semiconducting wafers

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SPIE Journal Paper | 19 July 2016

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Keiichiro Hitomi, Scott Halle, Marshal Miller, Ioana Graur, Nicole Saulnier, Derren Dunn, Nobuhiro Okai, Shoji Hotta, Atuko Yamaguchi, Hitoshi Komuro, Toru Ishimoto, Shunsuke Koshihara, Yutaka Hojo

JM3, Vol. 15, Issue 03, 034002, (July 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.3.034002

KEYWORDS: Optical proximity correction, Data modeling, Critical dimension metrology, Optical calibration, Scanning electron microscopy, Hybrid optics, Metals, Calibration, Instrument modeling, OLE for process control

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Proceedings Article | 18 March 2016 Paper

EUV patterning successes and frontiers

Nelson Felix, Dan Corliss, Karen Petrillo, Nicole Saulnier, Yongan Xu, Luciana Meli, Hao Tang, Anuja De Silva, Bassem Hamieh, Martin Burkhardt, Yann Mignot, Richard Johnson, Chris Robinson, Mary Breton, Indira Seshadri, Derren Dunn, Stuart Sieg, Eric Miller, Genevieve Beique, Andre Labonte, Lei Sun, Geng Han, Erik Verduijn, Eunshoo Han, Bong Cheol Kim, Jongsu Kim, Koichi Hontake, Lior Huli, Corey Lemley, Dave Hetzer, Shinichiro Kawakami, Koichi Matsunaga

Proceedings Volume 9776, 97761O (2016) https://doi.org/10.1117/12.2219894

KEYWORDS: Extreme ultraviolet, Optical lithography, Lithography, Extreme ultraviolet lithography, Oxides, Neodymium, Ions, Etching

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Proceedings Article | 31 March 2014 Paper

Hybrid OPC modeling with SEM contour technique for 10nm node process

Keiichiro Hitomi, Scott Halle, Marshal Miller, Ioana Graur, Nicole Saulnier, Derren Dunn, Nobuhiro Okai, Shoji Hotta, Atsuko Yamaguchi, Hitoshi Komuro, Toru Ishimoto, Shunsuke Koshihara, Yutaka Hojo

Proceedings Volume 9052, 90520W (2014) https://doi.org/10.1117/12.2047678

KEYWORDS: Optical proximity correction, Data modeling, Scanning electron microscopy, Critical dimension metrology, Metals, Instrument modeling, Calibration, Metrology, Logic devices, OLE for process control

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Proceedings Article | 12 April 2013 Paper

Benchmarking study of 3D mask modeling for 2X and 1X nodes

ChangAn Wang, Chao-Chun Liang, Huikan Liu, Chidam Kallingal, Derren Dunn, James Oberschmidt, Jaione Tirapu Azpiroz

Proceedings Volume 8683, 86831A (2013) https://doi.org/10.1117/12.2011485

KEYWORDS: Photomasks, 3D modeling, Optical proximity correction, Performance modeling, Data modeling, Calibration, Critical dimension metrology, Metals, Error analysis, Diffraction

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Proceedings Article | 29 March 2013 Paper

Etch correction and OPC: a look at the current state and future of etch correction

Ian Stobert, Derren Dunn

Proceedings Volume 8685, 868504 (2013) https://doi.org/10.1117/12.2015000

KEYWORDS: Etching, Optical proximity correction, Model-based design, Lithography, Photomasks, Critical dimension metrology, Data modeling, Extreme ultraviolet, Silicon, Printing

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Proceedings Article | 25 September 2010 Paper

Physical resist model calibration for implant level using laser-written photomasks

Dongbing Shao, Bidan Zhang, Sajan Marokkey, Todd Bailey, Derren Dunn, Emily Gallagher, Yea-Sen Lin, Takashi Murakami, Seiji Nakagawa, Chandrasekhar Sarma, Mohamed Talbi

Proceedings Volume 7823, 78230U (2010) https://doi.org/10.1117/12.865131

KEYWORDS: Photomasks, Data modeling, Calibration, 3D modeling, Semiconducting wafers, Scanning electron microscopy, Optical proximity correction, Photoresist processing, Process modeling, Silicon

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Proceedings Article | 3 April 2010 Paper

3D physical modeling for patterning process development

Chandra Sarma, Amr Abdo, Todd Bailey, Will Conley, Derren Dunn, Sajan Marokkey, Mohamed Talbi

Proceedings Volume 7641, 76410B (2010) https://doi.org/10.1117/12.846637

KEYWORDS: 3D modeling, Critical dimension metrology, Data modeling, Process modeling, Scanning electron microscopy, Semiconducting wafers, Etching, Optical lithography, Printing, 3D image processing

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Proceedings Article | 13 March 2010 Paper

Three-dimensional physical photoresist model calibration and profile-based pattern verification

Mohamed Talbi, Amr Abdo, Todd Bailey, Will Conley, Derren Dunn, Masashi Fujimoto, John Nickel, No Young Chung, Sajan Marokkey, Si Hyeung Lee, Chandrasekhar Sarma, Dongbing Shao, Ramya Viswanathan

Proceedings Volume 7640, 76401D (2010) https://doi.org/10.1117/12.846466

KEYWORDS: 3D modeling, Photoresist materials, Data modeling, Calibration, Scanning electron microscopy, Critical dimension metrology, Photomasks, 3D image processing, Statistical modeling, Optical lithography

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Proceedings Article | 16 March 2009 Paper

Etch aware optical proximity correction: a first step toward integrated pattern engineering

D. Dunn, S. Mansfield, I. Stobert, C. Sarma, G. Lembach, J. Liu, K. Herold

Proceedings Volume 7274, 727412 (2009) https://doi.org/10.1117/12.814224

KEYWORDS: Optical proximity correction, Etching, Lithography, Semiconducting wafers, Process modeling, Photoresist processing, Reactive ion etching, Critical dimension metrology, Calibration, Photomasks

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Proceedings Article | 16 March 2009 Paper

A new method for post-etch OPC modeling to compensate for underlayer effects from integrated wafers

Chandra Sarma, Amr Abdo, Derren Dunn, Daniel Fischer, Klaus Herold, Scott Mansfield, Len Tsou

Proceedings Volume 7274, 72740Z (2009) https://doi.org/10.1117/12.813546

KEYWORDS: Semiconducting wafers, Etching, Data modeling, Optical proximity correction, Instrument modeling, Critical dimension metrology, Photomasks, Data integration, Integrated modeling, Photoresist processing

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Proceedings Article | 16 March 2009 Paper

C-quad polarized illumination for back end thin wire: moving beyond annular illumination regime

Sohan Mehta, Hyung-Rae Lee, Bassem Hamieh, Chidam Kallingal, Itty Matthew, Ramya Viswanathan, Derren Dunn

Proceedings Volume 7274, 72742Y (2009) https://doi.org/10.1117/12.814296

KEYWORDS: Polarization, Line edge roughness, Optical lithography, Semiconducting wafers, Diffraction, Fiber optic illuminators, Fourier transforms, Critical dimension metrology, Lithography, Reticles

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Proceedings Article | 17 October 2008 Paper

Single exposure is still alive: gate patterning at 45nm technology node

Klaus Herold, Donald Samuels, Derren Dunn, Amr Abdo, Chandrasekhar Sarma

Proceedings Volume 7122, 71220W (2008) https://doi.org/10.1117/12.801526

KEYWORDS: Optical proximity correction, Optical lithography, Etching, Double patterning technology, Process modeling, Photomasks, Semiconducting wafers, Computer simulations, Tolerancing, Manufacturing

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Proceedings Article | 17 October 2008 Paper

Double dipole RET investigation for 32 nm metal layers

Carl Babcock, Yi Zou, Derren Dunn, Zachary Baum, Zengqin Zhao, Itty Matthew, Pat LaCour

Proceedings Volume 7122, 71220R (2008) https://doi.org/10.1117/12.801789

KEYWORDS: SRAF, Optical proximity correction, Resolution enhancement technologies, Photomasks, Critical dimension metrology, Metals, Fiber optic illuminators, Printing, Algorithm development, Detection and tracking algorithms

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Proceedings Article | 1 April 2008 Paper

32 nm logic patterning options with immersion lithography

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, D. Medeiros

Proceedings Volume 6924, 69243C (2008) https://doi.org/10.1117/12.784107

KEYWORDS: Photomasks, Double patterning technology, Logic, Lithography, Etching, Optical lithography, Optical proximity correction, Immersion lithography, Printing, Image processing

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The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Proceedings Article | 26 March 2007 Paper

Dark Field Double Dipole Lithography (DDL) for back-end-of-line processes

M. Burkhardt, Sean Burns, Derren Dunn, T. Brunner, Stephen Hsu, Jungchul Park

Proceedings Volume 6520, 65200K (2007) https://doi.org/10.1117/12.713277

KEYWORDS: Photomasks, SRAF, Lithography, Optical proximity correction, Photoresist processing, Metals, Lithographic illumination, Printing, Resolution enhancement technologies, Fiber optic illuminators

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Showing 5 of 24 publications

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