Mr. L. Jeff Myron Profile

L. Jeff Myron

Energy Solutions Program Manager at JSR Micro Inc

SPIE Involvement:

Author

Publications (2)

Proceedings Article | 23 March 2006 Paper

Defect inspection for imprint lithography using a die to database electron beam verification system

L. Jeff Myron, Ecron Thompson, Ian McMackin, Douglas Resnick, Tadashi Kitamura, Toshiaki Hasebe, Shinichi Nakazawa, Toshifumi Tokumoto, Eric Ainley, Kevin Nordquist, William Dauksher

Proceedings Volume 6151, 61510M (2006) https://doi.org/10.1117/12.659457

KEYWORDS: Inspection, Metals, Lithography, Silica, Logic, Semiconducting wafers, Defect detection, Photomasks, Chromium, Databases

Read Abstract +

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FIL^TM) is a unique method for printing sub-100nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz. Three different experiments were performed. In the first study, large (350-400nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70nm. Using a pixel address of 3nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.

Proceedings Article | 10 May 2005 Paper

Advanced mask metrology enabling characterization of imprint lithography templates

L. Myron, Liraz Gershtein, Gidi Gottlieb, Bob Burkhardt, Andrew Griffiths, David Mellenthin, Kevin Rentzsch, Susan MacDonald, Greg Hughes

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.603718

KEYWORDS: Semiconducting wafers, Lithography, Chromium, Photomasks, Quartz, Critical dimension metrology, Etching, Metrology, Photoresist processing, Cadmium

Read Abstract +

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years