KEYWORDS: Charge-coupled devices, Clocks, Field programmable gate arrays, Camera shutters, CCD image sensors, Sensors, Chromium, Signal to noise ratio, Control systems, Seaborgium
The paper designs a driving circuit of high sensitive, wide dynamic and high signal-to-noise ratio for binocular CCD
imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Inner
structure and driving timing of the FTF5066M sensor are presented. Field Programmable Gate Array (FPGA) is used as
the main device to accomplish the timing design of the circuits and power driver control of the two sensors. By using the
Correlated Double Sampling (CDS) technique, the video noise is reduced and the SNR of the system is increased. A 12-
bit A/D converter is used to improve the image quality. The output rate of the imaging system designed with integrated
chip can reach to 1.3 frames per second through bi-channel. For its good performance, low power consumption and small
volume, the driving system can be applied to aeronautics and astronautics field. With a further improvement, a maximum
data output rate of 2.7 frames per second can be reached through all the eight channels of the two CCDs.
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