Dr. Thuc Dam Profile

Dr. Thuc Dam

Sr. Manager Product Engineering at Synopsys Inc

SPIE Involvement:

Author

Publications (33)

Proceedings Article | 10 April 2024 Presentation

Advancing the curvilinear ILT and OPC ecosystem for low-k1 DUV and EUV lithography

Guangming Xiao, Kevin Hooker, Yunqiang Zhang, Ji Li, Thuc Dam, Yu-Po Tang, Linghui Wu, WooJoo Sim, Kevin Lucas

Proceedings Volume 12954, 1295413 (2024) https://doi.org/10.1117/12.3014637

KEYWORDS: Photomasks, Deep ultraviolet, Optical proximity correction, Extreme ultraviolet lithography, Ecosystems, Lithography, Extreme ultraviolet, Yield improvement, Source mask optimization, Printing

Read Abstract +

Proceedings Article | 1 May 2023 Presentation + Paper

Computational patterning and process variation impact on photonics devices

Maryvonne Chalony, Lawrence Melvin, Rainer Zimmermann, Bernd Küchler, Emilie Viasnoff, Robert Scarmozzino, Daniel Herrmann, Yves Saad, Phil Stopford, Thuc Dam, Ulrich Klostermann, Wolfgang Demmerle, Al Blais, Remco Stoffer

Proceedings Volume 12499, 124990A (2023) https://doi.org/10.1117/12.2658788

KEYWORDS: Design and modelling, Manufacturing, Polarization, Optics manufacturing, Photonic devices, Optical lithography, Incident light, Metalenses, Geometrical optics, Optical proximity correction

Read Abstract +

Proceedings Article | 28 April 2023 Presentation + Paper

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Jennefir Digaum, Gary Chiang, Lin Wang, Kyle Braam, Dave Gerold, Yongdong Wang, Thuc Dam

Proceedings Volume 12495, 1249503 (2023) https://doi.org/10.1117/12.2657538

KEYWORDS: Design and modelling, Optical proximity correction, Semiconducting wafers, Lithography, Manufacturing, Visualization, Reticles, Printing, 193nm lithography, Source mask optimization

Read Abstract +

Proceedings Article | 28 April 2023 Presentation + Paper

Scalable hierarchy extraction of repeating structures to enhance full chip mask synthesis

Jun Zhu, Lin Wang, Brad Falch, Thuc Dam, Yongdong Wang, Petrisor Panaite, Mingchao Ji, Yuan Yuan Li, Ming Su

Proceedings Volume 12495, 124950X (2023) https://doi.org/10.1117/12.2662031

KEYWORDS: Design and modelling, Resolution enhancement technologies, Manufacturing, Lithography, Source mask optimization, Reconstruction algorithms, Printing, Yield improvement, Visual inspection, Very large scale integration

Read Abstract +

For the past few decades, PPA (performance, power, and area) demand of computation infrastructure has been driving exponential increase of chip density. In recent years, the challenges of printability and process window for advanced manufacturing node continuously motivated innovations in reticle enhancement techniques, notably the adoption of inverse lithography technology (ILT) and curvilinear mask. We have observed a few challenges: 1) ILT provides unmatched quality of results but does incur additional computation time to manage; 2) for curvilinear mask, though the benefits are evident, the associated data volume is very large; and 3) mask consistency remains a critical component for design manufacturability. To utilize the advanced RET techniques to their full potential, it is crucial to identify the repeating structures in design layout and reuse the correction result, getting three benefits at the same time: reducing mask preparation runtime, reducing mask data volume, and improving mask consistency. Conventional layout repetition analysis is based on native design hierarchy. However, in many cases, the input layout for mask synthesis flows is either completely stripped of hierarchy or contains sub-optimal hierarchy. Some layout hierarchy can be detected and reconstructed using manual methods such as using user generated pattern library of highly repeating structures in conjunction with pattern matching technology. However, the preparation of such libraries is a formidable effort, and a significant number of repetitions in designs will be overlooked by this approach. In this paper, we investigate the automatic detection of repeating geometry structures and formed a hierarchy that is optimized for mask synthesis. The detection supports any process layer and both Manhattan and all-angle designs. The engine detects repeating regions of arbitrary shape. The detected repeating structures can also be applied within the chip or across chips to accelerate correction to further improve mask consistency. By scaling well to hundreds of processors, the distributed hierarchy extraction is very efficient for a full chip layout. For highly repetitive layouts, mask synthesis runtime reduction of more than an order of magnitude has been observed by performing this hierarchy extraction.

Proceedings Article | 28 April 2023 Presentation + Paper

Evaluation of field stitching optimization for robust manufacturing with high-NA EUVL

Zachary Levinson, Thuc Dam, Paul Pfaeffli, C. Jay Lee, Wolfgang Hoppe, Ulrich Klostermann, Kevin Lucas

Proceedings Volume 12495, 124950B (2023) https://doi.org/10.1117/12.2659721

KEYWORDS: Reticles, Etching, Tolerancing, Extreme ultraviolet lithography, Simulations, Mirrors, Scanners, Manufacturing, Semiconducting wafers, Metals

Read Abstract +

Proceedings Article | 28 April 2023 Presentation + Paper

Process optimization for next generation high-NA EUV patterning by computational lithography techniques

Zachary Levinson, Thuc Dam, Pervaiz Kareem, C. Jay Lee, Wolfgang Demmerle, Ulrich Klostermann

Proceedings Volume 12494, 124940W (2023) https://doi.org/10.1117/12.2658580

KEYWORDS: Extreme ultraviolet, SRAF, Semiconducting wafers, Extreme ultraviolet lithography, Optical lithography, Scanners, Reflection, Lithography, Computational lithography, Process control

Read Abstract +

The lithography industry has historically striven to improve resolution by reducing wavelength and increasing the lens’ numerical aperture (NA). The introduction of 0.33 NA extreme ultraviolet (EUV) lithography into high-volume manufacturing (HVM) represents the largest jump in resolution ever achieved by the industry. However, even this resolution is not sufficient for the patterns required for beyond the 2 nm logic technology node. This is due to low contrast and the diffraction limit of current EUVL scanners for the mask patterns required for these nodes. Instead, the resolution must be improved by increasing the NA. This will also increase the contrast of patterns which had insufficient contrast at 0.33 NA, which will in turn improve LCDU and defectivity. This change is not without its challenges though. Increasing the NA from 0.33 to 0.55 will cause a significant reduction in depth of focus. In addition, stronger mask 3D effects can cause pattern dependent shifts in best focus. As a result, the common overlapping process window of several critical patterns can become strongly diminished. The use of anamorphic optics will require two separate half-field exposures to obtain the equivalent of a single full-field exposure on current EUV and DUV scanners. For some chip sizes, this will require stitching two half-fields together to pattern the full chip area. In previous technology nodes, the process window could be improved using SMO and SRAFs. In addition, over the last five years, the industry has put significant effort into studying alternative absorbing materials. These materials can significantly reduce the mask 3D effects by reducing the thickness of the absorber. The use of alternative absorbers alone will not be sufficient for improving the overlapping process window. Instead, several techniques must be simultaneously utilized in order to ensure sufficient overall process window. Optimization of overlapping process windows is critical for successful insertion of high-NA EUVL into HVM. In this paper we analyze how the process window of critical patterns can be optimized by using different optimizations. We will show for realistic mask designs how process window can be improved in different process steps. Double exposure from half-field stitching will also be included in the process evaluation. We use both rigorous and compact modeling in a complimentary fashion for overall process optimization analysis. All techniques presented in this paper accurately model the anamorphic, centrally obscured optics of the upcoming next-generation high-NA scanners.

Proceedings Article | 22 February 2021 Presentation + Paper

Ab initio for design-technology co-optimization

Shela Aboud, Joanne Huang, Jonathan Cobb, Tue Gunst, Plamen Asenov, Thuc Dam, Ricardo Borges

Proceedings Volume 11614, 116140S (2021) https://doi.org/10.1117/12.2583912

KEYWORDS: Metals, Standards development, Ruthenium, Performance modeling, Copper, Transistors, Scattering, Oscillators, Materials processing, Electronic design automation

Read Abstract +

Proceedings Article | 23 March 2020 Paper

Impact of flare on source mask optimization in EUVL for 7nm technology node

Lisong Dong, Rui Chen, Taian Fan, Rongbo Zhao, Yayi Wei, Jianjun Jia, Zac Levinson, Thuc Dam, Jay Lee, Yongdong Wang, Larry Melvin

Proceedings Volume 11323, 113232E (2020) https://doi.org/10.1117/12.2552008

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Source mask optimization, Nanoimprint lithography, Lithography, Extreme ultraviolet, Electroluminescence, Reflectivity, Critical dimension metrology, Light scattering

Read Abstract +

Proceedings Article | 23 March 2020 Paper

Proteus SMO for process window improvement

Kun-Yuan Chen, Andy Lan, Richer Yang, Jing Jing Liu, Ting Ting Xu, Cheng-Shuan Lin, Hua Ding, Chih-Jie Lee, Thuc Dam, Jianjun Jia

Proceedings Volume 11327, 1132711 (2020) https://doi.org/10.1117/12.2552230

KEYWORDS: Source mask optimization, Photomasks, Semiconducting wafers, Lithography, Nanoimprint lithography, Resolution enhancement technologies, Photovoltaics, Optical proximity correction, Optimization (mathematics), Scanning electron microscopy

Read Abstract +

Proceedings Article | 4 April 2017 Presentation + Paper

Cost effective solution using inverse lithography OPC for DRAM random contact layer

Jinhyuck Jun, Jaehee Hwang, Jaeseung Choi, Seyoung Oh, Chanha Park, Hyunjo Yang, Thuc Dam, Munhoe Do, Dong Chan Lee, Guangming Xiao, Jung-Hoe Choi, Kevin Lucas

Proceedings Volume 10148, 1014809 (2017) https://doi.org/10.1117/12.2257857

KEYWORDS: Lithography, Optical proximity correction, Optical lithography, Manufacturing, Photomasks, Semiconducting wafers, Atrial fibrillation, Source mask optimization, Image processing

Read Abstract +

Proceedings Article | 24 March 2017 Presentation + Paper

Resist 3D aware mask solution with ILT for hotspot repair

Kosta Selinidis, Wolfgang Hoppe, Thomas Schmoeller, Thuc Dam, Kevin Hooker, Guangming Xiao

Proceedings Volume 10147, 101470Q (2017) https://doi.org/10.1117/12.2257962

KEYWORDS: 3D modeling, Optical proximity correction, Optical lithography, Data modeling, Computational lithography, Optimization (mathematics), Photoresist processing, Source mask optimization, Scanning electron microscopy

Read Abstract +

Proceedings Article | 31 March 2014 Paper

Applying ILT mask synthesis for co-optimizing design rules and DSA process characteristics

Thuc Dam, William Stanton

Proceedings Volume 9052, 90521B (2014) https://doi.org/10.1117/12.2046370

KEYWORDS: Photomasks, Lithography, Source mask optimization, Photovoltaics, Calibration, Lens design, Process modeling, Performance modeling, Neck, Directed self assembly

Read Abstract +

Proceedings Article | 14 October 2011 Paper

Double patterning for 56 nm pitch test designs using inverse lithography

Thuc Dam, Robert Gleason, Paul Rissman, Robert Sinn

Proceedings Volume 8166, 81663Q (2011) https://doi.org/10.1117/12.900852

KEYWORDS: Photomasks, Lithography, Double patterning technology, Metals, Immersion lithography, Source mask optimization, Etching, Fiber optic illuminators, Manufacturing, SRAF

Read Abstract +

Proceedings Article | 14 October 2011 Paper

Exploring the impact of mask making constraints on double patterning design rules

Thuc Dam, Robert Sinn, Paul Rissman, Bob Gleason

Proceedings Volume 8166, 816629 (2011) https://doi.org/10.1117/12.896963

KEYWORDS: Photomasks, Lithography, Fiber optic illuminators, Double patterning technology, Mask making, Image segmentation, Back end of line, Source mask optimization, Computational lithography, Metals

Read Abstract +

In order to achieve an economical design-to-mask (DTM) development cycle in the low k1 domain, designers, lithographers, and mask makers needed to move away from many sequentially isolated developmental activities onto one collaborative environment managed by a computational lithography platform that integrates their respective ecosystems. ^1,2 A successful development cycle used to be achievable by designers providing designs to lithographers, who then provided RET/OPC solutions to realize designs, but once k1 fell below a certain level, the lithographers could not provide solutions to realize some critical designs, which then required feedback to designers for further redesigns requiring further lithographic evaluation cycles. So collaboration and automations between lithographers and designers became necessary to reduce feedback loops and development cycle time. RET and design solutions also were impacted by mask making, and so mask maker's feedback on MRC and other constraints needed to be integrated for all three groups to achieve an economical DTM. As many lithographers attempted to print sub-80 nm pitches with 193 nm wavelength, it became necessary to use double patterning to achieve feature resolution. With the effective pitch doubling on each split layer, there could be significant increased design rule freedom for certain complex design situations. Using an integrated computational lithographic platform, one could find design space sweet spots that could further achieve optimal lithographic performance. In this paper, the optimization of design rules (DRD) for double pattern designs (~60 nm pitch) was explored with the mask maker's perspective. The experiment to be presented started with a 2x nm design set of clips. Each set of clips underwent size/width/space/pitch variations to generate a design space, and then each design space underwent SMO with an inverse lithography technology (ILT) engine using various mask MRC's and manhattan segmentations. The lithographic results were analyzed with respect to MRC and manhattan segmentation to show their impact on design space and mask solutions.

Proceedings Article | 14 October 2011 Paper

Enabling virtual wafer CD (WCD) using inverse pattern rendering (IPR) of mask CD-SEM images

Thuc Dam, Dongxue Chen, Hsien-Min Chang, Noel Corcoran, Paul Yu, Linyong Pang, Chia-Wei Chang, Rick Lai, Peter Chang, Laurent Tuo

Proceedings Volume 8166, 81660O (2011) https://doi.org/10.1117/12.896951

KEYWORDS: Scanning electron microscopy, Photomasks, Semiconducting wafers, Calibration, Critical dimension metrology, Optical proximity correction, Image processing, Signal to noise ratio, Mask making, Holons

Read Abstract +

Proceedings Article | 23 March 2011 Paper

Comparison of clear-field and dark-field images with optimized masks

Robert Sinn, Thuc Dam, Bob Gleason

Proceedings Volume 7973, 79731V (2011) https://doi.org/10.1117/12.879533

KEYWORDS: Photomasks, Optical lithography, Current controlled current source, Lithography, Opacity, Performance modeling, Phase shifts, Source mask optimization

Read Abstract +

Proceedings Article | 29 September 2010 Paper

Lithographic plane review (LPR) for sub-32nm mask defect disposition

Vikram Tolani, Danping Peng, Lin He, George Hwa, Hsien-Min Chang, Grace Dai, Noel Corcoran, Thuc Dam, Linyong Pang, Laurent Tuo, C. J. Chen, Rick Lai

Proceedings Volume 7823, 78232G (2010) https://doi.org/10.1117/12.864284

KEYWORDS: Photomasks, Inspection, Lithography, Image restoration, Defect detection, Image transmission, Optical proximity correction, Image processing, Extreme ultraviolet, Scanning electron microscopy

Read Abstract +

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns under mask inspection optical conditions continues to diminish. Furthermore, as mask complexity and MEEF has also increased, it requires detecting even smaller defects in the already narrower pitch mask patterns. This leaves the mask inspection engineer with the option to either purchase a higher resolution mask inspection tool or increase the detector sensitivity on the existing inspection system or maybe even both. In order to meet defect sensitivity requirements in critical features of sub-32nm node designs, increasing sensitivity typically results in increased nuisance (i.e., small sub-specification) defect detection by 5-20X defects making post-inspection defect review non-manufacturable. As a solution for automatically dispositioning the increased number of nuisance and real defects detected at higher inspection sensitivity, Luminescent has successfully extended Inverse Lithography Technology (ILT) and its patented level-set methods to reconstruct the defective mask from its inspection image, and then perform simulated AIMS dispositioning on the reconstructed mask. In this technique, named Lithographic Plane Review (LPR), inspection transmitted and reflected light images of the test (i.e. defect) and reference (i.e., corresponding defect-free) regions are provided to the "inversion" engine which then computes the corresponding test and reference mask patterns. An essential input to this engine is a well calibrated model incorporating inspection tool optics, mask processing and 3D effects, and also the subsequent AIMS tool optics to be able to then simulate the aerial image impact of the defects. This flow is equivalent to doing an actual AIMS tool measurement of every defect detected during mask inspection, while at the same time maintaining inspection at high enough resolution. What makes this product usable in mask volume production is the high degree of accuracy of mask defect reconstruction, predicting actual AIMS measurements to within ±4% CD error for > 95% of defects while not missing any OOS (out-of-specification) defect and maintaining high simulation throughput of ≥250 defects/min on Luminescent's distributed computing platform. This technique enables inspection recipes to be setup based on the sensitivity required to detect small but lithographically-significant defects, even if in the process a large number of nuisance defects are detected. LPR is being implemented as an integral part of defect classification for high-volume sub-32nm technology nodes and higher. Furthermore, this technique will be essential to the lithographic disposition of defects detected on EUV masks inspected under non-actinic conditions.

Proceedings Article | 26 May 2010 Paper

Computational inspection applied to a mask inspection system with advanced aerial imaging capability

Amir Sagiv, Aviram Tam, Wolf Staud, Linyong Pang, Danping Peng, Lin He, Dongxue Chen, Thuc Dam, Vikram Tolani

Proceedings Volume 7748, 77480P (2010) https://doi.org/10.1117/12.868053

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Image restoration, Image resolution, Airborne remote sensing, Scanners, Lithography, Defect inspection, Imaging systems

Read Abstract +

Proceedings Article | 2 April 2010 Paper

Computational inspection applied to a mask inspection system with advanced aerial imaging capability

Linyong Pang, Danping Peng, Lin He, Dongxue Chen, Thuc Dam, Vikram Tolani, Aviram Tam, Wolf Staud

Proceedings Volume 7638, 76380V (2010) https://doi.org/10.1117/12.848615

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Image resolution, Lithography, Airborne remote sensing, Wafer-level optics, Optical proximity correction, Scanners, Data modeling

Read Abstract +

Proceedings Article | 11 March 2010 Paper

Toward a consistent and accurate approach to modeling projection optics

Danping Peng, Peter Hu, Vikram Tolani, Thuc Dam, Jacek Tyminski, Steve Slonaker

Proceedings Volume 7640, 76402Y (2010) https://doi.org/10.1117/12.848252

KEYWORDS: Photomasks, Diffraction, Projection systems, Polarization, 3D modeling, Near field, Einsteinium, Near field optics, Spherical lenses, Semiconducting wafers

Read Abstract +

Proceedings Article | 10 March 2010 Paper

Optimization from design rules, source and mask, to full chip with a single computational lithography framework: level-set-methods-based inverse lithography technology (ILT)

Linyong Pang, Danping Peng, Peter Hu, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7640, 76400O (2010) https://doi.org/10.1117/12.848145

KEYWORDS: Source mask optimization, Photomasks, Lithography, SRAF, Optical proximity correction, Photovoltaics, Optimization (mathematics), Logic, Semiconducting wafers, Computational lithography

Read Abstract +

Proceedings Article | 10 March 2010 Paper

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

Yi Zou, Yunfei Deng, Jongwook Kye, Luigi Capodieci, Cyrus Tabery, Thuc Dam, Anthony Aadamov, Ki-Ho Baik, Linyong Pang, Bob Gleason

Proceedings Volume 7640, 76400L (2010) https://doi.org/10.1117/12.848479

KEYWORDS: Photomasks, Lithography, Source mask optimization, SRAF, Fiber optic illuminators, Metals, Optical proximity correction, Atrial fibrillation, Logic, Optimization (mathematics)

Read Abstract +

Proceedings Article | 4 March 2010 Paper

Source-mask optimization (SMO): from theory to practice

Thuc Dam, Vikram Tolani, Peter Hu, Ki-Ho Baik, Linyong Pang, Bob Gleason, Steven Slonaker, Jacek Tyminski

Proceedings Volume 7640, 764028 (2010) https://doi.org/10.1117/12.848257

KEYWORDS: Source mask optimization, Photomasks, Photovoltaics, Fiber optic illuminators, Fluctuations and noise, Polarization, Lithography, Scanners, Optimization (mathematics), Calibration

Read Abstract +

Proceedings Article | 12 December 2009 Paper

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

Linyong Pang, Peter Hu, Danping Peng, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7520, 75200X (2009) https://doi.org/10.1117/12.843578

KEYWORDS: Source mask optimization, Photomasks, SRAF, Lithography, Optical proximity correction, Photovoltaics, Optimization (mathematics), Logic, Semiconducting wafers, Manufacturing

Read Abstract +

Proceedings Article | 13 March 2009 Paper

Exploration of complex metal 2D design rules using inverse lithography

Simon Chang, James Blatchford, Steve Prins, Scott Jessen, Thuc Dam, Guangming Xiao, Linyong Pang, Bob Gleason

Proceedings Volume 7275, 72750D (2009) https://doi.org/10.1117/12.814197

KEYWORDS: Metals, Lithography, Photomasks, Optical lithography, Logic, Raster graphics, Resolution enhancement technologies, Computer simulations, Distributed computing, Visualization

Read Abstract +

As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as "hotspots." This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation. Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution. We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

Proceedings Article | 17 October 2008 Paper

Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)

Linyong Pang, Guangming Xiao, Vikram Tolani, Peter Hu, Thomas Cecil, Thuc Dam, Ki-Ho Baik, Bob Gleason

Proceedings Volume 7122, 71221W (2008) https://doi.org/10.1117/12.803801

KEYWORDS: Photomasks, Source mask optimization, Lithography, SRAF, Logic, Semiconducting wafers, Resolution enhancement technologies, Photovoltaics, Image processing, Optical proximity correction

Read Abstract +

Proceedings Article | 19 March 2008 Paper

Validation and application of a mask model for inverse lithography

Thuc Dam, Xin Zhou, Dongxue Chen, Anthony Adamov, Danping Peng, Bob Gleason

Proceedings Volume 6925, 69251J (2008) https://doi.org/10.1117/12.773081

KEYWORDS: Finite-difference time-domain method, Calibration, Photomasks, SRAF, 3D modeling, Panoramic photography, Lithography, Image processing, Polarization, Image transmission

Read Abstract +

Proceedings Article | 17 March 2008 Paper

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection

Steve Prins, James Blatchford, Simon Chang, Lewis Flanagin, Scott Jessen, Sean O'Brien, Guangming Xiao, Timothy Lin, Thuc Dam, Bob Gleason

Proceedings Volume 6925, 69250E (2008) https://doi.org/10.1117/12.774581

KEYWORDS: Lithography, SRAF, Photomasks, Logic, Optical proximity correction, Lithographic illumination, Printing, Critical dimension metrology, Design for manufacturing, Model-based design

Read Abstract +

Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Proceedings Article | 12 March 2008 Paper

Validation of inverse lithography technology (ILT) and its adaptive SRAF at advanced technology nodes

Linyong Pang, Grace Dai, Tom Cecil, Thuc Dam, Ying Cui, Peter Hu, Dongxue Chen, Ki-Ho Baik, Danping Peng

Proceedings Volume 6924, 69240T (2008) https://doi.org/10.1117/12.775084

KEYWORDS: SRAF, Photomasks, Optical proximity correction, Semiconducting wafers, Lithography, Lithographic illumination, Imaging devices, Inverse problems, Scanners, Fiber optic illuminators

Read Abstract +

Proceedings Article | 7 March 2008 Paper

Evaluation of inverse lithography technology for 55nm-node memory device

Byung-ug Cho, Sung-woo Ko, Jae-seung Choi, Cheol-Kyun Kim, Hyun-jo Yang, DongGyu Yim, David Kim, Bob Gleason, KiHo Baik, Ying Cui, Thuc Dam, Linyong Pang

Proceedings Volume 6924, 692438 (2008) https://doi.org/10.1117/12.772515

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, SRAF, Scanners, Atrial fibrillation, Calibration, Optimization (mathematics), Distance measurement

Read Abstract +

Proceedings Article | 20 October 2006 Paper

PAB and PEB temperature gradient methodology for CAR optimization

Thuc Dam, Andrew Jamieson, Maiying Lu, Ki-Ho Baik

Proceedings Volume 6349, 634906 (2006) https://doi.org/10.1117/12.692939

KEYWORDS: Scanning electron microscopy, Photomasks, Scatterometry, Photoresist processing, Semiconducting wafers, Critical dimension metrology, Diffractive optical elements, Diffusion, Metrology, Scatter measurement

Read Abstract +

Proceedings Article | 20 May 2006 Paper

The design and qualification of the TEL CLEAN TRACK ACT M photomask coating tool at Intel

Andrew Jamieson, Thuc Dam, Ki-Ho Baik, Ken Duerksen, Elie Eidson, Keiji Akai, Kazuya Hisano, Norifumi Kohama, Shinichi Machidori

Proceedings Volume 6283, 62831P (2006) https://doi.org/10.1117/12.681751

KEYWORDS: Photomasks, Coating, Manufacturing, Photoresist processing, Semiconducting wafers, Head, Ultraviolet radiation, Particles, Thin film coatings, Wafer manufacturing

Read Abstract +

Proceedings Article | 28 August 2003 Paper

SMIF capability at Intel Mask Operation improves yield

Thuc Dam, Matt Pekny, Jim Millino, Gibson Luu, Nitesh Melwani, Aparna Venkatramani, Malahat Tavassoli

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504267

KEYWORDS: Reticles, Inspection, Coating, Particles, Yield improvement, Thin film coatings, Photoresist processing, Particle contamination, Etching, Robotics

Read Abstract +

Showing 5 of 33 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years