The human quest for visual perfection has touched almost every area of earthly endeavour - from art and bodybuilding to architecture and automobiles - even technology. Eelctronic displays attempt to recreate the visual perfection of the natural world in a synthetic environment. Some succeed, e.g., the CRT and LCD, while other fail, sometimes ignominiously, sometimes with great spectacle. Some "killer" technologies look very promising in their early days of development, but never take off, or end up occupying only a niche market. In some fields there can be technology battles between rivals with one technology losing, yet the field itself, nevertheless, grows rapidly on the success of the winner. A classic example of this was the videocassette recorder, where the end product is now ubiquitous, but the battle amongst the main contenders - VHS, Betamax, and Video2000 - looked like a true struggle for technological supremacy. However many onlookers, and even the market itself, saw other factors in the eventual winner that drove it to the forefront. Picking the winners, and accurately predicting the percentage inroad of new technologies has never been easy and continues to be a difficult proposition.

Formation of TFTs inside location-controlled large Si grains with a low temperature process is an attractive approach for realizing system-circuit integration with displays on a large glass substrate. Local structural variations of the substrate using photolithography allows an accurate location-control of the large Si grains in excimer-laser crystallization. Single-crystalline Si (c-Si) TFTs was formed inside a location-controlled large (6 μm) grain by μ-Czochraski process of a-Si film. The c-Si TFTs showed field effect mobility of 450 cm²/Vs on average. Crystallization characteristics, spread of the TFT characteristics and effects of process parameters will be reviewed and discussed.

Crystallization of thin Si-films using excimer lasers is a well introduced technique to the manufacturing process of flat panel display poly-Si back plates. The crystallization is performed by a Line Beam exposure which is scanned with a typical overlay of 95% over the Si-coated glass plate. The poly-Si film is obtained with a very good homogeneity of typically 100-150 cm²/Vs electron mobility. Thus this performance is of importance for the system on glass (SOG) driver microelectronic circuits and is a key technology for high resolution (200ppi) LCD displays for mobile phones, personal digital assistance (PDA) and for the near future OLEDs (organic light emitting display). A recently considered process to obtain even improved performance poly-Si films is the sequential lateral solidification proposed by J. Im of Columbia University. This process requires a high resolution lines and spaces pattern which is designed to grow linear crystals or even single crystal like areas. High resolution optics for high power throughput is the relevant technique to introduce the SLS-process (sequential lateral solidification) into next generation production lines.

Polycrystalline silicon (p-Si) thin film transistors (TFTs) were fabricated using a high temperature process that included solid phase crystallization (SPC) and dry thermal oxidation with excimer laser annealing (ELA). Raman spectroscopy, X-ray diffraction and transmission electron microscopy analyses showed that the ELA process improved the quality of p-Si films markedly. The p-Si TFTs exhibited higher performance than the SPC p-Si TFTs. The field effect mobility for n-type self-aligned TFT was (formula available in paper). The longitudinal junction diffusion length of the p-Si TFTs was shorter than that of the SPC p-Si TFTs. This is favorable for fine design rules. If optimization of amorphous silicon (a-Si) deposition and SPC conditions enables the grains of p-Si films to grow larger than the channel length and the positions of the grain boundaries are controlled, this process will produce great scaling rule merits such as single-grain Si TFTs. This fabrication process is consistent with the high temperature p-Si TFT development trend towards using large substrates, low temperatures, and fine design rules. High temperature p-Si TFTs are expected to be used in LSI circuits as silicon-on-insulator (SOI) devices in the future.

We have developed a new crystallization technique using the EO-modulated CW-laser (LD-pumped Nd:YVO4 SHG λ=532nm). Enlarging of lateral crystallization is attained by rapid laser-scanning on Si surface where the large (4μm × 0.5μm in average) columnar grains are uniformly obtained. Sequential and step-by-step scanning makes large crystallization areas. During the each scanning, the irradiation is frequently suspended by pulse-like modulation. By using this technique, in-plane tensile strain in the irradiated areas is relieved. The size and the crystal orientation ({110} normal to the substrate and {100} normal to the growth direction) of obtained grains are, therefore, rather homogeneous. We have developed the crystallization technique, which can obtain high crystal quality as well as large grains in the selected areas. We have fabricated TFTs (typically W/L=4μm/2-4μm, t_ox=100nm, t_Si=50nm) in the irradiation areas on the glass-substrate. The field-effect mobility is 480 cm²/Vs for n-channel devices and 130 cm²/Vs for p-channel devices, respectively. The sub-threshold swing (S-value) is less than 0.2 V/dec for both types. This technology gives possibility to integrate electronic systems on the glass.

In this paper, we focus on a variation of the 2-shot sequential lateral solidification (SLS) process for crystallization of thin Si films for TFT applications. The resulting microstructure is engineered to reduce the large discrepancy in directionality of the TFTs with respect to the lateral growth direction. Through this method, we are able to improve the mobility directionality ratio between devices with majority carrier flow parallel and perpendicular to the lateral growth direction, respectively, from 0.3 to over 0.7. Further post-SLS process thinning and planarization of the Si surface is used to improve the uniformity of device characteristics.

Low-temperature polycrystalline silicon (poly-Si) is today a promising material allowing the production of large-area thin-film transistor (TFT’s) displays. High-performance poly-Si TFT’s are currently obtained using a pulsed excimer laser beam to crystallize the amorphous deposited silicon (a-Si) film on a glass substrate. The final quality of the poly-Si devices depends on several key parameters such as the laser energy density, the beam homogeneity and the number of laser shots. However, rapid quality control is needed to optimise and stabilize the crystallization process. In this work, the micro structural evolution of the crystallized area with the laser annealing conditions and the formation in the Super Lateral Growth (SLG) region of large grain poly-Si have been investigated by interference microscopy. Phase Stepping Microscopy (PSM), which allows nanometric measurement of surface morphology, has been used to follow the annealing process in Si thin films on glass irradiated using a large area (~ 40 cm²) and long pulse duration (200 ns) excimer (XeCl) laser. The results of the surface morphology obtained by interference microscopy and confirmed by Atomic Force Microscopy (AFM) attest to the PSM technique being one of the most interesting alternative ways that could be used for the calibration of the laser annealing process in an industrial environment.

A model for projection laser crystallization of thin silicon films has been developed. The model is capable of simulating stochastic nucleation and grain growth to predict the extent of lateral growth (LG) in the film and the details of the final microstructure. This model was used to simulate irradiation schemes involving multiple pulses, designed to increase the lateral growth length (LGL) in the irradiated domain. For an irradiation scheme involving two pulses, with an adjustable time delay, our simulation predicted a maximum increase in LGL of about 50% (from 2μm to 3μm) with a maximum film temperature of ~2700 K. For a three-pulse irradiation scheme (without time delay) a 50% increase in LGL was also predicted, but with a maximum film temperature of ~2200 K. These simulations show the efficacy and the relative merit of each of the examined schemes, as well as, their associated process window.

Industrial production of low temperature p-Si back plates for LCDs by high power excimer laser annealing was introduced several years ago. Regarding the economy of the process, one of the major advantages of excimer laser annealing is the opportunity to make use of low cost glass substrates due to the low temperature of the annealing process. The Lambda Physik high power excimer laser series are operated with the MicroLas 370 mm line beam optics, integrated by Japan Steel Works into industrial systems. The MicroLas line beam optics for conventional excimer laser annealing (ELA) process converts the raw laser beam profile into a stable and homogeneous rectangular illumination field with high aspect ratio. The excimer laser light source, the LAMBDA STEEL 1000, delivers stabilized pulse energies up to 1 Joule at repetition rates up to 300Hz. The crystallization using excimer lasers allows to produce films with electron mobility of 100-150 cm²/Vsec with the Line beam technique. The new SLS-method, which is currently under industrial investigation, even allows to obtain electron mobility between 200-400 cm²/Vsec.

Large-area microelectronic applications require high-performance thin-film transistors for driver circuits. This is especially true in the case of "system-on-panel" applications where high levels of circuit integration are required to drive displays and sensors that are built onto the panel. While there are many methods that might be employed to crystallize Si films on lost-cost, high-temperature-intolerant substrates, very few offer the high performance characteristics that the applications demand. In this paper, we show that directionally solidified Si films can be readily used to fabricate high performance electronic devices for circuit applications. By only crystallizing those regions of the Si films that are used in the actual fabrication of TFTs, we show that many of the issues concerning low throughput rates can be avoided. Results from a CMOS ring oscillator showcasing the speed capability of such active layers are also presented.

Top gate and bottom gate microcrystalline silicon thin film transistors (TFTs) have been produced by the radio frequency glow discharge technique using three preparation methods: the standard hydrogen dilution of silane in hydrogen, the use of the layer-by-layer technique, and the use of SiF₄-Ar-H₂ feedstock. In all cases, stable top gate TFT with mobility values around 1 cm²/V.s have been achieved, making them suitable for circuit on glass applications. Moreover, the use of SiF₄ gas combined with specific treatments of the a-SiN:H dielectric in bottom gate TFTs, fully compatible with today's a-Si:H process, lead to lateral growth of the silicon crystallites and an enhancement of the mobility to reach stable values of around 3 cm²/V.s.

For laser crystallization of amorphous silicon, plasma enhanced chemical vapor deposition (PECVD) is the method of choice for a-Si precursor deposition. This situation is likely to change, however, with the transition to higher performance polysilicon material produced via advanced laser annealing techniques. Two factors make the use of sputtered a-Si precursors particularly attractive for laser annealing technologies. First, owing to their low hydrogen content, sputtered a-Si films are uniquely suited as precursors for laser crystallization techniques. Second, the ability to dope the target material (and thus produce doped silicon films) allows for control of the threshold voltage of the resulting TFTs. To that end we evaluated sputter deposited doped silicon as an a-Si precursor for excimer laser annealing. We established process conditions necessary to shift the Vth of both N and P transistors such that they were centered near zero. In addition we determined levels of target doping, DC power, and chamber pressure that produced TFT's with balanced N and P Vth values and satisfactory mobility. We also found that the off-state leakage and subthreshold slope of the PVD films were better than PECVD deposited films.

We report on the fabrication and characterization of SiO₂ thin films by high-density plasma enhanced chemical vapor deposition (HD-PECVD) technique at a processing temperature lower than 400°C for gate dielectric applications in thin film transistor (TFT) devices. An inductively coupled plasma source was used to couple the rf power to the top electrode. The SiO₂ thin films were fabricated on p-Si wafers using nitrogen, nitrous oxide, and silane precursors. The deposition process was optimized in terms of the effects of rf power, gas flow rates, and system pressure on deposition rate, chemical etch rate, optical properties, and electrical characteristics. The effects of the processing variables on the refractive index, Si-O bond formation, and impurity related bonds were analyzed. The electrical properties of the films were evaluated from the I-V and C-V characteristics of the MOS capacitors. The effects of the SiO₂ film thickness on the electrical characteristics of MOS capacitors were also investigated in the range of 30-100 nm. The influence of the low temperature processed gate dielectric on the performance of 500 Å poly-Si TFTs was evaluated in terms of the transfer and gate leakage characteristics. The microstructural and electrical characteristics of the HD-PECVD deposited SiO₂ thin films suggest their suitability for the low temperature integration of TFTs on glass or other low temperature substrates.

High-efficiency electrophosphorescent organic light emitting devices (OLEDs), based on triplet emission, is an enabling technology for low power full-color OLED displays. In addition, top emission OLED architectures can be used to maximize display aperture ratio and pixel current densities. In this paper we report on recent results in red, green and blue phosphorescent and top emission OLEDs and discuss the benefits that these attributes have on both active and passive matrix display performance.

Philips have been actively developing polymer OLED (poly-LED) displays as a future display technology. Their emissive nature leads to a very attractive visual appearance, with wide viewing angle, high brightness and fast response speed. Whilst the first generation of poly-LED displays are likely to be passive-matrix driven, power reduction and resolution increase will lead to the use of active-matrix poly-LED displays. Philips Research have designed, fabricated and characterized five different designs of active-matrix polymer-LED display. Each of the five displays makes use of a distinct pixel programming- or pixel drive-technique, including current programming, threshold voltage measurement and photodiode feedback. It will be shown that hte simplest voltage-programmed current-source pixel suffers from potentially unacceptable brightness non-uniformity, and that advanced pixel circuits can provide a solution to this. Optical-feedback pixel circuits will be discussed, showing that they can be used to improve uniformity and compensate for image burn-in due to polymer-LED material degradation, improving display lifetime. Philips research has also been active in developing technologies required to implement poly-LED displays on flexible substrates, including materials, processing and testing methods. The fabrication of flexible passive-matrix poly-LED displays will be presented, as well as the ongoing work to assess the suitability of processing flexible next-generation poly-LED displays.

Conventionally, small-molecule organic electroluminescent device is fabricated by vacuum depositing technology. In this paper, a novel small-molecule organic electroluminescent device was proposed. We adopt spin-coating technology to fabricate the device. It makes the fabrication of small-molecule organic electroluminescent device very simple and low-cost. The device has a brightness of 100 cd/m² at the 16V DC drive voltage.

Performance and relating subject for fine patterned Si TFT (Thin Film Transistor) are reviewed and discussed from a viewpoint of device and/or fabrication process based on reported results. Poly-Si TFTs fabricated on glass using low-temperature process are studied extensively for the application to LCD (Liquid Crystal Display) or OLED (Organic Light Emitting Diode) Display. Currently, the research target for the TFT application is emphasized on the highly functional system on glass or the display on flexible substrate by adopting an effective crystallizing technique of SPC (Solid Phase Crystallization) or ELC (Excimer Laser Crystallization). Improvement of device characteristics such as an enhancement of carrier mobility has been studied intensively by enlarging the grain size. Reduction of the voltage and shrinkage of the device size are the trend of Si LSI, which arise a peculiar issue of uniformity or an anisotropy problem for the device characteristics in the large grained poly-Si film. Some trial approaches for solving the issues such as nucleation control for the grain growth or lateral grain growth are proposed, so far. By overcoming the issues, coming SOP (System on Panel) era using the Si TFTs is expected.

Two different drain field relief architectures, lightly doped drain (LDD) and gate overlapped LDD (GOLDD), for polysilicon TFT have been analyzed and compared to conventional self-aligned (SA) devices. The introduction of LDD regions improves off-current, kink effect and electrical stability if compared to SA devices. However, a parasitic resistance effect is also introduced, thus limiting the benefits of LDD structures. GOLDD architecture overcomes this drawback, but, more importantly, show improved off-current and kink effect and exceptionally high electrical stability. The experimental results have been explained by analyzing the electric field distributions, obtained by two-dimensional numerical simulations, while a new tool to explain hot-carrier induced modifications in polysilicon TFTs was developed.

We report a new method for characterizing trap generation-recombination processes in Polysilicon TFTs. A small AC voltage was superimposed on a DC gate voltage and the ac current was measured at the source. A theoretical model has been developed, whereby n-channel TFTs have been analysed. A resonant peak in the imaginary part of the ac current and a corresponding step in the real part were found at the frequency of 147Hz. Our data indicate that the ac response is dominated by a single trap level. By combining the ac current measurement with low frequency capacitance measurement, we have determined the trap energy, capture cross section, trap density to be respectively 0.35eV above midgap, 3.1x10^-21cm², 5.7x10¹⁵ cm^-3.

The non-linear transmission / voltage characteristic of the pixels of a liquid crystal display (LCD) must be corrected for during the digital-to-analogue conversion of image data. This process of gamma correction is conventionally performed by a combination of a digital look-up table and a linear digital-to-analogue converter (DAC) with a bit resolution, m, greater than the bit depth, n, of the digital image (m>n). We present a new method of LCD gamma correction based upon a carefully optimised non-linear DAC with a bit resolution of only n. By reducing DAC complexity we are able to reduce circuit area and move towards our vision of a fully integrated CGS, system-on-panel LCD.

In recent years, there has been a growing interest in microelectronic fabrication of thin, flexible substrates. The utilization of flexible materials in processing is motivated by the need to have low weight, high strength microelectronic circuitry compatible with roll-to-roll processing. This can lead to a new era in the fabrication of reliable, low cost and highly versatile circuits for a wide variety of applications. This metal foils offer a number of significant advantages over polymers, their main contender in this field. The most important asset of metals for substrate application is their compatibility with high temperature processing (up to 1000°C), which can lead to high mobility, low drift devices. This paper examines the performance of a variety of circuits fabricated on flexible metal foils, such as stainless steel, using laser crystallized polycrystalline silicon films. The basic performance characteristiscs and architecture of fabricated static and dynamic shift registers and ring oscillators are discussed. N-channel thin film transistors with an average mobility of 200cm²/Vs were measured. Ring oscillator measurements indicated an average propagation delay of 1.38ns per inverter stage at a supply voltage of 15V. Both static and dynamic shift registers exhibit a maximum clock frequency beyond 1MHz. These circuits play a pivotal role for the fabrication of integrated display systems and most other large area electronics. This is the first time circuits of this complexity and performance have been successfully fabricated on flexible metal substrates.

Our motivation is to realize CMOS on plastic foil. We report the development of thin film transistors (TFTs) made of nanocrystalline silicon (nc-Si:H). nc-Si:H is compatible with present a-Si:H thin film technology. Because of the structural evolution of nc-Si:H with film thickness, it requires extensive experimentation with device geometry. For comparison we fabricate TFTs in (a) conventional coplanar top-gate, top-source/drain geometry and (b) staggered top-gate, bottom source/drain geometry. A seed layer is introduced in the latter case serves to develop the crystallinity of the intrinsic channel layer. While the coplanar geometry provides the shortest carrier path in the most crystalline channel region, the inverted staggered geometry ensures that the active channel is formed in the last-to-grow nc-Si:H layer, and also avoids exposure of the channel to reactive ion etching (RIE). The highest process temperature is 150°C. Both intrinsic and doped nc-Si:H layers are grown by plasma-enhanced chemical vapor deposition with an excitation frequency of 80MHz. Present p-channel TFTs reach a hole field-effect mobility of ~ 0.2 cm²V^-1s^-1 in the staggered geometry, and an electron field-effect mobility of ~ 40 cm²V^-1s^-1 in both geometries. These results suggest that directly deposited nc-Si:H is an attractive candidate material for CMOS capable electronics on plastic substrates.

Thin metal foils present an excellent alternative to polymers for the fabrication of large area, flexible displays. Their main advantage spurs from their ability to withstand higher temperatures during processing; microelectronic fabrication at elevated temperatures offers the ability to utilize a variety of crystallization processes for the active layer of devices and thermally grown gate dielectrics. This can lead to high performance (high mobility, low threshold voltage) low cost and highly reliable thin film transistors. In some cases, the conductive substrate can also be used to provide power to the active devices, thus reducing layout complexity. This paper discusses the first successful attempt to design and fabricate a variety of active matrix organic light emitting diode displays on thin, flexible stainless steel foils. Different pixel architectures, such as two- and four-transistor implementations, and addressing modes, such as voltage- or current-driven schemese are examined. This work clearly demonstrates the advantages associated with the fabrication of OLED displays on thin metal foils, which - through roll-to-roll processing - can potentially result in revolutionizing today's display processing, leading to a new generation of low cost, high performance versatile display systems.