This PDF file contains the front matter associated with SPIE Proceedings Volume 7470, including the Title Page, Copyright information, Table of Contents, Introduction, Meeting Sponsors, and Conference Committee listing.

For the 32 and 22 nm half-pitch nodes of the International Technology Roadmap for Semiconductors, the industry will face the challenge of introducing new lithography technologies into manufacturing. Some can build on the extension of current optical lithography technologies. However, others require a tool, optics, mask, and resist infrastructure quite different from those supporting today's manufacturing. Developing new technology solutions for use in manufacturing takes a long time and the final stages of infrastructure development and commercialization are very costly. The readiness of lithography technologies needs to be assessed based on development progress, but it also needs to consider whether a technology receives the necessary support to intersect a given technology node. In addition to being technically challenging, enabling an infrastructure capable of supporting pilot line and then high volume manufacturing insertion on an aggressive timeline is also a significant business challenge. To share the risk and cost, the industry must consider new business models for efficient collaboration with tool and infrastructure suppliers on the one side and device manufacturers on the other.

Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top critical issues. A survey was created with support from SEMATECH to gather information about the mask industry as an objective assessment of its overall condition. This year's survey data were presented in detail at BACUS and the detailed trend analysis presented at EMLC. The survey is designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's assessment is the seventh in the current series of annual reports. With continued industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments on critical path issues. This year's survey is basically the same as the surveys in 2005 through 2007. Questions are grouped into seven categories: General Business Profile Information, Data Processing, Yields and Yield Loss, Mechanisms, Delivery Times, Returns, and Services. (Examples are given below). Within each category is a multitude of questions that creates a detailed profile of both the business and technical status of the critical mask industry.

An advanced photomask is rarely made meeting all specifications in one attempt. In the photomask industry, yield is the critical component to all key performance measures including cost and delivery time. Defect-free advanced masks are extremely difficult to manufacture but leading-edge masks simultaneously meeting atomic level pattern placement, angstrom level CD uniformity, and defectivity to virus size sensitivity are a rarity. While the patterning and inspection segments have been the long-time nemeses of cost, the ideal mask fabrication process will perform these operations only once per mask order. To enable this, mask salvage processes are essential. Defects are the primary priority and are addressed with cleaning and repair techniques of various types targeted to needs. CD uniformity is addressed with predictive and feedback mapping techniques. CD uniformity is also addressed with post-mask fabrication gray-mask correction and dose correction at the scanner. Mask pattern placement correction by systematic error mapping is done but post-mask-patterning correction represents an opportunity for salvage process development. Until consistently superior mask registration can be achieved during or after patterning, self-aligned wafer processing will continue to be the primary enabling method for optical double-exposure while normal scaling issues will challenge EUV mask development. It is the ability to perform the high-cost operations only once to create each mask and then recover individual specification parameters with salvage operations which will differentiate mask makers in the future.

Defect free masks are a critical component to enable extreme ultraviolet lithography (EUVL). It is projected EUVL will be inserted for the 22nm hp node with a timeframe of 2012-2013 for leading IC manufacturers. To meet the goal of defect free masks, a concerted effort is required with emphasis on mask blank development and mask infrastructure readiness. With this in mind, SEMATECH mask program has been uniquely positioned to make important contributions to these areas. Together with several partners, an overall strategy has been defined focused on meeting EUVL mask requirements including setting mask standards and enabling the mask-making infrastructure. This paper will highlight the overview of key projects and accomplishments from the mask blank development program. It is critical that SEMATECH and its partners be ready to meet the overall pilot line defect density requirement of 0.04 defects/cm² at 18nm defect sensitivity by the end of 2010. Although important progress has been made, much work remains to meet these challenging goals.

Within our paper we are going to discuss the variation within the patterning process in the context of the overall electrical parameter variation in an advanced logic Fab. The evaluation is based on both the variation of ring oscillators that are distributed across the chip as well as on local variation of matched transistor pairs. Starting with a view back to the 130nm technology, we will show how things and requirements changed over time. In particular we focus on the gate layer where we do a detailed ACLV-comparison from the 130nm technology node down to today's 45nm node. Within the patterning variation we keep special attention on the mask performance. Within that section, we do a detailed wafer-mask correlation analysis. Additionally to the low-MEEF gate layer we show the importance of the mask CD-performance for a typical high MEEF-layer. Finally, we discuss the mask contribution to the overall overlay error for the most critical contact to gate overlay. In all of the cases, we will show that the mask performance is not the limiter within today's most advanced technology, as long as we get access to a world class mask shop.

This paper presents an extended Abbe based imaging algorithm for faster and more accurate simulations of current and future projection lithography systems. The basics of the physical model and several methods for the evaluation of the new image simulation software are explained. The comprehensive evaluation of the new image simulation software includes convergence tests, comparisons with analytical results, and various methods for the assessment of computed imaging results in terms of intensity difference plots, simulated linewidths, and image slopes. Tests include simulations for two- and three-dimensional thin and rigorous simulated masks, scalar and vectorial computations of intensity distributions in air/immersion liquid (aerial images) and photoresist (bulk images), respectively. The test scenarios range from special settings which result in simple two-beam interferences to large area simulations of more complex mask layouts. The excellent accuracy and computational performance of the new imaging algorithm is demonstrated by a comparison with the well-established imaging algorithm of Fraunhofer IISB. The new imaging algorithms are integrated in the research and development lithography simulator Dr.LiTHO of Fraunhofer IISB.

The Semi Conductors manufacturing processes have been, over the years, striving to shrink the dimensions of the devices that can be realized on silicon wafers from one technology node to the next. Utilization of optical lithography in the manufacturing process has enabled predictable process adjustments that can be put in place to allow for the next generation of smaller silicon devices. However after reaching ArF wavelength for source illumination, it became obvious that moving to the next smaller wavelength would cost a lot. Innovative Resolution Enhancement Techniques had to be researched, developed and implemented to enable the dimension shrink while utilizing the same illumination wavelength. Double patterning is among the techniques that can enable devices of 45nm and below dimensions. The technique relies on decomposing the exposure mask into two masks; each of the decomposed masks will have a relaxed mask features' pitch compared to the original mask, such that the relaxed pitches are resolvable by the illumination process. In this paper we present an implementation of a fast algorithm for pitch splitting of contact and via layer.

Double Patterning Technology (DPT) is now considered as the mainstream technology for 32 nm node lithography. The main DPT processes have been developed according targeted applications: spacer and pitch splitting either by dual line or dual trench approaches. However, the successful implementation of DPT requires overcoming certain technical challenges in terms of exposure tool capability, process integration, mask performance and finally metrology (1, 2). For pitch splitting process, the mask performance becomes critical as the technique requires a set of two masks (3). This paper will focus on the mask impact to the global critical dimension (CD) and overlay (OVL) errors for DPT. The mask long-distance and local off target CD variation and image placement were determined on DP features at 180 nm and 128 nm pitches, dedicated to 45 nm and 32 nm nodes respectively. The mask data were then compared to the wafer CD and OVL results achieved on same DP patterns. Edge placement errors have been programmed on DP like-structures on reticle in order to investigate the offsets impact on CD and image placement. The CD lines increases with asymmetric spaces adjacent to the drawn lines for offsets higher than 12 nm, and then have been compared to the corresponding density induced by individual dense and sparse symmetric edges and have been correlated to the simulated prediction. The single reticle trans-X offsets were then compared to the impact on CD by OVL errors in the double patterning strategy. Finally, the pellicle-induced reticle distortions impact on image placement errors was investigated (4). The mechanical performance of pellicle was achieved by mask registration measurements before and after pellicle removal. The reticle contribution to the overall wafer CD and OVL errors budgets were addressed to meet the ITRS requirements.

Within the frame of the European R&D project the so called "HYMNE" project, lead by STM, advanced vacuum decontamination processes had been demonstrated to be efficient on wafer substrates in order to remove airborne molecular contamination (moisture, VOC..), to avoid crystalline defects after dry etching process and to improve yield for sub 90 nm technologies. Further to these significant results on wafers, a pool of partners investigated new methods and processes based on vacuum technology for photomask decontamination. These studies were carried out in the frame of the European R&D CRYSTAL project, focusing on photomask defect reduction. Today, vacuum process is not very widespread in photomask environment: in fab environment nor in mask manufacturing cycle. However such vacuum substrate decontamination could be also efficiently applied in order to reduce AMC contamination, which is one of the root causes of haze and crystalline defects. In this paper, we report for the first time, vacuum process investigations on pellicled photomasks that could be applied in fab environment, as well as vacuum process investigations on patterned blank that could be integrated into mask manufacturing cycle. First, vacuum process had been investigated on pellicled photomasks, including parameter influences. Goal is to renew and replace the environment under the pellicle by clean environment. During the process, specific care has to be taken on pellicle behavior under vacuum. The challenge is indeed to manage the pellicle during the vacuum process without damaging it, especially after several decontamination cycles. Finally, repeatability tests have also been successfully carried out and will be reported. We also report advanced vacuum process on patterned blank that could be integrated into mask manufacturing flow. Such procedure is an efficient complementary process in order to outgas contaminants from photomasks, and in order to reduce AMC residues (especially sulfate) in mask manufacturing cycle. Experimental results will be reported.

The cleaning processes used today for photomasks were developed over decades and optimized to fulfill customer specifications. Some mask procedures were adapted from wafer cleaning technology. A principal technique, megasonic (MS) cleaning, yields high particle removal efficiencies (PRE). However, MS can frequently cause feature damage, and so damage becomes the principle limitation to MS power levels applied to small feature sizes. The use of lower MS power levels can benefit from a better understanding of removal mechanisms. In several publications the effects influencing the mechanisms of particle cleaning were discussed ^[1]. Particle transfer was investigated experimentally on wafer surfaces using bath tools and was tracked using fluorescent optical microscopy ^[2]. The goal of our investigation is to test the validity of the aforementioned models for mask cleaning using a spinning mask and a megasonic head mounted on a arm swinging over the mask surface, which is the most common hardware setup used for mask cleaning tools. While this equipment setup provides a useful variability, it also introduces disadvantages e.g. non-equal distribution of the megasonic power across the cleaned surface as will be shown. We will focus on some of the main parameters e.g. chuck speed, arm swing speed and media flow, which are strongly coupled by the fluid dynamics and cannot be treated separately. All three parameters influence particle-mask decoupling and reattachment during particle transport by the media stream across the mask surface. The approach to estimate the particle removal and reattachment rate is illustrated. The experiments performed allow the conclusion that the reattachment rate on a flat spinning mask surface is lower than previously assumed and the most critical part of the cleaning process is the detachment of the particle from the surface.

Advanced photolithography tools use 193 nanometer wavelength light for conventional and immersion printing. The increased energy of 193 nm (ArF) light coupled with the higher absorption cross section of most materials has lead to a dramatic increase in the rate of haze formation as compared to previously used lithographic wavelengths (248 KrF and 365 nm i-line systems). It is well known that at this short wavelength photochemical reactions are enhanced leading to progressive defect formation, or haze, on optical surfaces within microlithography tools. Therefore, strict contamination control of the optics environment is needed to avoid cumulative effects. Such measures have been implemented in lithography tools both for the optics and for the reticle during exposure. However, the patterned side of the photomask is the most sensitive element in the litho optical path for haze growth, because it is in focus and small defects will show up as printing defects. Moreover, the reticle life time depends both on rigorous contamination control for expose and transport/storage conditions (both inside and outside of the lithography tool). The litho operating cost depends directly on reticle life time. It is imperative that the industry takes the required measures to improve the airborne molecular contamination levels both in the storage part of the photolithography tool and in devices used to transport reticles outside of the tool to slow down reticle haze Past studies have shown the large effects of humidity and AMC on haze growth during storage and exposure. Therefore, significant improvements in storage and exposure environment have been implemented by many fabs to reduce the frequency of haze failures. It has also been shown that outgassing from materials surrounding the mask can influence or cause haze. It is clear that the reticle must be adequately protected from contamination sources throughout the life cycle of the reticle (both inside and outside of the lithography tool). In this paper we examine improvements in the storage conditions of reticles inside the lithography tool as well as improvements in commercial SMIF pods used in fab storage and automated handling of reticles.

The need for improved lithography resolution has driven the development of light sources with ever shorter wavelength. Excimer lasers have extended the exposure wavelength down to 193nm. Further resolution extension will require the introduction of Extreme UV (EUV) light source technology at 13.5nm. The traditional light source driver at each technology node has been higher power which enables increased productivity. More recently, improved light source stability, driven by tighter CD and overlay budgets for Double Patterning processes, has become more important and developments in this area will be described. The leading challenge for insertion of EUVL is source power and lifetime, which are both necessary to ensure cost effective operation. The first Laser Produced Plasma (LPP) production source using a high power CO2 laser and tin droplet targets is described. High conversion efficiency has enabled high EUV power performance. Continuous operation up to 18 hours, with stable power output, has been demonstrated. High collection efficiency is obtained using a large (5sr) multilayer mirror collector optic. The first integrated source will be delivered to support scanners for process development and insertion of EUVL at the 22nm node. A roadmap for future generations of LPP sources with scalable power will be outlined.

High volume manufacturing (HVM) of EUV-masks requires increase in accuracy, precision and practicability. HVM requirements for reflectometry of EUV-masks are expected to be < 0.05 % in peak reflectance, and < 0.002 nm in centroid wavelength (3 σ). Absolute accuracies should be of the same value at 1 σ. This should be accomplished along with the reduced measuring spot size of down to < 0.01 mm² as well as monitored alignment and positioning using fiducial mark. With the existing EUV-reflectometer developed for mask blank characterization, 0.1 % in peak reflectivity precision and 0.005 nm for centroid wavelength (1 σ) are routinely achieved on both reflective multilayer coated and absorber coated blanks. It has been demonstrated that our EUV-lamp enables EUV-MBR operation without wear or components change for > 300 million pulses, which is > 100.000 full spectra measured at different sites or > 10.000 samples measured at 9 spots each. In this work we are presenting our present status as well as the first steps to achieve the demanded target for HVM of EUV masks. We will analyze the factors and parameters which are critical to achieve this level quality.

To test the applicability of scatterometry on EUV masks we measured a prototype EUV mask both with an EUV scatterometer and a conventional scatterometer operated at 193 nm and compared the results with AFM and CD-SEM measurements provided to us by the mask supplier. The results of both CD-SEM and EUV- and DUV scatterometry show a quite good agreement in linearity despite constant CD offsets for these different metrology tools. The influences of the multilayer and Si capping layer on top of the multilayer thickness on EUV scatterometry results have been modelled with the help of FEM based simulations. A strong correlation has been found between the thickness of the capping layer and the sidewall angle. In general these results demonstrate the applicability both of EUV and DUV scatterometry for the characterisation of absorber structures on EUV masks. The application of DUV scatterometry allows to omit any influence from multilayer features and is only sensitive to the absorber structure. In this way EUV and DUV scatterometry complement each other for metrology on EUV masks. For applications in process optimisation and in process control the use of a conventional VIS/DUV-scatterometer may be sufficient in many cases.

ASML's two alpha demo tools (ADTs) have successfully gone through acceptance testing at the customer sites. The ADTs are full field step-and-scan exposure systems for extreme ultraviolet lithography (EUVL) and are being used for EUVL process development. The main objectives for the program are to prepare EUVL for insertion at the 27nm node, and to support the development of the global infrastructure of masks and resist. Resolution of 28nm dense L/S has been demonstrated recently. In this paper we will look at the imaging performance of the AD-tools in comparison to the requirements for the 32nm node for Memory (NAND-Flash and DRAM) and 22nm node Logic applications, as these feature sizes can be supported by the current resist performance. Process windows and MEEF are evaluated for L/S and CHs through pitch down to 32nm half pitch. Furthermore, the full wafer CD uniformity of the critical features of a NAND-Flash gate layer at 32nm half pitch is presented as well. Based on these findings the expected imaging performance of the TWINSCAN NXE:3100 at the 27nm node will be discussed.

Nano-Imprint Lithography (NIL) is one of the leading potential solutions for next generation lithography. Obtaining full field template with fine pattern resolution and reasonable throughput are the critical challenges in NIL. In a previous study, we reported the pattern resolution capability of EBM-6000 under nominal operation conditions (Current density: 70 A/cm²) that can be applied to CMOS device fabrication of 45 nm hp generation1. Smaller blur for better resolution is necessary to make NIL templates for 32nm hp generation and beyond. Blur in patterning process can be suppressed with smaller process blur, smaller aberration of electron optics, smaller forward scattering in resist and coulomb interaction among electrons. Beam blur incurred by coulomb interaction among electrons in EBM-6000 can be reduced with lower current density. In this paper, resolution extendibility of EBM-6000 with lower current density (30 A/cm²) was tested as one of the resolution enhancement techniques. Smaller aberration of electron optics is also effective to improve the resolution. We also checked the resolution of EBM-7000 under nominal operation conditions (Current density: 200 A/cm²) for a basic study of this paper. EBM-7000, which was developed for mask fabrication of 32 nm hp generation and mask development of 22 nm hp generation, will keep using 50 kV acceleration voltage and enhanced electron optics with smaller aberration as compared with EBM-6000².

Step and Flash Imprint Lithography redefines nanoimprinting. This novel technique involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the limitations of inspection at half pitches of 32 nm and below. A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. Defects in both the mask and imprinted wafers were characterized scanning electron microscopy and the measured defect areas were calculated. These defects were then inspected using a KLA-T eS35 electron beam wafer inspection system. Defect sizes as small as 12 nm were detected, and detection limits were found to be a function of defect type.

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in NIL template making with a 100keV acceleration voltage spot beam EB writer process, and have established a template making process to meet the requirements of the pioneers. Usually such templates needed just a small field (several hundred microns square or so) Now, for several semiconductor devices, the UV NIL is considered not only as a patterning solution for R&D purpose but eventually as a potential candidate for production, and instead of a small field, a full chip field mask is required. Although the 100kV EB writers have excellent resolution capability, they are adopting spot beams (SB) to generate the pattern and have a fatally low throughput if we need full chip writing. In this paper, we are focusing on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50keV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we achieved resolution down to hp28nm, and initial promising results of hp22nm (partial resolution) for line and spaces, and hp26nm for dense holes were observed..

For the preparation of interdigitated sensor devices with nanometre sized electrodes a low-cost route is followed. The central technique used for electrode definition is nanoimprint. To imprint the larger contact areas as easy as the electrodes, the contacts are broken down into a grid. In order to end up with a highly uniform residual layer the concept of 'partial cavity filling' is utilised, resulting in an almost negligible layer thickness. The metallic electrodes are defined by sputtering and lift-off directly after imprint, where a previous etching of the residual layer is not required. The results show that the concept works. With this strategy, preparation of an interdigitated sensor requires nothing but spin-coating, nanoimprinting and sputtering/lift-off.

The continuous progress of PROVE, the new photomask registration and overlay measurement tool currently under development at Carl Zeiss has been reported at mask related conferences since it's first publication at EMLC 2008. The project has moved in the past year from a final design on paper to functional hardware in the lab. Major tool components such as the climate control unit, the automated mask handling system and the metrology stage have been assembled and successfully tested. The scope of this paper is to report on the current status of PROVE and furthermore present results from simulations utilizing the image analysis routines of the tool. Monte-Carlo simulations were used to analyze the impact of several realistic tool limitations (camera noise, stage and focus noise and imaging telecentricity) on the image analysis process. The evaluation itself was based on a conventional threshold approach to perform both registration and CD measurement simultaneously. The results show, that the routines can deal with the tool imperfections and limit the contribution to the reproducibility error for standard registration markers to a negligible part. Even single contact holes suffer only from small errors, when camera noise is low and image averaging is increased. Employing a generally used test pattern the CD test results also confirm a sufficiently small error contribution to the CD non-uniformity reproducibility.

Scanning electron microscopy (SEM) is widely used as a fast and high resolution measurement method capable to per-form characterizations of the smallest isolated and dense features which are to be specified and produced on photomasks and wafers down to the 32 nm node and below. Furthermore, electron beam writing tools for mask or direct wafer patterning need electron beam based metrology capabilities for the required high precision alignment purposes. All of these applications benefit from a proper physical understanding of the electron interaction processes in the measured features of interest and suitable simulation capabilities in order to model the measured SEM image or signal contrasts. In this contribution we will report on a new Monte Carlo based modular simulation package, developed at the PTB and called MCSEM, which allows to model secondary as well as backscattered electron image contrasts on 3-dimensional object features. The fundamentals, basic features as well as first applications of the new simulation package MCSEM in the nanometrology field will be explained. Where appropriate, also other existing Monte Carlo based simulation pack-ages still are in use at the PTB, examples and comparisons with the new MCSEM simulation will be given.

Double patterning is considered as an upcoming class of technologies for the 32nm node photolithography processes and beyond. Several different double patterning technologies have been published within the last years. The ability to use coarse patterns to define finer patterns offers an opportunity to achieve resolution below 30 nm by using optical DUV immersion lithography. The specifications for overlay registration on a pair of photomasks are expected to be much tighter than for standard photomasks. Especially the registration of related patterns, distributed on two separate photomasks, gives a new challenge to the metrology tools. Accordingly, we will present a new approach for overlay registration by the KLA-Tencor LMS IPRO4 system. Similar to the standard overlay evaluation, the new algorithms allow pairing up related sites on both photomasks for registration. Even though the sites are not located on the same coordinates, the KLA-Tencor LMS IPRO4 system is able to pair up each site on the second photomask to a dedicated site on the reference photomask. Thus the algorithm creates a set of common sites for the overlay registration. Results of this versatile method will be presented, showing the feasibility to several applications.

Placement of a pellicle on a reticle will result in mechanical distortion of the reticle. Due to the mechanical distortion, exposure of the reticle with the pellicle will show additional image distortion, resulting in a reduced overlay performance on the wafer. Furthermore, a pellicle is a consumable and might be replaced during the lifetime of a reticle, introducing a different image distortion. Based on experimental reticle measurements before and after pellicle placement and modeling of the resulting data it has been suggested by Cotte et.al. [1] that the impact of the pellicle can be reduced by 50% using linear corrections. These corrections are common available on most exposure tools. Cotte reported that by correcting for the third order term in x-direction was said to reduce the impact of the pellicle by another 25%. We studied the impact of pellicle induced mechanical distortion on the overlay performance of the reticle. We experimentally tested pellicle induced distortion using a standard 193-nm pellicle and a standard ASML overlay reticle. The experiments included mask registration measurements before and after pellicle placement, as well as wafer data from exposures of the reticle before and after pellicle placement on an ASML TWINSCAN^TM XT:1400. We showed that, by using an intrafield grid correction model consisting of 15 coefficients of a third order polynomial regression model, we can execute grid corrections on the exposure tool enabling a reduction of the pellicle induced additional overlay to a level comparable to the situation without a pellicle.

The ever more demanding requirements in the semiconductor manufacturing sector together with the increasing mask making costs and cycle times call for new lithographic solutions. Electron beam lithography has shown its superior performance and flexibility in advanced patterning applications. It enables already today process and technology developments ahead of the ITRS roadmap, which addresses currently the 32nm and 22nm node or even below. Thus electron beam direct write (EBDW) can avoid the high costs and delay times related to the advanced masks required for critical layers. On the other side EBDW faces the concerns regarding its throughput, which bases upon the inherited sequential exposure method. A solution to improve the throughput performance offers the implementation of the cell projection method as already materialized in the Vistec SB3055 tool. In addition to the variable shape beam technology, which can project regular structures (rectangles, slants and triangles) only, cell projection is able to image complex structures. Thus, structures that would have required a multiple of regular shots are now projected in one single shot. Thanks to this approach not only the shot count is noticeably reduced, but also the overall throughput is increased. First experimental and simulation results show an improvement of a factor of about 3X. Nevertheless, the final throughput gain strongly depends on the pattern and data structure itself. Combining high resolution variable shape beam technology with the cell projection feature allows advanced R&D and small volume and prototyping applications to be performed with one system. The Vistec SB3055 features the high resolution capability of variable shape beam lithography and incorporates the advantages of the cell projection technology. Owing to this new option we are able to improve the throughput for standard design features while maintaining the required high accuracy of our exposure system. Beside this, the combination of cell projection and standard shape beam technology still offers a high degree of flexibility as the key advantage of EBDW. On the Vistec SB3055 system we have performed different resolution tests serving as comparison between cell projection and standard shape beam. In this paper we will present the resolution capability obtained with cell projection on test structures as well as the general accuracy achieved for real patterns.

Maskless electron beam lithography, or electron beam direct write, has been around for a long time in the semiconductor industry and was pioneered from the mid-1960s onwards. This technique has been used for mask writing applications as well as device engineering and in some cases chip manufacturing. However because of its relatively low throughput compared to optical lithography, electron beam lithography has never been the mainstream lithography technology. To extend optical lithography double patterning, as a bridging technology, and EUV lithography are currently explored. Irrespective of the technical viability of both approaches, one thing seems clear. They will be expensive [1]. MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10-20 wafers per hour. By clustering several of these columns together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV alternatives. In 2007 MAPPER obtained its Proof of Lithography milestone by exposing in its Demonstrator 45 nm half pitch structures with 110 electron beams in parallel, where all the beams where individually switched on and off [2]. In 2008 MAPPER has taken a next step in its development by building several tools. A new platform has been designed and built which contains a 300 mm wafer stage, a wafer handler and an electron beam column with 110 parallel electron beams. This manuscript describes the first patterning results with this 300 mm platform.

Electron beam direct write lithography is known for its high resolution capabilities, which enables studies ahead of the technology in production. That is why this technique is used for many years in laboratories for R&D. Recently it was shown that electron beam lithography can be integrated within the flows of the microelectronics industry for prototyping applications, low volume production and to support optical lithography for ASIC manufacturing. Moreover recent lithography workshops highlighted that the multi beam solution is identified as one potential technique for next generation lithography techniques to meet the requirements of sub-32nm technological nodes. The present proximity correction methods for electron beam lithography are based on the standard dose modulation principle. However these methods cannot properly ensure a sufficient control of the patterning of the most critical designs. To push the resolution capability of electron beam lithography, a new correction method is proposed. It consists in a multiple pass exposure strategy. For example instead of patterning a line in one pass (standard exposure), the pattern is split in several basic blocks with potential overlaps exposed in several passes and with an adapted dose. Compared to standard exposure, this solution provides an improved process window and a better control of the critical dimensions. We could achieve energy latitude of 22.2% and we improved the line edge roughness by 27% on 45nm dense lines (line width equal to space) with this method.

As chip design becomes more and more complex and alternative lithography technologies like EBDW get broader usage, the challenges increase with respect to all parts of the entire process. For exposure data preparation, we want to introduce a novel solution that offers new approaches to a user-friendly GUI, to exposure simulation, project definition and control, combined with proven kernels for data post-processing, fracturing and Proximity Effect Correction. This new solution has been implemented to run in an efficient 64 bit parallel computing environment and is called ePlace (eBeam Direct Write and Mask Data Preparation Layout Console). ePlace has the ability to process layout data of (in principle) unlimited size, given in various formats (GDSII, OASIS, DXF, CIF and others) and distributed over multiple files and hierarchies. Data post-processing capabilities include common Boolean functions (AND, OR, XOR, and Negation) as well as sizing, scaling, translation, rotation and overlap removal. Processed data can be fractured and formatted for e-beam writers (e.g. Vistec Shaped Beam (SB) tools). For Proximity Effect Correction both dose variations and newly developed geometry correction (EPC) algorithms are available and a simulation engine provides fast and precise results for exposure pattern predictions. In addition to the standard shape exposure, ePlace supports the latest Cell Projection (CP) feature of current Vistec's SB series as well as the upcoming Vistec Multi-Beam-Tool.

The paper describes a new approach of evaluating isolated opaque defects, as well as CD-like defects on hole layer, using features available on the inspection tool. This eliminates further verifications on specific tools, which would result in their overloading and in time consuming, with a potential negative impact on the delivery time of any product going through such processes. In the first case the method consists of associating the effect of a cluster of assist bars to that of isolated opaque defects, considering their size and position on the layout of the mask. In case of CD-like defects on holes the evaluation is based on a thorough characterization of the performance of the Litho2 detector of the Terascan T576 and its further verification with the AIMS readings.

Conventional photomask inspection techniques utilize global sensitivity for all inspected area in the die; SRAF and OPC features become the sensitivity-limiters for advanced photomasks which can result in reduced sensitivity to defects of interest (DOI). We describe the implementation of Sensitivity Control Layer (SCL), a novel database inspection methodology for the KLA-Tencor TerascanHR platform to improve sensitivity and reduce nuisance detections. This methodology enables inspection at maximum sensitivity in critical die-areas via "layer definition" and reducing sensitivity to sub-resolution features during inspection which can dramatically improve false-rate. DRAM and FLASH inspection performance was improved through the use of up to 6-control layers to increase sensitivity in the active area while reducing false detections by as much as 100X. Post-inspection defect analysis, and improved disposition accuracy of the SCL-enabled inspections will also benefit cycle time and higher throughput. In all test cases, sensitivity parameters were increased in the regions of interest over baseline inspections run with typical, production-type inspection methodologies. SCL inspection-sensitivity management, and layer partitioning of OPC structures, SRAF's, and other sub-resolution features is discussed in detail.

Especially for advanced masks the reticle inspection operation is a very significant cost factor, since it is a time consuming process and inspection tools are becoming disproportionately expensive. Analyzing and categorizing historical equipment utilization times of the reticle inspection tools however showed a significant amount of time which can be classified as non productive. In order to reduce the inspection costs the equipment utilization needed to be improved. The main contributors to non productive time were analyzed and several use cases identified, where automation utilizing a SECS¹ equipment interface was expected to help to reduce these non productive times. The paper demonstrates how real time access to equipment utilization data can be applied to better control manufacturing resources. Scenarios are presented where remote monitoring and control of the inspection equipment can be used to avoid setup errors or save inspection time by faster response to problem situations. Additionally a solution to the second important need, the maximization of tool utilization in cases where not all of the intended functions are available, is explained. Both the models and the software implementation are briefly explained. For automation of the so called inspection strategy a new approach which allows separation of the business rules from the automation infrastructure was chosen. Initial results of inspection equipment performance data tracked through the SECS interface are shown. Furthermore a system integration overview is presented and examples of how the inspection strategy rules are implemented and managed are given.

The evolution of the ALTA^(R) series of laser mask pattern generators has increased the relative contribution of intensity errors on critical-dimension (CD) control to those from placement errors. This paradigm shift has driven a change in rasterization strategy wherein aerial image sharpness is improved at the cost of a slight decrease in the averaging of column-to-column placement errors. Print performance evaluation using small-area CD test patterns show improvements in stripe-axis local CD uniformity (CDU) 3σ values of 15-25% using the new strategy, and systematic brush-error contributions were reduced by 50%. The increased importance of intensity errors, coupled with the improvement of ALTA system performance, has also made the mask-blank and process-induced errors a more significant part of the overall error budget. A simple model based on two components, a pattern-invariant footprint and one related to the exposure density ρ(x, y), is shown to describe adequately the errors induced by these sources. The first component is modeled by a fourth-order, two-dimensional polynomial, whereas the second is modeled as a convolution of ρ(x, y) with one or more Gaussian kernels. Implementation of this model on the ALTA 4700 system shows improvements in global CDU of 50%.

The availability of defect-free mask blanks is one of the most significant challenges facing the commercialization of extreme ultraviolet lithography (EUVL). The SEMATECH Mask Blank Development Center (MBDC) was created to drive the development of EUVL mask blanks to meet the industry's needs. EUV mask defects come from two primary sources: the incoming mask substrate and defects added during multilayer deposition. For incoming defects, we have both an in-house advanced cleaning capability and an advanced in situ defect smoothing capability. This smoothing system utilizes combinations of ion beam deposition and etch to planarize any remaining incoming substrate defects. For defects added in the multilayer deposition process, we have an aggressive program to find, identify, and eliminate the defects. This paper summarizes progress in smoothing substrate defects and eliminating ever smaller multilayer-added defects. We will show the capability of our smoothing process to planarize our existing population of bump and pit type defects and discuss how quickly this can be done. We will also discuss how many defects are added by the planarization process. In addition, we will show 53 nm sensitivity defect data for multilayer-coated EUV mask blanks.

Extreme ultraviolet (EUV) mask blanks with embedded phase defects were inspected with a reticle actinic inspection tool (AIT) and the Lasertec M7360. The Lasertec M7360, operated at SEMATECH's Mask Blank Development Center (MBDC) in Albany, NY, has a sensitivity to multilayer defects down to 40~45 nm, which is not likely sufficient for mask blank development below the 32 nm half-pitch node. Phase defect printability was simulated to calculate the required defect sensitivity for a next generation blank inspection tool to support reticle development for the sub-32 nm half-pitch technology node. Defect mitigation technology is proposed to take advantage of mask blanks with some defects. This technology will reduce the cost of ownership of EUV mask blanks. This paper will also discuss the kind of infrastructure that will be required for the development and mass production stages.

Naturally occurring sub 30 nm defects on quartz and Low Thermal Expansion Material (LTEM) substrates were characterized by using Atomic Force Microscope(AFM). Our data indicates that a majority of defects on the incoming substrate are hard defects including large, flat particles with a height less than 5 nm, tiny particles with a size of 10 nm to 30 nm SEVD and pits with a depth of about 9 nm. All the soft particles added by handling with sizes of >50 nm can be removed with a single cleaning process. At least four cleaning cycles are required to remove all of the remaining embedded particles. However, after particle removal in their initial location a shallow pit remains. Based on detailed characterization of defect and surface by AFM, we propose that these hard particles are added during the glass polishing step and therefore it is important to revisit the glass Chemical Mechanical Polishing (CMP) processes and optimize them for defect reduction. A qualitative value for particle removal efficiency (PRE) of >99% was obtained for 20 nm Poly Styrene Latex Sphere (PSL) deposited particles on surface of glass.

Contamination and especially Airbone Molecular Contamination (AMC) is a critical issue for mask material flow with a severe and fairly unpredictable risk of induced contamination and damages especially for 193 nm lithography. It is therefore essential to measure, to understand and then try to reduce AMC in mask environment. Results and assessment of mask pod environment in term of molecular contamination was presented in a first step (1¹). Then in second step further studies was carried out within European CRYSTAL project in order to reduce mask pod influence and contamination due to material out gassing. Results are shown here. These studies were carried out in the frame of the European R&D project, the so called "CRYSTAL" project, focusing on photomask defect reduction.

Maskless lithography based on electron beam parallelization requires well adapted data links, capable of transmitting the corresponding data volume at rates up to the Tbps domain. In this paper we focus on two key components, the high-speed data buffer unit and the integrated optical receiver, which are part of a scalable (24 - 140 Gbps) optical data link. The high-speed buffer design architecture enables the transmission of skew-compensated parallel data in the range of 50 Gbps. The 45-channel low-noise integrated optical receiver chip based on BiCMOS 0.6 micron technology is capable of an overall transmission capacity of 140 Gbps.

Molecular dynamics simulation is performed to study the yield stress and fracture mechanism of single crystalline silicon mold with notch-defect structures. From the stress distribution, it is found that the stress is concentrated near the notch defect and the notch acts as a trigger of the crucial mold fracture. The yield stress with a nano scale notch on the mold sidewall deteriorates more than 7.5 % compared to a defect-free mold. It is found that a surface damage such as notch defect is significant for strength deterioration of the mold. This result shows that the surface defects on the sidewall, which could be induced during the mold fabrication process such as dry etching process, causes serious failure.

In a semiconductor factory, each lithographic scanner is combined with a laser source and a track to form a lithocell. Quite frequently, lithographers have to deal with running the same lithographic process on multiple lithocells. Usually a new process is developed for one cell, and then transferred to other cells. However, small but non-negligible differences between lithocells, may result in yield losses. Nevertheless, several scanner's parameters (called proximity manipulators) can be used to compensate for these differences and match the secondary lithocells to the reference one. Recently a new advanced process matching methodology called Pattern Matcher has been developed. Using this method, we performed successful proximity matching of several ArF scanners in the production environment. In this paper, we discuss the principles of Pattern Matcher approach as well as methodology for data acquisition and present results of our matching.

Extreme Ultraviolet Lithography (EUVL) is one of the leading candidates for the next-generation lithography in the sub-30 nm regime. Stringent flatness requirements have been imposed for the front and back surfaces of EUVL masks to ensure successful pattern transfer that satisfies the image placement error budget. The EUVL Mask Standard (SEMI P-37) specifies the flatness of the two mask surfaces to be approximately 50 nm peak-to-valley. It is essential to measure the mask surface nonflatness accurately (without gravitational distortions) to the extent possible. The purpose of this research was to study the various mask mounting techniques and to compare these methods for repeatability and accuracy during the measurements.

The achievement of a depth of focus required for stable process conditions is one of the biggest challenges in modern optical photolithography. There are several ways of improving the depth of focus. For line/space layers, for instance, application of RET (Resolution Enhancement Technology) using scattering bars, phaseshift masks or optimized illumination systems have shown good results. For contact and via layers the depth of focus is limited and critical, due to the structure size of the holes, alternating pattern density and wafer topology. A well known method of improving the depth of focus for contact and via layers is called focus latitude enhancement exposure (FLEX) [1-3]. With FLEX, several focal planes are being exposed, i.e. each during a separate exposure step. The main drawback is low throughput, as the total processing time rises which each additional exposure. In this paper, we investigate Nikon's CDP (continuous depth of focus expansion procedure) [4]. The CDP option is applicable to modern scanning exposure tools [4-5]. A schematic view of the procedure is shown in Fig. 1. The CDP value or CDP amplitude defines the tilt of the wafer and thus the range of focus in the resist, as the focus plane migrates through the resist during the exposure. The main advantage of CDP, compared to FLEX, is higher throughput, since focal planes are defined within a single exposure. A non-CDP exposure may result in varying aerial images within resist thickness, therefore leading to decreased image contrast within out-of-focus planes. As shown in Fig. 1 the averaged aerial images of a CDP exposure induce better image contrast throughout the resist layer and therefore increase the focus window.

With the transition of lithography into 45nm node and beyond the industry faces the challenge that mask complexity increases steadily, mask specifications tighten and process control becomes extremely important. The use of Phase Shifting Masks (PSM), combined with off-axis illumination schemes, is essential to print feature sizes going beyond the lithographic wavelength. In conjunction with the shrinking feature size the tolerable defect size shrinks as well. This goes along with rising mask costs and therefore a high first pass yield becomes more important than ever. Repair strategies are required which have the potential to support the trend of decreasing tolerable defect sizes for both clear and opaque defects. In case of PSM it is not only important to remove material, of special interest is the capability to repair phase defects. This requires material deposition and etching accounting for transmission and phase as well. The ebeam repair system MeRiT^(R) MG 45 is based on the GEMINI^(R) column and allows etching and deposition to repair both clear and opaque defects with high resolution and edge placement precision. In this paper we focus on repair of phase defects on 6% att. PSM. We concentrate on 45nm lines/spaces looking into different defect dimensions. At feature sizes of 45nm CD, corresponding to 180nm CD at mask, feature topography already impacts the phase shift. Therefore a base line investigation is performed evaluating the correlation between deposited PSM layer height and phase shift covering also the impact of 3D mask effects on phase shift. The deposited layer height is measured using AFM. For phase evaluation the newly developed phase metrology system Phame® was used. Phame^(R) enables optical phase shift measurement with high spatial resolution down to 120nm half pitch on mask. On-axis and off-axis illumination can be applied according to the required scanner settings during wafer printing. Phame^(R) captures imaging effects as well as 3D mask effects which are of special importance for further shrinking feature sizes.

Because of mask cost reduction, electron beam direct write (EBDW) is implemented for special applications such as rapid prototyping or small volume production in semiconductor industry. One of the most promising applications for EBDW is design verification by means of metal fix. Due to write time constrains, Mix & Match solutions have to be developed at smaller nodes. This study reports on several Mix and Match processes for the integration of E-Beam lithography into the optical litho process flow of Qimonda's 70 nm and 58 nm DRAM nodes. Different metal layers have been patterned in part with DUV litho followed by E-Beam litho using a 50 kV Vistec SB3050 shaped electron beam direct writer. All hardmask patterns were then simultaneously transferred into the DRAM stack. After full chip processing a yield study comprising electrical device characterization and defect investigation was performed. We show detailed results including CD and OVL as well as improvements of the alignment mark recognition. The yield of the E-Beam processed chips was found to be within the range of wafer-to-wafer fluctuation of the POR hardware. We also report on metal fix by electrical cutting of selected diodes in large chip scales which usually cannot be accessed with FIB methods. In summary, we show the capability of EBDW for quick and flexible design verification.