Design For Manufacturability Production Management (DFM-PM) Subcommittee has been started in succession to Reticle Management Subcommittee (RMS) in Semiconductor Manufacturing Technology Committee for Japan (SMTCJ) from 2005. Our activity focuses on the SoC (System On Chip) Business, and it pursues the improvement of communication in manufacturing technique. The first theme of activity is the investigation and examination of the new trends about production (manufacturer) technology and related information, and proposals of business solution. The second theme is the standardization activity about manufacture technology and the cooperation with related semiconductors' organizations. And the third theme is holding workshop and support for promotion and spread of the standardization technology throughout semiconductor companies. We expand a range of scope from design technology to wafer pattern reliability and we will propose the competition domain, the collaboration area and the standardization technology on DFM. Furthermore, we will be able to make up a SoC business model as the 45nm node technology beyond manufacturing platform in cooperating with the design information and the production information by utilizing EDA technology.

Photomask manufacturing automation has lagged semiconductor wafer process automation development. In a highly complex wafer fab, data automation and advanced process control techniques are required. Given limited demand, photomask equipment manufacturers have not unilaterally made the investment necessary to implement a standardized data flow protocol which would allow photomask process automation enhancements. Surveys indicate that significant photomask yield loss is attributed to manufacturing and administrative errors. By working with individual photomask equipment suppliers and through internal application development, IBM photomask manufacturing automation has eliminated nearly all manufacturing and administrative errors. Some examples of processes that were automated over the past several years are process routing selection, photomask yield prediction, linkage of photomask blank to mask build part number, automated recipe and setup download and dispositioning criteria, statistical analysis of process parameters and defect density, defect information management and automated data upload for photomask and wafer engineering use. Project highlights will be discussed and the case will be made for standardization of data flow protocol and for further photomask process automation improvements.

As photomask pattern complexity continues to increase, it becomes more challenging to control write times of shaped e-beam tools. This raises the related concerns of increased mask costs and extended mask cycle times. A strategy for sub-100 nm technology nodes is to use high-speed DUV laser pattern generators for as many layers as possible, reserving e-beam tools for only the most critical layers. With 248 nm optics and high-NA partially coherent imaging, the Sigma7500 increases the application space available to laser pattern generators. Image profiles are steepened with phase shifting methods, and pattern fidelity is improved with on-line corner enhancement. In the Sigma architecture, mask patterns are imaged with full fidelity and addressability in each writing pass. Because of this, the Sigma7500 provides additional means to improve write time by reducing the number of exposure passes. Platform improvements have resulted in a 2-pass writing accuracy that meets the 4-pass specification of the previous system. Write time is typically under two hours in 2-pass mode, compared to approximately three hours for 4-pass. The Sigma7500 can generally be used for all binary mask layers at the 90 nm technology node, and for about half the layers at 45 nm. The ProcessEqualizer^TM function addresses long range CD errors arising from mask process effects. Mask data is sized in real time to compensate for process errors related to local pattern density, and also to correct for static process CD signatures. With a through-the-lens alignment system and both grid matching and pattern matching capabilities, the tool is also suited to 2^nd layer patterning for advanced phase shifting mask (PSM) applications down to 45 nm, with extendibility to 32 nm. Process integration is facilitated by the use of standard FEP-171 chemically amplified resist (CAR).

EBM-5000 equipped with the new feature of high current density (50A/cm²) has been developed for 45 nm technology node (half pitch (hp) 65 nm). EBM-5000 adopts 50 kV variable shaped electron beam (VSB)/vector scan architecture and continuous motion stage, following the steps of preceding EBM series. In addition to the high current density, new technologies such as high resolution electron optics, finer increment for beam position and exposure time control, and new data format "VSB-12" to handle large data volume have been introduced on EBM-5000. These new technologies address two conflicting issues: improvement of throughput and better accuracy. This paper will report the key challenging technologies, certain results of EBM-5000 operation and findings obtained through our development efforts that can be applied to future generation tools. The fundamental local CD uniformity (LCDU) limit is also discussed.

This paper includes an empirical determination of the relative CD error as a function of in-vacuum post exposure delay (PED). The effects of local pattern density and the impact of reticle proximity effect correction on the in-vacuum PED CD bias error are also considered. Results of dose compensation to improve CD uniformity on both artifact and production reticles are reviewed. The results show that by applying an exposure time dependent dose correction, the CD bias dependency upon in-vacuum PED is effectively compensated. In addition, the results show that dose compensation is effective at correcting for the in-vacuum PED dependency of local pattern density proximity errors. Finally, the paper concludes with a brief discussion of the relationship between existing reticle CD correction techniques for errors including electron beam fogging, etch loading, stable reticle process spatial CD non-uniformities and the new time dependent dose correction.

Recently, the mask writing technology with 50keV electron beam energy is close to its resolution limit. It will be hard to achieve 30nm node mask pattern in near future. Especially the writing of OPC and 2-D patterns will be critical issue. Furthermore, according to the shrinking of pattern, the tight mask CD uniformity is required due to large MEEF. About 2.4nm mask CD uniformity will be required in terms of 3σ. In this report, we analyze the beam energy effect on the resolution improvement using the quantitative analysis of beam blurring including the resist effect. From the experimental result, the total blur is about 45.57nm with 50keV VSB and 43.70nm with 100keV spot beam. And we compare the dose margin and linearity for each case. Dose margin by 50keV VSB is 0.96nm/%dose and 0.89nm/%dose for 100keV spot beam. We conclude that the effect by the increasing of electron beam energy is not so much significant and the reduction of the blur by electron beam column is as much as efficient. And finally we calculate the limitation of CD uniformity for each case.

With the use of 193nm lithography, time-dependent haze problem has become a critical issue for semiconductor industry. The understanding of the conditions that create haze defects is very crucial for the future development of haze-free cleaning processes. The gaseous environment trapped between the pellicle film and the mask surface triggers photochemical reaction under laser exposure, which could result in the formation of killer (printable) defects on the mask surface. Therefore, the real time analysis of the haze environment in the trapped space could provide essential clues to the characterization of haze defect growth mechanism. This fundamental study can be applied to the invention of real-time monitoring tools for the defect growth progress on the mask surface as well as the development of haze-free cleaning processes. Here, we propose a method to analyze the gaseous space trapped between the pellicle film and the mask surface that creates a highly reactive environment.

To eliminate ammonium sulfate haze caused from sulfuric acid residue on the mask surface, we have been working for resist stripping and cleaning without the use of sulfuric acid process. This paper describes sulfate-free photomask cleaning technology by improving ozone cleaning process.

Requirements to meet the 45nm technology node place many challenges on photomask makers. Resolution Enhancement Techniques (RET), employed to extend optical lithography in order to resolve sub-resolution features have burdened mask processes margins. Also, yield compromises rise with every nanometer of error incurred on the photomask (and device) platforms. As photomask costs rise, strict performance control is required for all photomask varieties utilized in the mask shop. Mask etching for future technology nodes, requires a system-level data and diagnostics strategy. This necessity stems from the need to control the performance of the mask etcher at increasingly stringent and diverse requirements of the photomask production environment. From etch applications perspective, alternating phase-shift masks (APSMs) and OPC masks pose key challenges. Specifically, the etcher needs to provide highly uniform CD performance across the entire active area of the photomask - for various feature sizes and load distributions, with no degradation to profiles. It is challenging to strike this balance, yet maintain adequate process window. Future etch systems require sensitive controls and knobs to provide this high precision and repeatable performance. Additionally, incoming variation in plate characteristics and quality necessitate tuning knobs capable of targeting the optimum performance across a diversity of applications.

Advanced process control (APC) of photomask dry-etching has been studied for strict mean control of both CD and phase angle of phase shift masks (PSMs). Equations to correlate process information with actual etching results have been developed for this purpose. It is showed that plasma reactance measured with RF sensor has noticeable correlation with Cr etching bias, which is affected by Cr load and condition of etching chamber. Simulation of etching bias based on plasma reactance shows the good agreement with the trend of actual etching results. Expectation of process capability index (Cpk) for mean-to-target (MTT) within 5.2nm is about 1.27, corresponding to CD yield more than 99.9%. In case of MoSi based PSMs, monitoring the sensor outputs is also useful to simulate the etching rate of phase shifter. One simple relationship can be also derived as the case of Cr etching bias. Expected phase error is within 1.5degree in almost cases. In actual photomask fabrication, maintenance of the equation for APC is a critical issue to guarantee the high process yield for a long period. It is showed that trend of the plasma reactance gives the meaningful information effective in automatic maintenance of the equations. As a conclusion, it is proved that our APC method is one of the answers to give the highest MTT yield for both CD and phase angle.

Intra-field CD variation is, besides OPC errors, a main contributor to the total CD variation budget in IC manufacturing. It is caused mainly by mask CD errors. In advanced memory device manufacturing the minimum features are close to the resolution limit resulting in large mask error enhancement factors hence large intra-field CD variations. Consequently tight CD Control (CDC) of the mask features is required, which results in increasing significantly the cost of mask and hence the litho process costs. Alternatively there is a search for such techniques (1) which will allow improving the intrafield CD control for a given moderate mask and scanner imaging performance. Currently a new technique (2) has been proposed which is based on correcting the printed CD by applying shading elements generated in the substrate bulk of the mask by ultrashort pulsed laser exposure. The blank transmittance across a feature is controlled by changing the density of light scattering pixels. The technique has been demonstrated to be very successful in correcting intra-field CD variations caused by the mask and the projection system (2). A key application criterion of this technique in device manufacturing is the stability of the absorbing pixels against DUV light irradiation being applied during mask projection in scanners. This paper describes the procedures and results of such an investigation. To do it with acceptable effort a special experimental setup has been chosen allowing an evaluation within reasonable time. A 193nm excimer laser with pulse duration of 25 ns has been used for blank irradiation. Accumulated dose equivalent to 100,000 300 mm wafer exposures has been applied to Half Tone PSM mask areas with and without CDC shadowing elements. This allows the discrimination of effects appearing in treated and untreated glass regions. Several intensities have been investigated to define an acceptable threshold intensity to avoid glass compaction or generation of color centers in the glass. The impact of the irradiation on the mask transmittance of both areas has been studied by measurements of the printed CD on wafer using a wafer scanner before and after DUV irradiation.

It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by introducing EUV-specific tool sets while capitalizing on the existing photomask technology and utilizing the standard photomask equipment and processes in 2004. Since then, significant progress has been made in many areas including absorber film deposition, mask patterning optimization, mask blank and patterned mask defect inspection, pattern defect repair, and EUV mask reflectivity metrology. In this paper we will present the EUV mask process with the integrated solution and the results of the mask patterning process, Ta-based in-house absorber film deposition, absorber dry etch optimization, EUV mask pattern defect inspection, absorber defect repair, and mask reflectivity performance. The EUV resist wafer print using the test masks that are fabricated in the EUV mask pilot line will be discussed as well.

Dry etch process of ASET developed EUV blank was evaluated. ASET blank used TaGeN for absorber layer and Cr for buffer layer. CF4 gas process and Cl2 gas process were evaluated for TaGeN absorber layer dry etching. Because of advantages of small buffer layer damage and etching stability, CF4 gas process was selected as our standard process for TaGeN etching. Cl2 and O2 mixture gas was used for Cr buffer layer dry etching. After buffer layer dry etching, EUV reflectivity and wafer print were tested. AFM nano-machining was applied to absorber layer defect repair. Repair results were evaluated using SEM, AFM and wafer print test. EUV mask fabrication process was also developed for commercial EUV blank.

Defects on an extreme ultraviolet (EUV) mask blank strongly depend on the defects on the mask blank substrate. Any imperfection on the substrate surface in the form of a particle, pit, and scratch will appear on the EUV mask blank. In this article, we study the effect of the cleaning process on the creation of defects on the EUV substrate and mask blank. Added particles could be removed by improving the cleaning tool and the cleaning process. Pits are generally created when many large defects, particularly glass-like materials, are present on the surface and the substrate is exposed to a high energy cleaning step. Comparison of different high energy steps in a typical cleaning process suggests that the megasonic step most likely creates pits. Current cleaning processes developed in the Mask Blank Development Center (MBDC) have been optimized so that no added pits or particles are observed after using them.

We evaluated and optimized Ta-based absorber added by Si for EUV mask. Consequently, we confirmed TaSix based bi-layer absorber stack has the following performances; It has amorphous morphology without columnar structure advantageous to fabricate fine pattern with smaller line edge roughness. In order to realize better position accuracy, it has low internal stress capable to control. As an optical property, it has low DUV reflectance at 257nm which facilitates to perform defect inspection. As it can be etched anisotropcally by conventional halogen gases without using hard mask, we achieved almost vertical sidewall profile of 120nm lines and spaces pattern and promising CD control accuracy.

Mask defect specifications not only are needed to ensure quality masks for acceptable resist patterning on wafers, but also are utilized as a common goal for tool development, noticeably for mask inspection and repair. Defect specifications are generally determined by the allowable critical dimension (CD) changes from 'defect printability' experiments where a programmed defect mask (PDM) with intentionally placed defects is exposed in a stepper and the changes in resist CDs are measured. With the recent availability of extreme ultra-violet micro-exposure tools (EUV MET), a small field stepper with a numerical aperture (NA) of 0.3, 5X reduction and adjustable degrees of coherence, we are able for the first time to perform extensive studies of pattern defect printability for EUV masks with a high NA exposure tool. Such studies have investigated the defect impact to feature CDs for three different types of patterns: poly gate layer, contacts, and dense lines and spaces. This paper presents the experimental results and analysis of printability data collected under two illumination conditions, annular and dipole, on the MET with full focus and dose matrix (FEM). We have investigated as many as 10 types of defects designed on the PDM for each pattern layer. For each type of defect, a total of 15 sizes are coded on the PDM. With the consideration of limited resolution and line edge roughness of current EUV resists commonly used for EUV lithography development, the CDs under study were chosen in the range of about 40nm to 70nm. Extrapolations from these data are made to predict pattern defect specifications for smaller resist line features. Resist resolution is the main reason for the discrepancies between aerial image simulations and data presented in this paper.

This study investigated the feasibility of individual mask-pattern corrections to compensate for the effects of off-axis incidence and optical proximity effects for a reflective mask in EUV lithography. Individual mask pattern corrections for the effects of off-axis incidence are made by biasing, and then merged with conventional optical proximity effect corrections (OPC). This method provides good pattern fidelity in printed images on a wafer. Three evaluation functions were used to determine the amount of bias; they are related to the energy of the light reflected from a mask surface, the energy of 0th-order diffracted light, and the energy of light passing through the pupil. Merging to obtain the final corrected mask pattern allows the use of conventional OPC algorithms and is a simple method that is applicable regardless of the relationship between the direction of the incident light and the orientation of the edges of mask patterns.

As semiconductor technology nodes continue shrinking down to 45nm and below, the requirements for number of particle adders and their size during optical mask blank shipment are getting tighter and tighter. In the case of extreme ultra-violet lithography (EUVL) for 32nm and below technology nodes, the requirements for shipping the final mask product are even more stringent. It virtually requires zero particle adders or single digit particle adders (if local mask clean tool is equipped at wafer fab) at 30nm size for 32nm technology node and even smaller size for the 22nm technology node. This EUVL mask handling specific issue is due to the lack of pellicle material available at EUV wavelength, because of strong EUV light absorption by all solid materials. In the past few years, several benchmarking studies on mask handling and shipping without pellicles have been conducted by different companies. The results indicated that many improvements are needed to bring down the handling and shipping induced particle adders at the required 30nm size for the 32nm technology node. In this study, we have evaluated particle generation at ≥60nm PSL equivalent size during mask shipment. We have demonstrated zero particle adders in shipping by using mask carriers with simple design. Our study included different commercially available carriers and non-commercially available carrier with designs to further minimize the particle generation and deposition onto the mask critical surface. The study has also shown that both the carrier design and the shipping packaging are responsible for clean mask transportation. The smallest particle size (60nm) evaluated in this study is limited by the metrology capability. Further evaluation for particle adders at size ≤60nm requires new development for higher sensitivity inspection capability.

As patterns on photomasks are getting more complex due to RET technologies, mask rule check (MRC) has become an essential process before manufacturing photomasks. Design rule check (DRC) tools in the EDA field can be applied for MRC. However, photomask data has unique characteristics different from IC design, which causes many problems when handling photomask data in the same way as the design data. In this paper, we introduce a novel MRC tool, SmartMRC, which has been developed by SII NanoTechnology in order to solve these problems and show the experimental results performed by DNP. We have achieved high performance of data processing by optimizing the software engine to make the best use of mask data's characteristics. The experimental results show that only a little difference has been seen in calculation time for reversed pattern data compared to non-reversed data. Furthermore, the MRC tool can deal with various types of photomask data and Jobdec in the same transparent way by reading them directly without any intermediate data conversion, which helps to reduce the overhead time. Lastly it has been proven that result OASIS files are several times smaller than GDS files.

At deep sub-wavelength nodes, it is difficult to transfer accurate mask pattern onto the wafer. However, actual gate pattern is distorted, and timing analysis tools calculates circuit performance on the assumption that the same gate length exists throughout the whole gate width. We calculated the property of the original 2 dimensional distorted transistor by using distribution of gate length. Firstly, in order to evaluate the accuracy of this approach, we have compared them with experimental results that may influence the 65 nm-node design rule. In the conventional method using a rectangular model, results of transistor properties are different from the experimental values, however, results of this approach can reproduce the experimental results. Secondly, this approach is applied to optimization of layout design and OPC. In order to investigate the influence of circuit performance on a layout design and OPC, we calculated the properties (drive current; Ion and leakage current; Ioff) of each transistor contained in standard cell library which is most referred to in a system LSI. We have investigated 2 layouts and 8 OPCs. According to these results, we find out that optimal OPC differs according to the prioritization of Ion and Ioff, whether it is an N-channel or P-channel, and also by layout. Furthermore relaxation of layout decreases variability of Ion caused by defocus. Moreover, since the influence of pattern distortion can be expressed by circuit term such as Ion and Ioff in addition to conventional process terms, it becomes easier for designers to understand manufacturing issues.

We have reported a new paradigm in design database inspection, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScan^TM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window for an entire chip design. The simulated images are compared to the best focus/exposure reference, and defect detection and CD variation and uniformity algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window. In addition, DesignScan can sort out detected defects based on the severity of defects-their impact to lithography process window. Such sorting provides powerful guide for prioritizing defective patterns for fixing based upon their contribution for process window enlargement. In this paper, we will report on inspection results of DesignScan on a ProMOS test device database with two different OPC models, in particular its ability to sort defects based on their process window impact. The process window can be enlarged by fixing the weakest patterns, which are the limiting patterns of the process window, until the next weakest patterns become the limiting ones. Previously, we have demonstrated conceptually a database design error detection and correction using DesignScan and Aprio's reconfigurable OPC technology on a test database through programmed defects. We will demonstrate in this paper the process window enhancements achieved on a customer test database through the fixing of process window limiting patterns using integrated defect detection, defect severity sorting and OPC correction for the first few groups of defects.

Hot spot clearance using process simulation is indispensable under low-k1 lithography process for logic devices of 65 nm and below. Hot spots such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Appropriate calibration of design rule (DR), mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of design at hot spot will be effective, but it takes too much time to determine how to modify layout to be consistent with DR, MDP/OPC rule, and the process often needs to be iterative. Therefore, there is a need for an automated hot spot fixing system is capable of fixing design layout so as to avoid fatal hot spot occurrence, with sufficient process margin and short turn around time (TAT). We developed an automated hot-spot fixing system, Hot Spot Fixer (HSF). The basic system flow in the developed system is as follows; Design data is processed with the conventional mask data preparation process. Then, process simulation is performed to extract hot spots. The hot spots are categorized by lithography error mode, critical level, and surrounding context. An intelligent hot-spot modification instructor, taking the surrounding situation into consideration, generates modification guide for the every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. If necessary, several modification candidates are indicated and the user can choose the most adequate one from them. The design modification process is verified from every aspect, using Design Rule Checker (DRC) and process simulation. The modified design data, with reduced potential hot spot compared with pre-modification design, is processed under the conventional mask data preparation process again, and then makes mask data, which will reduce the number of potential hot spot. We applied the HSF system to metal layer of logic devices of 65 nm and then the hot spots are almost diminished throughout a full chip within twelve hours. Thus HSF feasibility has been proved for metal layers in 65 nm node and below with full chip data volume.

In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. This approach is a key enabler of printing mask features on wafers without requiring new manufacturing equipment and with minor changes to existing manufacturing processes. The approach also does not require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking used to verify the lithographic results.

Extending ArF lithography to the 45nm node at a lower k₁ puts a heavy demand on resolution enhancement techniques (RETs), exposure tools, and lithography friendly design. Hyper numerical aperture (NA) exposure tools, immersion, and double exposure techniques (DETs) are promising methods to extend lithography manufacturing to the 45nm node at k₁ factors around 0.3. Double dipole lithography (DDL) is becoming a popular RET candidate for foundries and memory makers to pattern the poly gate active layer. Double exposure method or double pattern technique (DPT), using ternary 6% attenuated PSM (attPSM) is a good imaging solution that can reach and likely go beyond the 45nm node. In this work, back end of the line (BEOL) metal like test structures were used for developing a model-based dark field DDL method. We share our findings of using DDL for patterning 45nm node trench structures with binary intensity mask (BIM) on a dry high NA ArF scanner.

As the k1 factor and minimum feature sizes decrease, the use of optical proximity correction (OPC) is increasing and is getting more complex. The complexity increases the possibility of correction errors like improper placement of edges in the OPC output data such that the printed results will deviate from target design. In this paper we will describe new modeling method by using 2-dimensional test structures for model based verification of post OPC data. Recently, most of the semiconductor companies implement a system for model based verification (MBV) for post OPC data into a manufacturing data flow. In case of model based verification, the most important thing is the accuracy of model which is used to detect the potential hot spot and critical errors like pinching-bridging errors and CD variation. For good model accuracy, process change has to be feedback to the model generation step by injecting real wafer information. Therefore, optimization process of 2-dimensional data set is needed. We proposed new modeling method by using optimization process of calibration data set which consists of 2-dimensional structures. Also, we present results of MBV and discuss about constraints and considerations of model based verification.

Due to the low k₁-factor which leads to reduced process latitude, it is becoming increasingly important that OPC and lithography verification take into account process variations. An essential element to the successful implementation of full-chip, process window aware RET/OPC design and verification is a lithography model that is able to accurately describe the lithography process across the entire focus-exposure window. Moreover, a straightforward calibration without requiring excessive amount of through process window measurements is also critical to ensure quick turnaround-time. In this paper, we introduce a new Focus Exposure Matrix (FEM) model based on Brion's Tachyon platform. The FEM model has two adjustable parameters: focus and exposure. By adjusting these parameters, new models at arbitrary process conditions within the process window can be quickly derived, with which large number of simulation results can be obtained at different exposure and focus for detailed process window analysis. The fitting of FEM model is through a single calibration process using wafer measurements at limited number of sampling locations within the process window. The resulting calibrated FEM model is shown to have superior fitting as well as prediction accuracy, without requiring massive additional focus-exposure measurements. Accurate FEM modeling enables two important applications in the deep sub-wavelength regime: lithography manufacturability check (LMC) and optical proximity correction (OPC). FEM-enabled LMC proves to be a substantial advance in model-based verification by providing through process window analysis capability. Furthermore, FEM models can be employed in OPC practically to prevent catastrophic failures due to process variation while still maintaining satisfactory OPC quality in terms of matching the modeled wafer image to design intent. In this paper, we use real data and simulation results to demonstrate the quality of the FEM-model and its effectiveness in the LMC and OPC applications.

Inverse Lithography Technology (ILT) is a rigorous approach to determine the mask shapes that produce the desired on-wafer results. In this paper, we briefly describe an image (or pixel))-based implementation of ILT in comparison to OPC technologies, which are usually edge-based. Such implementation is more computationally scalable and avoids laborious segmentation script-writing, which becomes more complex for newer generations because of complicated proximity effects. In this paper, we will give an overview of ILT, present some simulation and wafer examples to demonstrate the benefit of ILT, clarify common myths about ILT, discuss and show examples to illustrate the impact in every step of the mask making process. Specifically, studies done with several leading mask shops around the world on mask manufacturability (including data fracturing, writing strategy and writing time, mask inspection), will be shown.

The usage of ArF immersion lithography for hp 65nm node and beyond leads to the increase of mask error enhancement factor in the exposure process. Wavelength of inspection tool is required to consistent with wavelength of lithography tool. Wavelength consistency becomes more important by the introduction of phase shift mask such as Tri-tone mask and alternating phase shift mask. Therefore, mask inspection system, whose inspection light wavelength is 199nm, has been developed. This system has transmission and reflection inspection mode, and throughput, using 70 nm pixel size, were designed within 2hours per mask. The experimental results show expected advantages for Die-to-Die and Die-to-Database inspection compared with the system using 257nm inspection optics. Shorter wavelength effect makes transmission inspection sensitivity increase, and realizes 40nm size particle inspection. As for the phase shift mask, the difference of gray value between the area with phase defect and without phase defect was clear relatively. In this paper, specifications and design, experimental results are described.

Mask inspection plays a pivotal role in current high grade mask making processes and further its importance is getting bigger. The purpose of inspection process is as follows. One is simple sorting of NG masks that have fatal defects with high sensitivity. The other is improvement of total mask manufacturing process and mask quality using defect source analysis. As semiconductor device is getting shrunk down, the influence of mask defect is increasing. Therefore, there are special needs for the efficient use of such expensive inspection machines and the systematic approach of defect analysis. In this paper, we propose novel mask inspection flow to improve mask inspection capacity and systematic defect management. In general, Inspection process is divided by two steps. One is detection of defects and the other is review for defect analysis. Our concept of new inspection flow is adoption of individual defect review system after defect detection in inspection machine. With this new inspection flow using defect review system, we could increase inspection capacity by 30% and set up unified defect analysis hub.

Repair technology for 65nm generation photomasks requires more accurate shape and transmittance. The objective of this study is to evaluate FIB repair process with low acceleration voltage. The evaluation items were imaging impact, defect visibility, repaired shape, through focus behavior, repeatability of edge placement and controllability of repair size. In conclusion, we confirmed that FIB repair process with low acceleration voltage is applicable to 65nm generation photomasks.

The efficacy of currently available repair techniques has been assessed for a wide variety of defect types encountered on advanced lithographic masks. Focused ion beam (FIB) with gas-assisted etching and deposition, electron beam induced chemical processing (EBIC), and atomic force microscope based nano-machining (RAVE) were among the different methodologies evaluated. Various types of optical phase-shifting masks for the 45nm lithographic node, as well as nano-imprint lithography (NIL) templates, were used as test vehicles. Defect imaging resolution, spatial process confinement, repair edge placement, end-pointing control, sample damage (undesired changes in topographic or optical properties), and future extendibility served as the primary metrics for gauging repair performance. The primary aim of this study was to provide a single "snapshot" in time of the current development status of each tool for the context of 45nm node mask repair specifications and by no means were there any expectations for a final solution to already be commercially available. However, the results obtained from these tests should provide useful feedback and information to help improve the learning cycle for the development of 45nm lithographic node mask repair systems.

Immersion lithography offers the semiconductor industry the opportunity to extend current ArF processes before switching to shorter wavelengths. As numerical apertures of scanners for hyper NA move above 1.0 with immersion lithography, increased attention must be paid to the photomask or reticle and its wafer printability. Feature sizes on the photomask become increasingly critical as they behave more like partial wire grid polarisers, as they become comparable to, or smaller than the wavelength. Besides challenges to address reticle polarisation effects, lithographers must also consider the polarisation state of the illumination and subsequently the contrast loss for light with a TM polarisation state. Such an effect, also called the vector effect, is caused by the increasing angle of incidence of the diffracted light for larger numerical apertures on the scanner. Therefore, for wafer printing using hyper NA scanners, the industry consensus is that TE polarised illumination must be used to meet the stringent requirements of imaging contrast. In this paper, initial results of measurements using the optical test stand and the alpha tool of a completely new AIMS^TM tool for the 45nm node will be presented. The system covers all aspects of immersion and polarisation lithographic emulation. Measurements have been made on binary and phase shift masks with different sizes of features and on programmed defects.

Control of line width and profile is gaining more importance in photomask processes as the industry moves toward 45nm node and beyond. In this paper we report scatterometer measurements of CD and profile data from chrome-less mask profile processed using Intel's 65nm and 45nm node technology. As opposed to the highly charging nature of chrome-less plate during CD SEM measurements, scatterometry provides a non-charging optical alternative to measure critical CDs. As for trench depth measurement, scatterometry has big advantage over AFM with its much higher throughput (about 5 seconds vs. >2min). Since quartz plate is very transmittive to lights, we use eliipsometer-based scatterometry instead of conventional reflective-photometer based one. Parameters characterized in this study include line/space CD, contact CD, and trench depth. Correlation to top-down CD-SEM, cross-sectional SEM, and AFM is reported. Line CD uniformity reduction is more than 30% compared to that from CDSEM, due to averaging effect of scatterometry as well less lack of charging during measurements. Depth bias to AFM was around 3nm in both DCCD and FCCD height measurements we performed. The data show that Scatterometry provides a nondestructive way to monitor basic etch profile combined with relatively little time loss from measurement step.

A new calibration method for critical dimension (CD) linearity improvement with an immersion microscope is proposed. Correlation tables of an edge position against CD of the clear pattern and CD of the dark pattern are obtained experimentally. The detected edge position is calibrated with the correction tables. Distance between the calibrated edge positions is output as CD. The experiment result indicates the calibration method improves CD linearity of an immersion microscope. CD repeatability with the calibration method using an immersion microscope is found to be sufficient for 45nm HP masks. As a result, an immersion microscope with our calibration method is available for CD measurement of 45 nm HP masks.

The precise targeting of critical dimension (CD) features on photolithographic masks is an essential part of the mask production process. It is straight forward that the usual decrease of specification numbers can only be achieved using cutting edge CD Metrology tools. That also implies that the most advanced CD tool might change from node to node and over time mask houses accommodate a small variety of different tools. Therefore, it is an important task of current mask metrology to ensure accurate matching and calibration and also to transfer these standards precisely over time. Here, we investigate the influences of the photolithographic mask material and the resist type on critical dimension measurements utilizing one Atomic Force Microscope (AFM), two CD-Scanning electrical microscopes (CD-SEM) by different suppliers and one optical CD tool. Simulating usual mask house strategies we defined one CD tool as golden tool and measured a 700 A chrome mask on it. This reference measurement was then repeated on all other tools and each of them was matched to the golden tool using standard procedures. Once matching was achieved 5 other masks were measured on all tools with exactly the same settings as the reference measurements. In all we varied the material COG, Mosi193, Mosi248, Chrome thickness 700A and 1000A and different resists. We do observe that calibration within the CD SEM tool class works very well for linearity, but with detectable offset in the range of a couple of nm for different reference masks used. Cross-calibration on the other hand from optical CD to CD SEM tools shows significant differences for process variations, layer thickness and different materials. These findings strongly point out that first of all cross calibration is extremely difficult with current metrology tools and can not be utilized for high end products with the necessary precision. And secondly, even matching within tool classes is material dependent which has to be considered for accurate tool to tool matching.

Immersion exposure system with the numerical aperture (NA) greater than unity effectively extends the printing resolution limit without the need of shrinking the exposure wavelength. From the perspective of imaging contact hole mask, we are convinced that a mature ArF immersion exposure system will be able to meet 45nm node manufacturing requirement. However, from a full-chip mask data processing point of view, a more challenging question could be: how to ensure the intended RET mask to best achieve a production worthy solution? At 45nm, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For full-chip, especially for contact hole mask, we need a robust RET mask strategy to ensure sufficient CD control. A production-worthy RET mask technology should have good imaging performance with advanced exposure system; and, it should base on currently available mask blank material and be compatible with the existing mask making process. In this work, we propose a new type of contact hole RET masks that is capable of 45nm node full-chip manufacturing. Three types of potential RET masks are studied. The 1st type is the conventional 6% attenuated PSM (attPSM) with 0-phase Scattering Bars (SB). The 2nd type is to use CPL mask with both 0- and π-phase SB, and their relative placements are based on interference mapping lithography (IML) under optimized illumination. The 3rd type, here named as 6% CPL, can be thought of as a CPL mask type with 6% transmission on the background but with π-phase SB only. Of those three RET masks, 6% CPL mask has the best performance for printing 45nm contact and via masks. To implement 6% CPL for contact and via mask design, we study several critical process steps starting from the illumination optimization, model-based SB OPC, 3D mask effect, quartz etch depth optimization, side-lobe printability verification, and then to the mask making flow. Additionally, we investigate printability for through-pitch contact array, and random contact design. To characterize the printing performance, we use MEEF, and process window (PW) to analyze the simulation data. We conclude that the 45nm node contact hole imaging is well within reach using a mature ArF immersion exposure tool with a robust and well integrated RET mask scheme.

In 193nm optical lithography, immersion technology will enable numerical apertures much greater than 1.0. Furthermore, polarized light is likely to be applied, enhancing the imaging properties of structures with dimensions near the resolution limit. As a result, the consequences of extreme oblique angle illumination as well as polarization effects need to be carefully evaluated for all elements of the lithographic process. This paper explores the aberrations and apodization induced by the pellicle film in hyper NA lithography. In a first step, the angle and polarization-dependent phase errors of a perfectly flat pellicle are investigated and discussed for varying thicknesses. It will be shown that for NAs greater than 1.0 the pellicle induces higher order spherical aberrations which can be in the range of today's scanner lens specifications. Also, the impact of polarizationdependent apodization will be discussed. In a second step, the analysis is extended to the case of a non-flat pellicle due to a given frame bow. Under these conditions, the phase and transmission error is not radially symmetric and, furthermore, is field dependent. It will be discussed under which conditions this effect can lead to a significant pellicle-induced CD signature over the entire image field.

This paper presents an evaluation of the finite-difference time-domain method (FDTD) and of the waveguide method (WG) for the simulation of typical hyper NA imaging problems. In contrast to previous comparisons of rigorous mask modeling methods, which were restricted to the assessment of few near fields, diffraction efficiencies, or aerial images at fixed imaging configurations, we compare the methods in terms of CPU-time and memory requirements, their capability to predict parameter dependencies and more global lithographic process characteristics such as process windows and through-pitch behavior.

Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k₁ conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond. In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IML^TM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.

Mask topography effects arise important components of optical image formation at 45nm node and beyond for attenuated Phase Shift Mask (attPSM). Since calculation of mask topography effects based on rigorous model is very costly, it is unrealistic for Optical Proximity Correction (OPC) and lithography design. This paper investigates an approximation model that takes mask topography effects into consideration. We propose the concept of Effectively Equivalent Mask Patterns (EEMP) method to obtain approximated optical images which include mask topography effects. We found mask space width is the main factor among mask topography effects. For realizing the EEMP method, we introduce and evaluate two approximation methods for mask topography effects. One is the simple space model and the other is the Proximity Mask Opening (PMO) model, which is a model of waveguide effects. EEMP with PMO model can improve prediction accuracy at both 1-dimensional and 2-dimensional patterns and increase in run time for EEMP with PMO model is 40 percent of that required for thin film simulations.

For advance semiconductor manufacturing, patterning contact and via mask layers continue to be major challenge. As a result, RET's beyond the current standard 6% attPSM technology are being pursued with a goal of reducing the k₁ for hole patterning to the range of 0.35 - 0.40. IML Technology has shown promising results as a possible solution which employs strong off axis illumination (OAI) to achieve the resolution for the dense pitch contacts and the use of sub-resolution scattering bars (SB) for the semi dense to isolated contacts. At the 45nm node, placing SB by simply applying a set of rules is not sufficient for deriving the correct assist feature placements for the entire range of pitches and for the complex, randomly placed contacts that occur in actual device patterns. IML Technology utilizes modeling to locate where SB should be placed and in the case of high transmission ternary PSM (HTPSM) and CPL, defines the phase of the SB relative to the contacts being imaged. To generate such reticle designs, highly complex interference maps are calculated and from this optical interference behavior, the reticle pattern is derived. Previously, the reticle pattern derived in such a manner was extremely complex raising a question as to how feasible such an approach would be in a manufacturing environment. New algorithms which simplify the mask pattern while maintaining the resolution enhancement capability of IML have been developed. The objective of this work is to demonstrate a manufacturing methodology that utilizes IML Technology and is capable of meeting the requirements for the 45nm node designs. We will explore the application of this method 6% attPSM and CPL reticle designs which containing contact patterns that are representative of production devices. To define the SB for what are effectively randomly placed contacts over a wide range of pitches from dense to isolated, IML Technology is used. This modeling algorithm is based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern. This technique provides a model-based approach for placing all types of assist features on both clear field and dark field patterns for the purpose of enhancing the printing resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. By implementing newly developed algorithms, simplified reticle patterns are generated which maintain the optimum SB placements determined by the IML process.

The bilayer approach of embedded attenuated Phase Shift Masks (EAPSM), causing phase shift and transmission by two different materials offers advantages compared to the single layer solution. Three different PSM blank types with the stacks Ta/SiO₂-6%, Ta/SiO₂-30% and Ta/SiON-30% have been manufactured and characterized. Afterwards, identical line pattern of different feature sizes and duty cycles have been patterned in each of the three PSM types as well as in MoSi for reference. Using the AIMS^TM fab 193i tool we have evaluated the lithographic performance of the four PSM in terms of contrast, normalized image slope (NILS), process latitude and process window. Improvements of up to 20% contrast, 10% NILS and 65% exposure latitude have been achieved for the Ta/SiO₂ 6% stack compared to the MoSi material with the same transmittance. In addition, the high transmission PSM clearly offers advantages in contrast, NILS and exposure latitude especially for smaller features.

The immersion lithography for 45 nm generation has been developing aggressively for smaller critical dimension of semiconductor devices. The polarization lithography system is indispensable to have an advantage to use the immersion lithography with hyper NA (>1.0). As pattern size becomes smaller, mask induced polarization effects to polarization of exposure image seems not to be negligible. There are several issues about mask induced polarization. But dominant factor for mask induced polarization effect is not understood well. In this paper, in case of monolayer mask of att.PSM, degree of polarization (DoP) strongly depends on film thickness and extinction coefficient from simulation and experimental results. DoP depends on material factor. And in case of double layer mask, DoP depends on total film thickness and extinction coefficient of both upper layer and bottom layer. So, DoP depends also on structure of mask.

In the exposure using ArF immersion exposure tool, under the conditions in which the mask pattern pitch is smaller than a several times of the exposure wavelength, diffraction light distribution cannot be predicted correctly by the Kirchhoff approximation mask model, and therefore, rigorous Electromagnetic Field (EMF) analysis is required. In particular, in the dense L&S formation using oblique illumination and an attenuated phase shift mask (att-PSM), the intensity of 0th and 1st diffraction lights changes as pitch shrinks. In high density L&S formation, it is necessary to reduce a mask error enhancement factor (MEF) and to obtain sufficient exposure latitude. We consider the following two contrast control knobs: (1) optimizing the transmittance of attenuated mask material, (2) optimizing mask bias. The important image characteristics are normalized image log slope (NILS) and dose-MEF. Dose-MEF means a dose to size change per mask critical dimension (CD) change. We performed a simple optimization for exposure-defocus window of dense L&S pattern reflecting consideration of the mask EMF model for half pitch 45nm L&S imaging using att-PSM and oblique illumination. We explain the characteristics of the contrast control knobs and their effectiveness. An optimized combination of contrast control knobs depends on the capability of mask CD process as a smallest limit of mask CD and mask CD uniformity.

Most IC manufacturers are considering MoSi to be the material of conventional 6% attenuating phase-shifting masks (attPSM) in hyper-NA lithography (50 nm half pitch node and smaller). However, simulation results show that Cr-based binary-intensity mask (BIM) outperforms the attPSM at dense lines and spaces (LS) patterns in hyper-NA lithography. A reason lies in the transmitted polarization state through the mask. The attPSM is found to be a transverse-magnetic polarizer for hyper-NA imaging, while the BIM acts as a transverse-electric polarizer, which is beneficial for imaging. Using a metal-based absorber of the attPSM has potential for improving the degree of polarization of transmitted light. In our previous work absorber thickness of bi-layer attPSM, i.e. Ta/SiO₂, was optimized through three-dimensional electromagnetic field (3D-EMF) simulations for better imaging performance than the MoSi attPSM. In this study, the thickness-optimized Ta/SiO₂ attPSM was fabricated to compare the imaging performance with the standard Ta/SiO₂ and MoSi attPSMs with 6% transmission and 180^o phase shift. The thickness-optimized Ta/SiO₂ attPSM has 1% transmission due to 50% thicker Ta than the standard, while the 180^o phase shift is controlled by SiO₂ thickness. The exposure latitude of 45 nm LS delineated by using an NA1.20 full-field scanner with xy-polarized cquadrupole was 15.7%, 13.4%, and 10.1% with depth of focus of 200 nm for the optimized Ta/SiO₂, the standard Ta/SiO₂, and MoSi, respectively. Line width roughness of the Ta/SiO₂ attPSMs was approximately 5.5 nm for the 45 nm LS, which was comparable to MoSi. Mask-error-enhancement factor (MEEF) of the 45 nm LS was 4.4, 4.9, and 3.8 for the optimized Ta/SiO₂, the standard Ta/SiO₂, and MoSi, though the simulation expected MEEF values of 4.1, 5.5, and 6.3, respectively. Because the transmission and the phase shift measured by normal incidence are not linked directly with the imaging performance in the hyper-NA lithography with off-axis illumination, the mask materials and structures need to be optimized by using 3D-EMF simulators for the better imaging quality.

Laser pattern generators ALTA 3500 and 3700 are widely used for 0.18 micron and above technology nodes in photomask manufacturing. They have low butting, high throughput and high position accuracy, with some weaknesses such as, corner rounding, no proximity effect correction and poor CD linearity when compared to E-beam pattern generators. Optical Proximity Correction (OPC) software was thus created to extend the productivity of laser pattern generators. For contact holes serifs are typically added at the four corners to enhance pattern fidelity. However, the serifs or scattering bars can significantly increase the data size. In our study, we generated serifs for contact holes but applied different exposure strategies: (1) lumping serifs together with the main pattern; (2) exposing serifs and main pattern separately with same dosage; (3) exposing serifs and main pattern separately with different dosages. We examined the results of each approach in terms of contact hole quality, throughput, and inspection results.

Photomask CD control requirements continue to tighten due to inevitable device scaling, in addition to the increasing mask error enhancement factor (MEEF). Managing the total CD error on production masks requires not only that the error contributions from the pattern generator should be minimized, but also that there is a way to handle errors due to the mask process. This paper addresses process-related contributions such as the CD signatures from mask developing and etching, and how their impact on the total CD error range can be reduced. This is accomplished using the on-line ProcessEquilizer^TM function in the Sigma7500 DUV laser pattern generator. Long range and medium range process CD errors are major contributors to the total CD error range. These errors can be classified as being either pattern-independent or pattern-dependent. Pattern-independent errors may occur in the bake, develop and etch process steps. These errors are by definition static from mask to mask, and can therefore be mapped and compensated by local sizing of the mask pattern data. Pattern-dependent errors typically originate from loading effects, for example, in plasma etching. If such errors can be predicted from the pattern density variation across the mask, then they can also be corrected for with local sizing. The on-line ProcessEqualizer^TM function performs local sizing, and offers a significant advantage over off-line solutions that have the drawback of requiring flattening and refracturing of the pattern data. Local sizing is performed in parallel with writing in the Sigma7500, and has no effect on throughput. In this paper the ProcessEqualizer^TM function is described, including how it is operated in the maskshop. Results are presented demonstrating the performance of the ProcessEqualizer^TM for handling global CD error signatures.

In order to make the mask for the photolithography, e-beam direct writing system has been used because e-beam source is most controllable among the direct systems. However, the development of the new e-beam system is scheduled slowly and there is no conspicuous breakthrough technology to improve the quality of the mask comparing to the wafer exposure tool development. Lately, a new laser writing system, Sigma7300 is introduced and shows 200x reduction projection system and very high throughput relative to the e-beam direct writing system. Because it can write the full layout in a mask less than 4 hours, the high reproducibility is expected. Although the current tool is using KrF light source and 0.82NA reduction projection lens column, the higher resolution tool using the ArF light source can be expected in the future. In this paper the possible resolution limit of the Sigma7300 is discussed and the application example for the mask fabrication. To estimate the process capability, the optical simulation is performed and compared with the experimental results. Because its patterned image is not so clear like the e-beam writer, the pattern rounding, the line-end shortening, and the minimum assist feature are discussed with the patterns of the e-beam writer. At the end the important qualities of the mask like defects are compared with the results of the e-beam system.

The higher productivity of the DUV laser mask lithography system compared to the 50-KeV e-beam system offers the benefit of mask cost down at low k1 lithographic process. But the major disadvantage of the laser mask writing system is rounding effect of contact hole and line end. In this paper, we study wafer process margin effect of corner rounded contact hole and present mask CD specification of corner rounded contact hole written by DUV laser lithography system compared to 50KeV writing tool. The contact hole rounding changes contact hole area at the same mask CD and also change MEEF(Mask Error Enhancement Factor) even though the contact hole area is compensated by adjusting mask bias. If one change EBM3500 mask writer machine to Alta4300 mask writer machine for 160nm contact hole using KrF and 6% HT-PSM, one has to change mask bias, 3.2nm, to meet same wafer process condition.. The MEEF of ALTA4300 mask is 1.6% higher than that of EBM3500 mask at same effective target mask CD. And the mask CD specification written by ALTA4300 has to be set more tightly about 1.3 ~ 1.5% to meet same wafer process margin with EBM3500 mask.

The performance of electron beam reticle writer EBM-5000(NFT) was examined with higher current density. The current density was raised up to 70A/cm² against to its standard current density 50A/cm², and sufficiently good results were obtained with that operating condition. We concluded that the performance with that operating condition was good enough to produce photomasks for 65nm node devices.

The composite critical dimension (CD) and registration performance of a photomask is limited partly by systematic constituent mask lithography tool errors. Test masks can be designed specifically to isolate these error sources so they can be measured and characterized independently from other error sources. This methodology allows the creation of a composite CD and registration error budget that can be used to realistically specify mask lithography tool requirements and predict actual performance on masks from these tools. In this study, we investigate the local CD and Registration errors that occur within a single deflection field on the JEOL JBX-9000MV vector shaped beam (VSB) electron-beam mask lithography system. Test patterns were designed to hold proximity, fogging, and loading effects constant and thereby show the true constituent error of the system. One advantage of using the JBX-9000MV in this study is that the step-and-repeat stage motion makes the position of each feature within the deflection field unambiguous compared to other VSB tools that use continuous stage motion. It is therefore relatively straightforward to characterize and compensate deflection errors. The authors will present experimental characterization of the constituent errors observed within a single deflection field. In addition, we will show how these errors can be controlled through increased shot settling time, increased deflection calibration, and multi-pass writing.

As photomask complexity has increased, mask manufacturing has become significantly more challenging. Tightening specs on defect performance, resolution, and CD control have pushed mask manufacturing to achieve levels that nearly match wafer capabilities. To meet wafer manufacturing needs, mask production requires high yield and quick turn-around time, resulting in an increased demand for very high equipment reliability. In-line resist coating capability is important to meet these demands; both for robust 2^nd level phase-shift coating processes, and the enablement of advanced 1^st-level process development with new resists and new resist process conditions. Intel Corporation worked with Tokyo Electron Ltd (TEL) to bring one of the first CLEAN TRACK ACT M (ACT M) units through design, acceptance tests and into manufacturing. TEL's CLEAN TRACK ACT M is a resist coating tool based on the CLEAN TRACK ACT12 (ACT 12) wafer manufacturing platform, and contains multiple mask-specific modules including advanced softbake oven units, edge-bead removal modules, and cleaning systems. After setup and optimization, the tool shows impressive performance, (for example, within-plate thickness uniformity of < 8A (3s) for certain processes). The motivation of the tool layout is discussed thoroughly. Elements of the module designs and their performance are shown. The acceptance testing performance is presented and includes: cleaning capabilities, oven performance, thickness performance, coating defect levels and edge bead removal capabilities. Finally, there is a limited discussion of manufacturing performance.

The temperature during electron-beam lithography (EBL) rises locally by a few tens or hundreds of degrees, causing change of resist sensitivity and leading to variation of critical dimensions. A method to increase the throughput of writing without causing additional linewidth error is necessary to reduce the cost of a mask. Two methods of correction were examined. In the first method, the exposure doses for individual flashes were adjusted so that the heating error was suppressed. The second correction method took into account the fact that the adjustment of exposure doses for individual flashes corrects for heating; however, it also changes proximity effects. In turn, dose modulation in proximity correction leads to different temperature increases. Both effects were taken into account simultaneously. The exposure doses of flashes were determined to correct for both effects.

Establishing parameters and tuning a dry etch process is an important task in maskmaking. Simulation should complement the time-consuming experiments to reduce cost and shorten development time. TRAVIT is a dry etch simulation tool that has been developed to simulate etch profiles, linewidths, and microloading dependent variation of critical dimensions (CD) resulting from dry etch. The software accepts GDS patterns, materials, initial resist profile, and process parameters. A mathematical model was further developed for more accurate predictions of etch profile while keeping simulation speed high to account for CD variation. Special attention was given to the footing effect. It contributes to significant CD variation if the etch time after end-point detection is not long enough. On the other hand, overetch leads to increased etch bias, which is not desirable. The simulation helps to optimize the post-etch time and minimize CD variation and bias.

CPL technology is one of the powerful methods for Resolution Enhancement Technology. With high NA and strong off-axis illumination CPL has a very high resolution and is capable of printing complex 2D patterns. Image using off-axis illumination with an attenuated phase shift mask can also improve process latitude. We can combine two technologies in one mask with same off-axis illumination condition to have more flexible application. Normally CPL technology is applied in binary mask and Qz is etched for 180 degree phase. To fulfill this hybrid mask we can apply Qz etch in current normal attenuate PSM blank and E-Beam 2nd writing is also can be applied for the zebra structure. To form the different application in different area we use 5 times writing in this hybrid mask process. Also the Qz etching process is very important because the Qz etching is strongly related to the Cr-Mosi-Qz three layer profile. So a L9 DOE has been applied for Qz etching parameter fine tuning. We will optimize the phase uniformity, phase linearity, profile, CD linearity and CD proximity through the DOE.

A photomask dry etch process typically uses chlorine and oxygen plasma for chrome etching with resist masking. This gas mixture leads macro- and micro-loading as different pattern density with mask-to-mask and within a mask. Thus, there have been several approaches to reduce chrome etch loading by changing etch chemistry, etch conditions and mask materials. Using hard mask material on the chrome layer can minimize chrome etch loading and reduce chrome etch bias. In this paper, chrome etch characteristics which use hard mask materials is investigated.

In any plasma etch process, there are slight variations in the output of generators, mass flows, and pressure control systems that may sometimes contribute to run-to-run differences in the final product. Even excluding material differences, endpoint times can vary somewhat, requiring an accurate endpoint system to stop processing at the appropriate time. The most widely accepted systems for plasma endpoint detection are based on optical emission spectroscopy (OES). OES-based endpoint systems analyze the visible and near-visible electromagnetic radiation emitted by the plasma in order to detect subtle changes that occur when a film has been completely etched. A signal can be constructed from this data and used to stop or otherwise modify the process. Other methods exist for detecting endpoint. Laser reflectance is well known to photomask etch engineers, but there are also lesser known methods that depend on detecting changes in pressure, DC bias, or match network positions. Each system has its own unique set of strengths and weaknesses. While all of these systems are quite capable of detecting endpoint under normal circumstances, the requirements of low load photomask etching are extremely demanding. Therefore, a need exists to enhance endpoint detection on low load photomasks. Our proposed method is a multi-sensor system that includes measurements of several process parameters in addition to emission spectra to generate an endpoint signal that is more robust than an endpoint signal produced by a single sensor.

Requirements to meet the 45nm technology node place significant challenges on Mask makers. Resolution Enhancement Techniques (RET) employed to extend optical lithography in order to resolve sub-resolution features, have burdened mask processes margins. Also, Yield compromises loom with every nanometer of error incurred on the Mask and the Device platforms. RET techniques, such as Optical Proximity Correction (OPC), require the Mask Etcher to achieve exceptionally tight control of Critical Dimensions (CD). This ensures OPC feature integrity on the mask and resultant image fidelity of OPC structures, as well as, subsequently high and sustainable yields. This paper talks about 45 nm Chrome etch challenges and how Applied Materials Tetra II^TM etcher provides solutions to these challenges.

Mask Etching for the 45nm technology node and beyond requires a system-level data and diagnostics strategy. This necessity stems from the need to control the performance of the mask etcher to increasingly stringent and diverse requirements of the mask production environment. Increasing mask costs and the capability to acquire and consolidate a wealth of data within the mask etch platform are primary motivators towards harnessing data mines for feedback into the mask etching optimization. There are offline and real-time possibilities and scenarios. Here, we discuss the data architecture, acquisition, and strategies of the Applied Materials Tetra II^TM Mask Etch System.

One means of extending the limits and lifetime of current lithography platforms for 45nm and beyond is the development of resolution enhancement techniques (RET) in the form of optical phase-shifting masks (PSM). By employing optical interference from 180° shifted lithography emission, PSM masks are able to enhance feature resolution at the wafer. This is particularly important for sub-wavelength features (i.e., features with critical dimensions less than the lithography wavelength) where line resolution can be severely degraded without such techniques. For these PSMs, the challenge is to provide highly uniform quartz etch performance across the entire active area of the mask for various feature sizes and local loads. Micro-loading (a.k.a. RIE lag or reactive ion etch lag) and phase angle range are key performance parameters to control. As the demands for these parameters tighten and mask costs rise, strict performance control is required for all PSM mask varieties utilized in the mask shop. In this paper we will discuss process improvements for the Applied Materials Tetra II^TM chromeless phase lithography (CPL) etch application. In particular, the discussion will focus on recent process improvements in phase uniformity and RIE lag for our chrome hard mask CPL etch process. Results from modifications to the etch process are presented. Feature profiles are also discussed with examples showing near vertical sidewalls and no micro-trenching.

As pattern feature sizes on the wafer become smaller and smaller, requirements for CD variation control has become a critical issue. In order to correct CD uniformity on the wafer, the DUV light transmission distribution of the photomask was altered using an ultra-fast pulsed laser technology. By creating a small scattering pixel inside the quartz body of the mask, a multitude of such points creates Shading Elements inside the quartz according to a predetermined CD variations distribution map. These Shading Elements reduce the dose of scanner's laser illumination onto the wafer per a local area. Thus by changing the local light intensity, inside the exposure field, to a required level during the photolithographic process the wafer CD is changed locally inside the field. This complete process of writing a multitude of Shading Elements inside the mask in order to control the light transmission and hence wafer level CD locally is called the CD Control (CDC) process. We have evaluated the tool utilizing Ultra fast laser pulses (CDC 101) for local transmission and CD controllability on the wafer. We used Binary and Att-PSM test masks and three kinds of test patterns to confirm the sensitivity of transmission and CD change by the attenuation levels of Shading Elements which is sequentially changed from 0% to 10%. We will compare the AIMS results to printed CD on wafer or simulation results, so that we can correlate the transmission change and CD change by the attenuation levels. This paper also reports the CD uniformity correction performances by using attenuation mapping method on Binary mask. We also cover how Shading Elements affect the phase and transmission on the Att-PSM.

The dissolution behaviors of chemically amplified resists for electron beam lithography (EB CARs) have been investigated using the technique of quartz crystal microbalance (QCM) method. We report the first direct measurement of the dissolution rate of EB CARs and the comparison with CAR of using KrF exposure in wafer fabrication. The EB CAR for nano-imprint lithography mold making was also evaluated by this technique, and then resolved 50 nm line and space patterns using conventional 50 KV variable shape beam writing system. The understanding of dissolution kinetics of EB CARs is capable of designing high performance resists in near future.

We have proposed and modified a model of drying process of polymer solution coated on a flat substrate for flat polymer film fabrication and have presented the fruits through Photomask Japan 2002, 2003, 2004 and so on. And for example numerical simulation of the model qualitatively reappears a typical thickness profile of the polymer film formed after drying, that is, the profile that the edge of the film is thicker and just the region next to the edge's bump is thinner. Then we have clarified dependence of distribution of polymer molecules on a flat substrate on a various parameters based on analysis of many numerical simulations. Then we done a few kinds of experiments so as to verify the modified model and reported the initial result of them through Photomask Japan 2005. Through the initial result we could observe some results supporting the modified model. But we could not observe a characteristic region of a valley next to the edge's bump of a polymer film after drying because a shape of a solution's film coated on a substrate in the experiment was different from one in resists' coating and drying process or imagined in the modified model. In this study, we improved above difference between experiment and the model and did experiments for verification again with a shape of a solution's film coated on a substrate coincident with one imagined in the modified model and using molar concentration. As a result, some were verified more strongly and some need to be examined again. That is, we could confirm like results of last experiment that the smaller average molecular weight of Metoloses was, the larger the gradient of thickness profile of a polymer thin film was. But we could not observe a depression just inside the edge of the thin film also in this improved experiment. We may be able to enumerate the fact that not an organic solution but an aqueous solution was used in the experiment as the cause of non-formation of the depression.

Three types of high transmission attenuated phase shift masks were evaluated. The attenuating materials were obtained from commercial and non-commercial sources. Various key performance metrics were investigated. Blanket film transmission and reflection was measured at various wavelengths. Laser durability and cleaning durability were measured. Standard dry etch processes were used for each film and the profile and surface properties were compared. Final mask transmission and phase were also measured. The summarized results show clear benefits of using some high transmission materials relative to others.

Megasonic cleaning has been a traditional approach for the cleaning of photomasks. Its feasibility as a damage free approach to sub 50 nm particulate removal is under investigation for the cleaning of optical and EUV photomasks. Two major mechanisms are active in a megasonic system, namely, acoustic streaming and acoustic cavitation. Acoustic streaming is instrumental in contaminant removal via application of drag force and rolling of particles, while cavitation may dislodge particles by the release of large energy during cavity implosion or by acting as a secondary source of microstreaming. Often times, the structures (substrates with or without patterns) subjected to megasonic cleaning show evidence of damage. This is one of the impediments in the implementation of megasonic technology for 45 nm and future technology nodes. Prior work suggests that acoustic streaming does not lead to sufficiently strong forces to cause damage to the substrates or patterns. However, current knowledge of the effects of cavitation on cleaning and damage can be described, at best, as speculative. Recent experiments suggest existence of a cavity size and energy distributions in megasonic systems that may be responsible for cleaning and damage. In the current work, we develop a two-dimensional atomistic model to study such multibubble cavitation phenomena. The model consists of a Lennard-Jones liquid which is subjected to sinusoidal pressure changes leading to the formation of cavitation bubbles. The current work reports on the effects of pressure amplitude (megasonic power) and frequency on cavity size distributions in vaporous and gaseous cavitation. The findings of the work highlight the role of multibubble cavitation as cleaning and damage mechanism in megasonic cleaning.

Researchers have linked the occurrence of reticle haze to many parameters which include cumulative irradiation, the greater use of 193nm in low-k1 lithography, humidity and the presence of ammonium with other process contaminants. Published methods of contaminant reduction include 1) volatilization by thermal treatment 2) induced preemptive crystallization with 172nm eximer energy followed by subsequent ozone-water and megasonic treatments and 3) hot water treatments. In this paper we explore the process characteristics necessary to achieve a new method of continuous ion removal which includes sustained plate temperature during UV treatment and the sublimation of ammonium crystals. The application of these principles are consistent with room temperature (RT) fluid flows which allow us to work within a regime of negligible phase angle, negligible transmissivity change and silicon nitride removal efficiencies above 99% for particles as small as 80nm.

Photomask pellicles play an important role in determining final photomask flatness, which is important to photomask optical performance. This study explores the impact of the pellicle frame flatness and pellicle-to-mask adhesive on photomask flatness. In addition, the change in mask flatness as a function of time after pellicle mounting is studied. Implications of these results on photomask manufacture and photolithography are discussed.

The paper analyses the factors which influence minimal features of detected adjacent defects during the use of traditional die-to-database method of inspection of reticles and also during the use of new Parametric Models of Pattern Features Comparison method (PMoPFC method). The analysis of influence of a set of factors, describing an instrumental error of the automatic reticle inspection system, and of a set of factors, describing a reticle patterning process, on various types of adjacent defects is made. Some relations are given, describing interrelation of the size of the minimal adjacent defect and the pixel size of the automatic reticle inspection system. A concept of the optimum and preset sizes of the minimal detected defect is introduced. The analysis of dependence of the number of false defects on the size of the preset minimal detected adjacent defect is made, as well as a criterion to choose an optimum capability of detection of adjacent defects is given. In conclusion, parameters of automatic reticle inspection systems developed at "KBTEM-OMO" of Planar Concern are given, specifying the adjacent defects detection capability. Also the parameters of the systems designed for 0.35 μm, 0.18 μm and 65 nm processes are described.

Deep ultraviolet (DUV) femtosecond-pulsed laser ablation has numerous highly desirable properties for subtractive photomask defect repair. These qualities include high removal rates, resolution better than the focused spot size, minimized redeposition of the ablated material (rollup and splatter), and a negligible heat affected zone. The optical properties of the photomask result in a broad repair process window because the absorber film (whether Cr or MoSi) and the transmissive substrate allow for a high degree of material removal selectivity. Repair results and process parameters from such a system are examined in light of theoretical considerations. In addition, the practical aspects of the operation of this system in a production mask house environment are reviewed from the standpoint of repair quality, capability, availability, and throughput. Focus is given to the benefit received by the mask shop, and to the technical performance of the system.

Defect disposition and qualification with stepper simulating AIMS tools on advanced masks of the 90nm node and below is key to match the customer's expectations for "defect free" masks, i.e. masks containing only non-printing design variations. The recently available AIMS tools allow for a large degree of automated measurements enhancing the throughput of masks and hence reducing cycle time - up to 50 images can be recorded per hour. However, this amount of data still has to be evaluated by hand which is not only time-consuming but also error prone and exhibits a variability depending on the person doing the evaluation which adds to the tool intrinsic variability and decreases the reliability of the evaluation. In this paper we present the results of an MatLAB based algorithm which automatically evaluates AIMS images. We investigate its capabilities regarding throughput, reliability and matching with handmade evaluation for a large variety of dark and clear defects and discuss the limitations of an automated AIMS evaluation algorithm.

This work represents one in a series of ongoing papers demonstrating the potential utility of integrating advanced photolithographic simulation software into a mask repair tool to provide immediate defect or repair printability feedback. The equipment used here is an AFM-technology based nanomachining photomask repair tool where the high-accuracy AFM surface topography data is fed directly into software applying rigorous solutions to Maxwell's equations. The nature of these systems allows for process endpoint printability evaluation, not restricted by the optical limitations of any given apparatus, of any micro to nano-scale region of the mask in-situ with the defect repair process. In prior work, the capability of this approach was shown in good correlations to AIMS^TM at 248 and 193 nm wavelengths, for binary mask repairs of varying dimensions, with no applied optical aberrations to the simulation. In this examination, the development of this system is taken to its next step by introducing it to a real photomask production environment, using production masks, for performance substantiation. Methodologies are shown for the best use of this system in streamlining the mask production process.

Optical proximity correction (OPC) is an essential technology for critical dimension (CD) control in Low-k1 lithography. As technology node becomes tighter, more aggressive OPC is required. However, the number of so-called HOT-SPOTS is increasing dramatically. To apply OPC correctly and efficiently, we should consider the total optimization of the process in close connection with data processing, reticle and wafer fabrication process. Conventional one-dimensional CD measurement is no longer suitable for complicated two-dimensional (2D) patterns generated by OPC (e.g. JOG and SERIF). For quality assurance of mask pattern, a metrology of complicated 2D OPC patterns has been required. In our previous report, we proposed a lithography simulation based on edge extraction from a fine pixel SEM image of an actual photomask. This method is very effective for evaluating quality of 2D OPC mask patterns. Employing the method, we developed a system for guaranteeing 2D OPC patterns before shipping the mask to a wafer factory (Fig. 1). In PMJ2005, we presented some specifications required for an SEM, which was one of the key factors of this method. We estimated how factors such as field of image, image resolution, positioning error, and image magnification affect lithography simulation based on fine pixel SEM image. For mask pattern quality assurance of hp65, we found that the field of image of larger than 16μm square, the pixel size of less than 3nm, the positioning error of within +/- 1μm and the magnification error of less than 0.3% were acceptable (Table 1). Under these conditions, wafer image can be predicted with sufficient accuracy by the simulation. And then, in BACUS2005, we reported on a new SEM that was able to satisfy these specifications. In this paper, we report some evaluation results of distortion caused by not only magnification error but also rotation and position error using actual fine pixel SEM image. We will also present our evaluation results of the errors in various pattern conditions such as Dark Field/Bright Field, Pattern density.

As required CD (critical dimension) measuring accuracy is tighter, it is necessary to enhance the repeatability of CD-SEM on photo-mask, by optimizing charge up, scan speed, beam size, acceleration, current and temperature control. CD-SEM shows sparkle noise which degrades the image of CD-SEM. And defocus is also getting the source of worse gauge R&R. We evaluated the effect of defocus and noise on CD repeatability by extracting CD from gradient value of image after anisotropic nonlinear diffusion filtering on SEM image. As SEM image is measured after averaging the intensity of image on range of interest (ROI) to remove scan noise, anisotropic nonlinear diffusion (AND) which has different diffusivity according to direction, is efficient tool to get smooth pattern without averaging. This smoothing technique is effective in measuring isolated pattern on mask which is difficult to measure around corner. Some simple CD measuring algorithms are available to get better CD repeatability. Using the maximum intensity and gradient of image, we were able to measure CD on various shaped patterns with enhanced repeatability.

The ever-narrowing specifications for high-end masks can only be derived from the continuous improvement of all manufacturing processes. Here, the metrology is crucial prerequisite since the development relies almost entirely on measurement results. In this paper we will address this relation by showing how the limits of metrology repeatability and reproducibility define also the limits of process development. In particular, we will show that improved metrology tool performance on resist results in a deeper understanding for the dry etch process. This is very important since resist metrology is not part of the ITRS roadmap and serves "only" as a supporting engineering process. Better short-term repeatability results in the possibility to detect more variables that might influence the etch regime. As an example, results from two CD scanning electron microscopes (SEM) were compared with very different short-term repeatability. The better knowledge based on the more accurate metrology data allows then to optimize the process within a process space which was previously not detectable with the other tool. An estimate is given how much this influenced the final performance of the process. We conclude from these results, that metrology parameters not covered in standard roadmaps become increasingly important to achieve process development goals in other process areas.

Spectrophotometry has been applied to the characterization of pattered mask line-width. Variations in the line-width by few nanometers can be distinguished by comparing spectrum profiles of reflectance or transmittance in spectrophotometry. It can be theoretically explained that the variations in the spectrum profiles are caused by CD bias of the patterned film. Experimental results also show that the positions of the spectrums along wavelength axis are related to the CD bias measured under CD-SEM. As a result, both spectra could be used to estimate quickly the line-width of patterned mask without in-depth analysis.

Rising complexity and density of device designs result in a tremendous increase of reticle inventory costs. Due to advanced RET solutions, reticle acquisition time and prices, as well as the data volume to be managed, increase significantly. High-energy exposure tools and new categories of progressive defects have an increasing impact on the reticle life time. New technologies, smaller feature sizes and shorter wavelengths raise challenges like haze, crystal growth and ESD. State of the art FABs have an ever-increasing amount of automation systems to run the processing steps. This requires all supporting systems to keep pace. New tool generations have very large throughput capability. So delays due to reticle availability have an even larger impact on output than previously. The real-time dispatching system needs to be able to automatically select and reserve suitable reticles to avoid exposure tool idle time. Reticles are a major fab asset and are one of the bottlenecks in achieving maximum efficiency in semiconductor manufacturing. An intelligent and fully automated reticle life cycle management is crucial to meet today's target quality and production goals at reasonable cost. All reticle data - from cradle to grave - needs to be stored in one central database to ensure consistency, performance and accuracy of data and trend analysis. The solutions described mainly result from the ramp-up at a new 300mm DRAM semiconductor facility. One of the key requirements was to fully automate the entire reticle data flow without human interaction or paper work. The given customer business rules were modeled to automatically monitor the reticle work flow. At the same time, highest flexibility was required to easily adjust the configuration to upcoming changes or improvements.

Small process window in ultra-low k₁ lithography (k₁<0.35) poses difficulties for judgment of the availability of high-end photomasks for preliminary exposure tools for high volume production ramp-up. Also, our previous judgment flow of high-end photomasks availability has several concerns. Therefore, the ultra-low k₁ lithography requires accurate judgment methodologies for high-end photomask availability with short turn-around-time (TAT). In this paper, we propose a new concept concerning hot spot-based judgment flow which consists of two stages for high-end photomask availability. Our proposed flow permits judgment of high-end photomask availability for high volume production ramp-up with short TAT.

Maskless lithography is one of the possible solutions to manage the escalating mask costs and demands for faster production cycles. One of the major issues with the maskless lithography technology however is the management and transfer of the enormous data volumes required to define the chip structures. Ensuring competitive and reliable operation requires dedicated preparation and buffering of the lithography data to be transmitted to the exposure unit. An optimized dedicated architecture and careful signal integrity design for proper functionality are needed due to the high data rates and the highly parallelized system operation. This paper presents the implementation aspects and the design of a high-speed transmission system solution for maskless lithography systems. The introduced solution treats a field programmable gate array (FPGA) based implementation for a latency-sensitive high speed lithography system.

As pattern size becomes very small, it has been getting difficult to correct an EB proximity effect accurately. We have developed a new proximity effect correction which corrects dose by simulating the energy scattering. It can correct accurately in reasonable computing time. We will explain how to improve efficiency of energy deposit simulation and evaluate the algorithm in this paper.

Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool for small-volume logic-LSI fabrication. The EB exposure time will be greatly reduced by applying character-projection (CP) aperture. But the applicable number of CP aperture is limited to 25-400 depending upon EB lithography apparatus. The cell-based logic LSIs are composed of standard-cells (SCs) whose number is 400-1000. Therefore, it is impossible to implement all SCs as CP apertures, because the SCs are placed to 4-directions in general. We had proposed the new technique named 'Character-Build (CB) standard-cell', and demonstrate the most of the combination-logic SCs can be composed by only 17 CP apertures. In this paper, not only combination-logic SCs but also sequential-logic SCs are considered. The number of EB-shots and the chip-area are estimated for some sample circuits. Compared to the simply-limited SCs, The EB shot number is 30-40% reduced by using proposed CB standard-cell, when the CP aperture numbers are 20-30. Moreover, CB standard-cell was advantageous in the module area. Considering 2-directional placement of SCs, the combination of the EB apparatus with 50-100 CP apertures and the CB standard-cell technique may be the best method for high-speed EB direct-writing.

The low-k1 lithography produces large volumes of mask data resulting in more complex optical proximity effect. It puts heavy burden on MDP flow and affects turn around time (TAT). To solve this problem, DP (Distributed Processing) method has been introduced. Even though DP is a very powerful tool to reduce the MDP time, there still might be unexpected pattern drop issue. In order to deal with this issue, the verification step was added in MDP flow. The present verification method is a boolean operation using 2 machine data after converting as a same way. However this verification method has two shortcomings. First, this method is not suitable to detect the same error caused by same software bug. Secondly, it needs double conversion time. A new verification method should be much faster and more accurate than the current verification method. In this paper, the new verification method will be discussed and experimental results using the new verification method will be shown with comparing to the old verification method.

Over the last 5 years, Japanese consortium, Semiconductor Leading Edge Technologies Inc. (Selete), lead the way in developing unified mask data format. Specification of the format was released as OASIS.VSB and registered to SEMI standard, P44. It is expected that using OASIS.VSB would reduce TAT and improve efficient usage of data infrastructure. OASIS.VSB has advantages for mask data preparation since OASIS.VSB is based on OASIS^TM (SEMI P39) and OASIS compliant software is already commercially available. Although fundamental evaluation of OASIS.VSB have been made by Selete on technical feasibility with VSB mask writers, its performance and advantage of data handling improvement is still controversial. We have been evaluating OASIS.VSB in order to estimate the impact of data handling improvement at mask manufacturer. Figure 1 shows that OASIS.VSB has good compression ratio compared to certain VSB mask data format. Although compression ratio partly depends on data and conversion software, OASIS.VSB is about 0.7 times as small as VSB data format on weighted basis average. Furthermore, we have confirmed by simulation that OASIS.VSB can hardly affect shot count and writing time. Unification of mask data format by OASIS.VSB can realize flexible mask data preparation (MDP) and reduce a cost of data storage. To achieve further TAT reduction, it is necessary to apply OASIS.VSB to not only mask writing data but other mask making processes such as die to database inspection and mask rule check (MRC).

OASIS format has begun to be accepted in the field of mask data processing gradually. Major EDA venders have announced their support of OASIS format and new versions of EDA tools which can handle with OASIS files have been shipped one by one. Still, there are great difficulties to convert all the data processing flow from old GDSII to new OASIS. One of the major issues is a problem of verification. Since all the tools have not been completely stable and reliable, there should be a method to verify whether the data is converted to OASIS without any problems. In addition to that, the integrity of the OASIS files itself have to be checked. In general, OASIS has two aspects for the mask industry. One is a role as a new replacement of GDSII. The other is OASIS.VSB, which is a unified format defined for the description of fractured EB data. SII NanoTechnology has been developing a new software package called SmartOASIS. SmartOASIS provides lots of practical functions to enable easy transition of data processing flow from conventional GDSII or EB formats to OASIS.

Optical Proximity Correction improves wafer image fidelity by combining small correction shapes with the original pattern data. Although these small shapes improve the exposure of the wafer image, the increase in total figure count results in longer fracture processing and E-beam writing time to create the mask. In this paper we describe alternative OPC treatment for jogs on non-Manhattan features, which reduce the additional figures produced, and make the data friendlier to the fracture and mask fabrication phases. Illustrations of example pattern data and improvement results in terms of figure counts are described.

Increasing transistor densities, smaller feature sizes, and the aggressive use of RET techniques with each successive process generation have collectively presented new challenges for current fracture tools, which are at the heart of layout data preparation. One main challenge is to reduce the number of small dimension trapezoids (slivers) to improve mask yield since the sliver count reflects the risk of mask critical-dimension errors. Some commercial tools are available for handling the sliver minimization problem in fracture, such as CATS from Synopsys and Fracturem from Mentor Graphics. However, the number of slivers in the existing fracture solutions can be significantly reduced. The integer linear programming (ILP) method has been previously applied to find the optimal fracture but has not explored potential benefits from additional ray-segments. Unfortunately, the ILP becomes prohibitively slow for polygons with the large number of vertices and heuristic partitioning of large polygons may severely degrade the solution quality. In this paper, we propose a new ray-segment selection heuristic which can find a near-optimal fracture solution in practical time while being flexible enough to take into account all specified requirements. We fist divide the rectilinear region with all rays from the concave points and formulate the fracture problem as a sequential ray-segment selection problem. Each ray segment is assigned a weight based on its probability to form a sliver. All ray segments to be selected are placed in a candidate pool. An iterative "gain" based process is used for fast and efficient selecting ray segments from the candidate pool and dynamic update of ray segments and their gains. Further reduction of the number of slivers is achieved by auxiliary ray-segments. The resulted runtime overhead is reduced by a rule-based auxiliary ray-segments addition method which achieves a tradeoff between the sliver number reduction and runtime overhead. Compared with state-of-art sliver-driven fracturing tools, the proposed method reduces the number of slivers in the fractures of two industry testcases by 76.7% and 58.6%, respectively, without inflating the runtime and shot count. Similarly, compared with the previous ILP based fracture methods, the new method reduces the number of slivers by 56.1% and 2.2%, respectively, with more than 60X speedup and insignificant shot count overhead. The reduction in the sliver number is primarily due to the introduction of additional ray-segments. The proposed method can also solve the reverse-tone fracture problem in practical time for large industry testcases.

Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated environment.

Negative etch bias is often used to decrease the minimum linewidth beyond what is possible with lithography alone, for example 110 nm minimum CD in resist and 70 nm minimum CD after etch. If the minimum space that can be opened in resist is, for example, 30 nm a true 70 nm half-pitch can be achieved when an etch shrink is employed. Due to iso-dense bias and other proximity effects, however, positive etch bias can also occur. This leads to the unfavorable situation where litho must print lines in resist smaller than the lines in the final post-etch silicon. Due to positive etch bias, among other factors, it is possible to create a configuration that can be realized from the point of view of etch, but can not be created due to photolithography or mask constraints. Specific trouble spots include boundary regions which transition between one set of DRC rules and another. With a new highly accurate etch model, problematic configurations can be identified and used to modify the design to make the etch, photolithography, and mask construction processes realizable. This paper will demonstrate unrealizable pattern conditions that can be found using a non-linear etch model for OPC[R], leading to layout configuration changes which improve the mask construction and photolithography processes.

A lot of source shapes have been proposed for resolution enhancement in semiconductor exposure field, and so-called OAI (OAI: Off Axis Illumination) in them improves not only the resolution but also defocus behavior. Such kind of small window illumination was realized aperture filter at first stage but there were issues of efficiency of light source and complex OPC due to higher coherency. The advantages of use DOE (DOE : Diffractive Optical Element ) are not only the flexible illumination shape available but also the controllability of intensity profile in addition to the higher efficiency of light source. However DOE design and fabrication to obtain enough resolution are difficult due to the huge design load and leading-edge fabrication. Not enough design and fabrication error lead unintended intensity distribution, and the distribution degrades the resolution and makes OPC less effective so that photomask specification shall be tighter. In this paper, as one example, dipole source shape named "Soft-Dipole" is optimized considering intensity distribution targeting 90nm with simulator and is estimated the impact to resolution and OPC. Then actual DOE is fabricated for the intended distribution and evaluated the behavior with the simulator of the DOE using captured intensity distribution. The result showed Soft-Dipole illumination had possibilities to reduce OPC load with enough resolution. Then the DOE design, the fabrication and the evaluation are discussed in this paper.

The RET Design Flow has become a conglomeration of various point tools and methodologies. Deep sub-wavelength DFM requirements have forced the design and manufacturing communities into very tight collaboration. EDA is also driven to provide an infrastructure to facilitate communication for these communities. Having this infrastructure in place has a direct impact on productivity and quality for which the value added is emphasized here.

In order to realize 45 nm node lithography, strong resolution enhancement technology (RET) and water immersion will be needed. In this research, we discussed about various RET performance comparison for 45 nm node using 3D rigorous simulation. As a candidate, we chose binary mask (BIN), several kinds of attenuated phase-shifting mask (att-PSM) and chrome-less phase-shifting lithography mask (CPL). The printing performance was evaluated and compared for each RET options, after the optimizing illumination conditions, mask structure and optical proximity correction (OPC). The evaluation items of printing performance were CD-DOF, contrast-DOF, conventional ED-window and MEEF, etc. It's expected that effect of mask 3D topography becomes important at 45 nm node, so we argued about not only the case of ideal structures, but also the mask topography error effects. Several kinds of mask topography error were evaluated and we confirmed how these errors affect to printing performance.

The dawn of the Sub 100nm technology has brought many new exciting challenges for lithography process such as Immersion, OPC, asymmetry illumination, and so on. But, these new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as PR defect, ID bias and Mask Error Factor(MEF) are very important, but the most critical of all for lithography engineer is low process margin created by these technologies. In this study, we will be presenting the result of the Illumination based assist feature that enhances the lithography process margin for both Exposure Latitude (EL) and Depth Of Focus (DOF), while retaining safety of the scum generation by positioning the assist feature proportional to the illumination for 60nm device. Also, by automatically generating illumination based assist feature on the peripheral region of the mask, we will show that it levels the Critical Dimension (CD) uniformity for pattern of the same dimension located at both cell and peripheral region of the mask. Results will be tested on the mask feature size of 60nm and will be analyzed for both process margin and CD uniformity.

Sub-resolution assist feature (SRAF) is widely used to improve lithographic performance. Rule-based SRAF insertion has been working well for one dimensional cases but becomes quite complex for 2-dimensional arbitrary layout. In addition, the best rule generation involves a large amount of simulation and empirical data collection. Therefore model-based SRAF insertion is much more desirable especially for 65nm node and below. In this work we use the newly developed pixel inversion method for a true model-based SRAF insertion. We'll extend our work from contact layer to lines and spaces layer to demonstrate the capability of this method for all critical layers of 65nm node. This method will be used in combination with model-based OPC to achieve the required overlapping process window and CD control. Furthermore, the manufacture issues such as mask making time and mask inspection will be examined and reported.

All OPC model builders are in search of a physically realistic model that is adequately calibrated and contains the information that can be used for process predictions and analysis of a given process. But there still are some unknown physics in the process and wafer data sets are not perfect. Most cases even using the average values of different empirical data sets will still take inaccurate measurements into the model fitting process (as Fig.1), which makes the fitting process more time consuming and also may cause losing convergence and stability. This work is to weight different wafer data points with a weighting function. The weighting function is dependent on the deviation (or range or other statistical index) values for each measurable symmetric feature in the sampling space of the model fitting. Using this approach, we can filter wrong information of the process and make the OPC model more accurate (as Fig.2). NanoScope-Modeler is the platform we used in this study, which has been proven to have an excellent performance on 0.13μm, 90nm and 65nm production and development models setup. Leveraging its automatic optical-tuning function, we practiced the best weighting approach to achieve the most efficient and convergent tuning flow.

With the critical dimension of IC design decreases dramatically, to meet the yield target of the manufacture process, resolution enhancement technologies become extremely important nowadays. For 90nm technology node and below, sub rule assistant feature (SRAF) are usually employed to enhance the robustness of the micro lithography process. SRAF is really a powerful methodology to push the process limit for given equipment conditions. However, there is also a drawback of the SRAF. It is very hard to check the reasonability of the SRAF location, especially when SRAF is applied on full chips. This work is trying to demonstrate a model-based approach to do full-chip check of the SRAF insertion rule. First, we try to capture the lithography process information through real empirical wafer data. Then we try to check every SRAFs location and to find any hot spot that has the risk of being printed out on the wafer. Based on this approach, we can then not only apply full chip check to reduce the printability of SRAF. Furthermore, combined with DRC tools, we can find SRAFs that are inserted unreasonably and then apply modification on them.

The mainstream of resolution enhancement techniques (RET) to critical layers is model-based optical-proximity-effect-correction (OPC) at the 90-nm node and below. For model-based OPC, the simulation model is calibrated using a test pattern transferred onto the wafer on a best dose and best focus condition, so process variations (i.e. focus, exposure dose, etc) cause pinching or bridging (open or short error), otherwise called a hotspot. The technique of reducing hotspots by sub-resolution assist features (SRAFs) and litho-friendly layout are already proposed. However, these methods sometimes cannot improve hotspots by design layouts or the post-OPC shapes. We have developed the technique which improves hotspots by additional modification to the post-OPC patterns of hotspots.

For the 45nm node and beyond, ever smaller CD budgets require tighter control over the entire process, demanding more accuracy from optical proximity correction (OPC). With the industry adoption of model-based over the traditional rules-based approach, OPC has come a long way to improve accuracy. Today, it is time to do the same for another important step in the process: dry etch. Here we demonstrate the accuracy of etch modeling for a 45nm node process. All experiments were conducted at IMEC with an immersion scanner using off axis illumination. Etch was achieved using a non-optimal recipe to exhibit an iso-dense bias effect. SEM data was extracted using a novel tool to automatically remove any experimental noise. Model calibration was performed with Progen^TM using standard and novel etch-sensitive structures. Model accuracy and predictability was verified with comparing modeled 2D contours against CD SEM measurements and images.

The contact hole patterning has been huge challenge in the photolithography since sub-100nm node device. There are many difficulties for NA (Numerical Aperture) and illumination optimization, especially since dense and sparse contact holes are mixed in the same mask. The high NA and OAI (Off Axis Illumination) have strong improvements for pattern fidelity and process margin in case of dense contact holes but DoF (Depth of Focus) margin is a problem for sparse patterns. The lithography engineers have two ways to overcome these contact holes patterning problems. The one is using the resist techniques such as resist thermal flow, SAFIER (Shrink Assist Techniques for Enhanced Resolution), RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) and the other is optimizing illumination and mask layout such as SRAF (Sub Resolution Assist Feature), OAI and PSM (Phase Shift Mask), double exposure. This paper will discuss contact hole patterning results using a combination OAI and SRAF with KrF.

This paper presents the impact of hyper-NA (NA > 1) lithography on the specification of mask critical-dimension (CD) uniformity. In order to realize the hyper-NA lithography, it is needed to adopt new technologies such as a liquid-immersion setup and polarized light illuminator. In the immersion lithography, it has been shown that the mask CD tolerance can be relaxed if NA is increased. This relaxation originates from the increase of the exposure-latitude (EL) in defocus conditions. As has also been reported, polarized light imaging enhances the EL of line-and-space patterns. This indicates that the application of polarized light imaging may enable us to relax the mask CD tolerance. In this paper, the mask CD relaxation will be discussed based on lithography simulations. In addition, the influences of mask birefringence and state of polarization in illuminator on the wafer CD will be discussed. Quartz substrate used as a mask blank can act as a rotation retarder, because of the presence of intrinsic stress induced in manufacturing processes. Therefore, the state of polarization of mask-transmitted light is disturbed. As a result, wafer CD is affected both by the mask birefringence and state of polarization in illuminator; hence, specification of mask CD uniformity (CDU) is also influenced. In this paper, the specification of mask CDU will be discussed by taking the effect of the impact of state of polarization in illuminator and mask birefringence into account. These results accelerate the practical use of hyper-NA lithography in 45-nm node.

The global pattern density of a mask is a major factor of etch process-induced CD skew. Logic products have different global pattern densities according to the various area portions of SRAM and logic cells. For example, the pattern densities of 66 devices of 130nm node vary from 34% to 47.7% for active layer and from 14.7% to 26.7% for gate poly layer. In order to compensate the global pattern density effect on CD skew, the process condition change is easy to practice for process engineers. But the process condition change for each device increases process variation and reduces process margin. A direct approach to compensate the global density effect on CD skew is necessary. In this paper, we propose a method to make the global pattern density of a mask uniform at the data preparation stage. Our approach is to resize fill patterns to control the global pattern density. We confirmed that the proposed method is effective to control the global pattern densities of masks to a target density within +/- 1%.

Recent integrated circuit (IC) manufacturing processes require smaller critical dimension (CD) in order to facilitate the development of exposure tools with a higher numerical aperture (NA) and shorter wavelength. Consequently, the depth of focus (DOF) has considerably decreased, and the DOF currently required for 45-nm node devices is approximately 150 nm. Hence, the contribution of mask flatness to the total DOF increases. Inoue et al. systematically and precisely investigated the influence of mask flatness by using a free-standing plate and chucked plate interferometer. In this study, we fabricated several back side chrome (BSC) masks for focus monitoring, determined the flatness of these masks by an exposure experiment, and compared the flatness with that directly determined by using a free-standing plate interferometer. Thus, we verified the possibility of predicting the mask flatness component on an image plane by using the mask flatness data obtained using the interferometer.

In recent years, it has been demonstrated that nanoparticles can be detached and removed from substrates using laser-induced plasma (LIP) shockwaves. While it was experimentally established the effectiveness of the LIP technique for removing nanoparticles in the sub-100nm range, the removal mechanisms were not well-understood. In this article, we introduce a set of particle removal mechanisms based on moment resistance of the particle-substrate bond and discuss their effectiveness and applicability in laser-induced plasma shock nanoparticle removal. The mechanical interactions between nanoparticles and shockwaves are studied by utilizing molecular dynamic simulation approach. The forces and moments acting on nanoparticles are calculated and are related to the detachment mechanisms. It is demonstrated that sub-100nm particles can be detached from various substrates. Experiments and simulations are performed to study the effect of LIP on optical and EUVL/LTEM substrates in terms of substrate damage. Initial experiments and simulations reveal the window of safe operation of LIP and the mechanisms responsible for material alterations if any at close distances of operation of LIP above the substrate.

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.

In the extreme ultra-violet (EUV) lithography, a defect-free mask blank is one of the critical issues for high volume manufacturing. The defects of EUV mask are typically classified into phase defects and amplitude defects. The phase defects, which may be originally included in substrate or generated during multilayer deposition, are not easily detected after the deposition of absorber and buffer films, since an inspection tool using the visible light shows strong absorption in this wavelength range. In addition, it is important to confirm the level of blank mask defects before e-beam writing in order to prevent yield drop of mask manufacturing. Confocal inspection method has been developed and widely used to inspect substrate and blank mask in current optical and EUV lithography. However, this method can only detect defects which are located on flat surface and buried near the surface. In this paper, both the confocal inspection and patterned mask inspection are simulated by rigorous analysis method and also experimentally determined. As a result, simulation shows good agreement with experiments, and thus the simulation tool can be applied to estimate detectability and printability of multilayer defects. For patterned mask inspection, mask near field images are calculated by the rigorous method. Then, aerial images of EUV mask in patterned mask inspection system are simulated and several properties are also investigated.

Nano-imprint lithography (NIL) is expected as one of the candidates for 32nm node and below. We reported in PMJ2005 that we could achieve 30nm resolution for isolated spaces and 50nm resolution for dense features with tools used in commercial mask shops today, and with modification of widely used resist. We also reported that the CD had shifted non-negligibly from the resist to quartz trench, due to the not-vertical pattern profile of the resist. In this paper, we review the resolution limit with current photomask manufacturing tools and the 100keV spot beam writer, and investigate the pattern line edge roughness. We also report our improvement in quartz dry-etch, in particular the improvement in the pattern profile and the etch depth linearity. We found by using the spot beam writer, we can potentially achieve 10nm isolated space and 35nm dense features, but we need to optimize the resist process.

Nanoimprint technology is placed on the ITRS 04 for the 32nm and 22nm technology node (half pitch of metal 1 layer for DRAM) competing technologies, which can also reach the throughput requirements of SEMI: EUV, DUV, X-ray and Electron projection lithography. Nanoimprint technology can be used for mainstream IC, nanoelectronics, polymer electronics, optics (wave guides, switches, lenses), data storage, biochemistry, life science (DNA), μTAS and microfluidics. However, the technology key of nanoimprint is stamp fabrication. In this paper, high resolution electron beam resist ZEP520 is used for the fabrication of 32 and 22nm nanoimprint stamp, PDMS material for nanoimprint is evaluated and the applications of nanoimprint technology using PDMS stamp for semiconductor, optoelectronics and biotechnology are presented.

Anodic aluminum oxide (AAO) mask was fabricated by a two-step aluminum anodizing process. Highly ordered through-holes porous anodic alumina film was obtained by oxidation of aluminum in the solution of oxalic or sulfuric acid, that were used as electrolytes. AAO mask possess hexagonally ordered porous structures with narrow size distributions of pore diameters and inter-pore space, we can control the dimensions of the AAO structure such as pore diameter, pore length, and pore density by changing the procedures and conditions of the fabrication process. In this paper, we change the etching condition, such as different kinds of etching solution, concentration of etching solution, and etching time. We hope to find out the adequate conditions to get a suitable pore size of AAO mask for different requirement. AAO mask offers a cheaper and easier method to apply to a large area and highly ordered nanostructure, such as nano-dot arrays, and nano-wire arrays with high aspect ratio, which is quite difficult to be formed by using electron beam lithography and track etching technique.

The character projection (CP) is utilized for maskless lithography and is a potential for the future photomask manufacture because the CP can project ICs faster than the point beam projection and the variable-shaped beam (VSB) projection. The drawback of the CP is its lower throughput than that of photomask-based lithography and the amortization cost of CP equipment leads to the price rise of ICs. This paper discusses a CP mask development methodology for increasing the throughput of MCC systems. The proposed methodology virtually increases the number of the logic cells which are projected with the CP. In the proposed methodology, the multiform CP masks are utilized among the column-cells for reducing the VSB projection. The experimental results show that the proposed CP mask development methodology reduced 71.3% of the number of EB shots needed for an SCC system. It also reduced 42.6% of the number of EB shots needed for the MCC system in which uniform CP masks are utilized for all column-cells.