The 1999 International Technology Roadmap for Semiconductors describes the critical measurement challenges for all areas of wafer processing in the Metrology Roadmap. The roadmap indicates that the research and development community must advance microscopy, especially scanning electron microscopy, in the near term and simultaneously develop alternate technology for IC generations with sub 100 nm feature sizes. In this paper, the issues such as loss of depth of focus that are facing CD-SEM are described. In addition, some of key challenges for overlay are briefly mentioned.

Electrical test structures of the type known as cross-bridge resistors have been patterned in (100) epitaxial silicon material that was grown on bonded and etched-back silicon-on- insulator (BESOI) substrates. The critical dimensions (CDs) of a selection of their reference segments have been measured electrically and by lattice-plane counting and they have been inspected by scanning-electron microscopy (SEM) cross-section imaging. The lattice-plane counting is performed on phase- contrast images made by high-resolution transmission-electron microscopy (HRTEM). The reference-segment features were aligned with <110> directions in the BESOI surface material. They were defined by a silicon micro-machining process which results in their sidewalls being nearly atomically planar and smooth and inclined at 54.737 degree(s) to the surface (100) plane of the substrate. This (100) implementation may usefully complement the attributes of the previously reported vertical-sidewall implementation for selected reference-material applications. The HRTEM, and electrical CD (ECD) linewidth measurements that are made on BESOI features of various drawn dimensions on the same substrate are being investigated to determine the feasibility of a CD traceability path that combines the low cost, robustness, and repeatability of the ECD technique and the absolute measurement of the HRTEM lattice-plane counting technique. Other novel aspects of the (100) Silicon-On- Insulator (SOI) implementation that are reported here are the ECD test-structure architecture and the making of HRTEM lattice-plane counts from both cross-sectional, as well as top-down, imaging of the reference features. This paper describes the design details and the fabrication of the cross- bridge resistor test structure. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross sections of the cross- bridge resistors's reference segments, as a prelude to making them available for dimensional reference applications.

The effect of the instrument on the measurement must be known in order to generate an accurate linewidth measurement. Although instrument models exist for a variety of techniques, how does one assess the accuracy of these models? Intercomparisons between techniques which rely upon fundamentally different measurement physics can play an important role in model verification. We report here such an intercomparison. The average linewidth of a test pattern on a BESOI (Bonded and Etched-back Silicon on Insulator) sample, which is single crystal silicon with a buried insulating oxide, was measured using scanning electron microscopy (SEM) and electrical critical dimension (ECD) techniques. The higher conductivity of the BESOI sample compared to a previously measured SIMOX (another silicon on insulator technology) sample reduced the ECD uncertainty. Unexpected features in the SEM image were fit by modeling the cross sectional geometry of the line as a skewed trapezoid with deviations of a few tenths of a degree from the expected 90 degree angles. The SEM and ECD results differed by 0.67% of the electrical tap spacing, a nominal difference of 55 nm. This is larger than can be accounted for by known sources of measurement uncertainty.

193 nm lithography is expected today to be an emerging solution for the development and the production of future integrated circuits based on sub 150 nm design rules. However the characterization and the evaluation of these tools require a lot of effort due to the 193 nm resist behavior during SEM observations. This paper presents the process flow chart to allow the evaluation of a ASM-L 5500/900 193 nm scanner by electrical measurement and the stack used for this study. After the validation of this flow chart, this work gives an overview of the ASM-L 5500/900 performances.

The Advanced Metrology Advisory Group (AMAG) comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). (Allgair, et al., 1998) This paper describes the results of an effort to benchmark six CD-SEM instruments according to this specification. The consensus among the AMAG metrologists was that many critical areas of performance of CD-SEMs required improvement. Following this assessment this specification for benchmarking was developed. The advanced CD-SEM specification addresses several critical areas for improvement, each with its own a separate section. The critical areas covered are: precision, accuracy, charging and contamination, performance matching, pattern recognition and stage navigation accuracy, throughput, and instrumentation outputs. Each section of the specification contains a concise definition of the respective performance parameter, and wherever appropriate refers to ISO definitions. The test methodology is described, complete with the relevant statistical analysis. Many parameters (including precision, matching, and magnification accuracy) are numerically specified to be consistent with the International Technology Roadmap for Semiconductors (ITRS, 1999). Other parameters, such as charging and linewidth accuracy, are targeted with guidelines for improvement. The test wafers developed for determining the level of compliance with the specification are also discussed. The AMAG circulated this report among the metrology instrument suppliers and conferred with them. Certain components of the specification have already been adopted by some of the manufacturers in their newer metrology instruments. International SEMATECH fabricated the AMAG test wafers described herein. Measurements on six state-of-the-art metrology instruments using the AMAG test wafers have been carried out and the results were processed according to this specification. A review of the results is presented in this paper.

On-line instrument testing can be employed by the analysis of sharpness using either the commercial product SEM Monitor or the public domain method referred to as kurtosis analysis. Both of these software programs require an appropriate sample artifact for the analysis. This paper discusses NIST Reference Material (RM) 8091 and its application to these programs. RM 8091 is intended primarily for use in checking the sharpness performance of scanning electron microscopes. It is composed of a granular tungsten layer deposited on a silicon wafer. The procedure for fabrication is provided if the user wishes to manufacture a full-wafer standard. This reference material is fully compatible with state-of-the-art integrated circuit technology. Optimization parameters and some data on the use of sharpness analysis in the semiconductor fab will be included in the presentation.

The performance of scanning electron beam instruments such as CD-SEMs can be defined in terms of parameters such as the beam probe size, the spatial resolution, and the signal to noise ratio of the image. A knowledge of these quantities is important in verifying the fact that an instrument meets its specification, and subsequently for tracking and optimizing its performance during use. Analytical methods based on the power spectrum (2-D Fourier transform analysis) of images are now beginning to be used for these purposes but care must be exercised to ensure reliable and meaningful results. Two new methods are suggested which can offer more detailed information about the microscope performance while avoiding the pitfalls of the simpler technique. Code implementing these tests, written as a plug-in macro for the well known NIH Image program, is available on-line.

Metrology will remain a principal enabler for the development and manufacture of future generations of semiconductor devices. With the potential of 130 nm and 100 nm linewidths and high aspect ratio structures, the scanning electron microscope (SEM) remains an important metrology tool. This instrument is also extensively used in many phases of semiconductor manufacturing throughout the world. A challenge was recently posed in an article in Semiconductor International. That challenge was to have an accurate, production level, linewidth standard for critical dimension scanning electron microscopes available to the semiconductor industry. The potential for meeting this challenge is explored in this paper.

Production fads currently rely on CD-SEM metrology for linewidth control in lithography and etch. The quality of the measurement data is therefore directly tied to the quality of the SEM imaging and that of the electron beam. Experience has shown that even within a 12 hour period, the beam alignment can drift sufficiently to cause a shift of several nanometers in the measured CD. Furthermore, the alignment of the electron beam has traditionally been performed manually, with the quality of the SEM image then being dependent on the judgement of the operator. While this has been adequate in the past, the drive towards ever smaller geometries means that even slight changes in the beam spot can lead to unacceptable variation in the CD measurements. In this paper, we will describe how a more consistent electron beam can be achieved by obtaining quantitative feedback on its sharpness and eccentricity. Using this quantitative information removes the subjective nature of the manual beam alignment and requires less training on part of the users. Furthermore, this procedure results in beam conditions that are at least as good as the alignment performed by an experienced operator, and in fact generally improves the alignment when compared to that obtained by subjective judgement of the image quality. Once a baseline is established, SPC charts for the sharpness and eccentricity values can be used to track tool performance. If either value falls out of a specified range, the system can be flagged as having a problem and efforts to restore the image resolution can begin immediately, reducing the risk of erroneous measurements and thus preventing lots from being misprocessed or mistakenly reworked.

Tool matching is an important metric for in-line semiconductor metrology systems. The ability to obtain the same measurement results on two or more systems allows a semiconductor fabrication facility (fab) to deploy product in an efficient manner improving overall equipment efficiency (OEE). Many parameters on the critical dimension scanning electron microscopes (CDSEMs) can affect the long-term precision component to the tool-matching metric. One such class of parameters is related to the electron beam column stability. The alignment and condition of the gun and apertures, as well as astigmatism correction, have all been found to affect the overall measurements of the CDSEM. These effects are now becoming dominant factors in sub-3nm tool-matching criteria. This paper discusses the methodologies of column parameter monitoring and actions and controls for improving overall stability. Results have shown that column instabilities caused by contamination, gun fluctuations, component failures, detector efficiency, and external issues can be identified through parameter monitoring. The Applied Materials (AMAT) 7830 Series CDSEMs evaluated at IBM's Burlington, Vermont manufacturing facility have demonstrated 5 nm tool matching across 11 systems, which has resulted in non-dedicated product deployment and has significantly reduced cost of ownership.

Phase Profilometry (PP) has been proposed for in-situ/in-line critical dimension and profile measurements. This is usually accomplished by using rigorous electromagnetic theory to simulate the optical responses of gratings with different profiles, and by using spectroscopic ellipsometry/reflectometry to measure 1-D gratings. In this paper, phase profilometry is applied to the lithography process for cross-sectional profile extraction metrology. A focus-exposure experiment was conducted using Sematech's 193 nm lithography tool. Comparison between the measurements from CD-SEM, CD-AFM and PP are discussed and explained.

The continuing demand for higher frequency microprocessors and larger memory arrays has led to decreasing device dimensions and smaller process control windows. Decreasing process control windows have created a need for higher precision metrology to maintain an acceptable precision to tolerance ratio with a reasonable sampling rate. In order to determine and reduce across chip, across wafer, and across lot linewidth variations, higher sampling is required which, in turn, demands faster move acquire measure (MAM) times to maintain throughput. Finally, the need to detect and quantify sidewall angle changes in addition to CD measurements is becoming critical. Spectroscopic Scatterometry is a metrology technique which offers the potential to meet these requirements. This work explores some of the fundamental technology concerns for implementing scatterometry in a manufacturing environment. These concerns include mark requirements and characterization necessary for library generation. Comparison of scatterometry data to in-line CD SEM, x-section SEM, and AFM results will be presented.

Scatterometry, an optical metrology based on the principle of diffraction, has received a considerable amount of attention in the literature in the past decade. By measuring and analyzing the light scattered, or diffracted, from a patterned periodic sample, the dimensions of the sample itself can be measured. Applications of the technique have included the characterization of photomasks, the monitoring of focus, dose and the post exposure bake process, and even the characterization of three-dimensional features such as contact hole and DRAM arrays. Like other optical metrologies, scatterometry measurements are rapid, non-destructive and highly repeatable. The most widely reported scatterometry data have been for measurements of developed photoresist and etched poly-Si gratings. Although these types of features represent a considerable portion of a typical process, other types of materials, such as metal layers, are also commonly present, and are important to characterize. In this work scatterometry measurement data from metal layers will be presented. The scatterometer used in this investigation was the well-known 2- (Theta) variety, where the scatter signature is obtained by measuring the diffraction efficiency of a particular order as the incident angle is varied. The analysis involved comparing the measured data to a library of theoretical scatter signatures (generated a priori from rigorous coupled wave theory) to find the best match. The measurements were performed at two process steps: pre-etch, where the patterned features were resist gratings on uniform metal layers, and post-etch/strip, where the patterned features were etched metal gratings. The composition of the metal stack starts with a silicon substrate, upon which is deposited 3000 A of oxide, followed by 500 A of Ti, 6000 A of AlCu and 250 A of TiN. A BARC layer and then the photoresist were deposited on this stack for patterning. The nominal patterned dimensions were 350 nm lines in 800 nm pitch gratings. Overall the sample set for this study included some 24 wafers with various AlCu layer thicknesses, providing a broad wafer split for analysis. Measurement results for linewidth and the various layer thicknesses will be presented, and comparisons to AFM measurements will be made. Results from assessing the repeatability of the 2-(Theta) scatterometer will also be presented, and indicate sub-nanometer precision (6-(sigma) ) for linewidth measurements. In addition, the practical aspects of the method, such as the modeling time required to generate the signature library as well as measurement speed and throughput will be presented.

Optical diffraction is an attractive process with which to non-invasively examine materials and structures. Waves diffracted by a periodic structure carry information about geometrical characteristics of the diffracting structure as well as intrinsic properties of the material comprising the structure. These features make optical diffraction from surface relief gratings appealing as a monitor for lithographic processes. Considering that lithographic processes are usually quite stringently controlled, a search for 'departures' from a set of expected design values can linearize the highly non-linear relationship between parameter values and diffraction measurements, and hence permits analyses using classical linear methods. We therefore propose a linear inversion technique to determine key parameters of a periodic structure from an analysis of diffraction data that seeks to determine the departures from a set of expected design values. The approach is validated for the retrieval of three geometrical parameters (groove depth, line width, and sidewall angle) based on simulations performed using the rigorous coupled-wave theory (RCWT). The results obtained are very encouraging and highlight the potential of a linear inversion technique in scatterometry.

This paper is the third of a series that defines a new approach to in-line lithography control. The first paper described the use of optically measurable line-shortening targets to enhance signal-to-noise and reduce measurement time. The second described the dual-tone optical critical dimension (OCD) measurement and analysis necessary to distinguish dose and defocus. Here we describe the marriage of dual-tone OCD to SEM-CD metrology that comprises what we call 'process window metrology' (PWM), the means to locate each measured site in dose and focus space relative to the allowed process window. PWM provides in-line process tracking and control essential to the successful implementation of low-k lithography.

We discuss the incentive and design outlines for a reticle that is used for assessing across-chip linewidth variation (ACLV). For printing features whose dimensions are near half of the exposure wavelength ((lambda) ), the ACLV Solver reticle can be used to diagnose the contributing factors that cause the critical dimension (CD) to vary out of control. For example, mask error factor (MEF) and mask pattern density loading have both been shown to have a significant impact on ACLV. The focus of this paper is the ACLV design methodology, along with a couple of proposed designs of experiment (DOE). Conclusions and future work are discussed.

In this paper we describe the process control and optimization strategy for a conventional metal process for 0.18-micrometer technology. It is well known that the interaction of DUV resists with substrates containing nitrogen, e.g. TiN, leads to resist footing. A technique to minimize this interaction and improve CD control will be presented. We then present process optimization strategies including substrate optimization, resist thickness optimization, and use of top- anti-reflective coating. A comparison of reflectivity simulations with CD control will also be shown. DOF with varying substrate thicknesses will be presented. Strategies for CD control in sub-0.18 micrometer metal patterning will also be presented.

In this paper, we present experimental results with a prototype design of a 'MEEF Meter,' and investigate its sensitivity to defocus and exposure changes. We find that the results of the MEEF meter complement the results obtained through conventional CD metrology, with conventional CDs being a good indicator of exposure changes, while the MEEF meter is a good indicator of defocus changes. We also investigate two kinds of MEEF meter, a dense MEEF meter and 'Process' MEEF meter design, and find the results for MEEF similar, but that the 'Process' MEEF meter design is far more susceptible to noise and bridging.

The pattern size variation (PSV) and pattern size deviation (PSD) dependency on inter-metal dielectrics (IMD) thickness is studied to improve overlay performance. A new model is introduced to explain the cause of such a large PSD and PSV(> 1 micrometer), which are frequently encountered in real process followed by chemical mechanical polishing (CMP) process. Abnormal PSD depends more on focus and substrate structure than on dose. The IMD as thick as 4 micrometer gives rise to a large PSD by 1 micrometer for a 3 micrometer overlay mark. To solve such large PSD and PSV, two solutions are suggested: application of anti-reflective layer (ARL) beneath the IMD or placement of a reflective layer in the middle of IMD. With this improvement, the failure rate of the overlay mark detection decreased from approximately 90% to less than approximately 2%.

Traditionally a single CD width parameter is expressed in a metrology measurement of an amplitude modulated waveform. The measurement is the result of a single and specific edge detection algorithm applied to the waveform. There is no distinction between scale and shape (profile). Feedback and feedforward use of metrology information requires such a distinction as well as some sense of how far to trust the data in making process decisions. Typical metrology waveforms are obtained from optical imaging (overlay, mask, end of line truncation), scanning mechanical probe, optical diffraction, ellipsometry and SEM tools. This system we describe separately determines shape and scale of linewidth metrology by combining an entire range of edge detection parameters in the space domain. It specifically is used to monitor scale and shape changes from a basic template derived from the process margin. It can also be used to determine what portion of the linewidth or profile has deviated from the template in a diagnostic sense. The method repeatedly measures all possible features from the 1D or 2D waveforms stored in memory. Derived values of characteristic features are determined from the string of data obtained from the edge detection parameters. (sidewall width and angle, footing, topping, space features, 2D roughness, inflection positions) First the data is analyzed to confirm that it is valid and supports the requirements of the technology and level. Only valid data of rated quality is utilized. The system output is a group of three values. Scale (nm), Quality Index (0-1), Descriptive Bin (Deviation of shape and scale denoted A-Z). The Quality Index is a weighted consideration of template deviation (Both shape and measure error). i.e. CD feature equals 0.23 micrometer, 0.67, F (footing) This paper describes our attempts to find ways of extracting the information needed to monitor the pattern transfer process from CD SEM waveforms. The basic idea however applies to all metrology waveforms that approximate the topographical contours of a feature. Multiple Parameter Characterization (MPC) in the space and frequency domain as well as whole, partial and derivative waveform correlation are the basic tools utilized for quality and shape determination. The core principle is that different physical features are more strongly expressed in different parts of the SEM intensity traces. Some of these physical features are more predictive of how the pattern transfer occurs than others. Modern linewidth metrology systems require that the distinction be made between scale and shape. Automated inspection systems require that this be carried out quickly and robustly for it to have any production impact. Metrologists have always made such distinctions in evaluating features by utilizing all manner of direct and indirect observation of the monitored process. Unfortunately the abilities of the metrologist are not yet available as a supported automated system running 24 X 7.

Currently, most production fabs use critical dimension (CD) measurements as their primary means for process control in printing lines, spaces and contacts. Historically, this has been adequate to control the lithography and etch processes and produce reasonable yields. However, as the industry moves from 0.25 micrometer manufacturing to 0.18 micrometer and beyond, it is becoming increasingly obvious that CD measurements alone do not provide enough information about the printed structures. As the geometry shrinks, slight changes in the shape and profile can significantly affect the electrical characteristics of the circuit while maintaining the same CD value. In this paper, we will describe a method which, in conjunction with the CD measurements, better characterizes the circuit structures and therefore provides valuable feedback about the process. This method compares stored image and linescan information of a 'golden' (correctly processed) structure to that of the structure being measured. Based on the collected data, it is possible to distinguish between different profiles and determine if a process shift has occurred, even when the measured CD remains within specification. The correlation score therefore provides an additional constraint that better defines the true process window and provides an additional flag for process problems. Without this information, the process used may not be truly optimized, or a shift may occur that is not detected in a timely manner, resulting in the loss of yield and revenue. This data collection has been implemented in production on a local interconnect lithography process. Before the correlation information was available, it was very difficult to detect the scumming within the LI trench, in which it was a time consuming and labor intensive procedure to identify problem lots. The correlation scores, collected automatically and concurrently with the CD measurement, allowed tracking through the SPC chart and the automatic flagging of problems while the lot was still in the photolithography module. The result has been faster feedback control and thus less scrap material.

Rapidly accelerating technology roadmaps have put increased pressure on in-line process control. CDs measured by automated SEMs are a common element of in-line process control. However, CD measurements alone may not be enough in all cases for adequate process control. For instance, degradation of feature integrity that does not lead to out of control CDs in photo can lead to scrap after etch. The cost of scrap and loss of time to results associated with catching photo process drift with after etch inspection has forced the development of new tools to monitor feature integrity in the ADI CD inspection module. Likewise, partially closed vias that are not caught with etch CD inspection can have a negative impact on copper processes. We describe a feature integrity monitoring technique using an automated CD-SEM that occurs simultaneously with the CD measurement to monitor and detect process drift prior to out of control CD events. We further describe the implementation of this technique in a production environment.

As gate widths shrink below 0.18 micrometer, the SPC (Statistical Process Control) based CD (Critical Dimension) control in lithography process becomes more difficult. Increasing requirements of a shrinking process window have called on the need for advanced CD control using a closed-loop feedback mechanism. This concept has been gaining momentum and shows promising advantages in shortening the time of feedback control. However, the current closed-loop feedback links only the average CD of a lot and the exposure dose (E), leaving out another critical lithography parameter -- stepper, or scanner, defocus (F). Up until now, F has been assumed constant while E has been shown to have one-to-one correlation with CD. Such an assumption is justified for feature sizes larger than 0.25 micrometer with a usable DOF (Depth Of Focus) of more than 1 micrometer. For 0.25 micrometer and below technologies, stepper defocus induces rapid feature profile, as well as CD, changes. Therefore, one parameter (exposure dose versus CD) feedback is not adequate enough to control CD in photolithography and a two-parameter (exposure dose and stepper defocus versus CD) feedback is needed. For stepper defocus variation, resist feature shape needs to be monitored in-line. We will present an innovative way of shape monitoring through sidewall imaging. The scanning beam is bent up to 5 degrees, so that a feature can be viewed from a tilted angle. Such tilted view greatly enhances edge resolution. Shape monitoring applications based on sidewall imaging will be presented. With both CD and shape are monitored in photolithography process, two critical parameters, i.e., exposure dose and defocus, can be easily controlled. Such shape control mechanism provides the base for two-parameter feedback loop.

The charging of the workpiece in electron beam direct writing processes has been identified as a problem that disturbs the electron beam and causes pattern displacement error. In this paper the electron beam deflection caused by surface charging is evaluated by the SIMION and MATHEMATICA simulation programs. Isolated charged patterns of different geometry are simulated as electrodes with given potentials in SIMION to calculate the extent of beam deflection, while secondary electron emission yield and beam dosage are assigned in MATHEMATICA programming for determination of surface potential and spatial field, from which the beam deflection is then calculated. The simulation results are in good agreement with each other and they are compared with values available in literature. The initial charge content along with the pattern dimensions chosen in simulation are found to be the major factors that determine the extent of beam deflection. The limitation of SIMION simulation on the beam deflection is also discussed.

As integrated circuit fabrication processes continue to increase in complexity, it has been observed that data collection, retention, and retrieval rates are continuing to increase at an alarming rate. At future technology nodes, the time required to source manufacturing problems must at least remain constant to maintain anticipated productivity. Current commercial and manufacturer in-house data management systems (DMS) have limited functionality in their ability to access, analyze, and intelligently extract information from the large variety of manufacturing data sources available within the semiconductor manufacturing site. It is critical that the semiconductor industry agree on a strategic R&D plan to develop a family of DMS technologies to simultaneously access multiple data sources and derive useful defect and yield information from that data via analysis algorithms. The Oak Ridge National Laboratory (ORNL) and SEMATECH performed an industry-wide survey of semiconductor device manufacturers and the suppliers of data management tools and systems in the Spring of 1999. The purpose of the survey was to determine: (1) the state-of-the-art in DMS technologies and systems; (2) limitations of the systems in use today; (3) technology gaps impacting future DMS development, and; (4) input for future strategic R&D activities. This paper describes the results of this survey and presents a prioritized R&D roadmap.

This paper summarizes the work completed as part of the Equipment Evaluation Program (EEP) for the Applied Materials SEMVision cX at Texas Instruments' KFAB facility. This tool employs real time Automatic Defect Classification (ADC) software in conjunction with an Automatic Defect Redetection (ADR) capability. The SEMVision cX utilizes a unique imaging system that employs multiple detectors to create several perspectives of the defect image. These perspectives enhance certain features of the defect that facilitate Automatic Defect Redetection of all defect types, and enable a rule- based ADC system. This tool was designed to meet the requirements of an advanced CMOS fab, which requires increased imaging resolution to resolve the ever-smaller defects that can cause yield loss. This evaluation program was begun to accomplish three objectives: (1) To evaluate the tool for automatic defect classification on advanced CMOS technology. (2) To increase speed/throughput/resolution of defect review. (3) To increase the accuracy of defect classification with the use of ADC. Of great importance for TI's advanced wafer fabs is the need for a defect review SEM that also has the capability of ADC to improve defect classification accuracy and also to improve queue time in the Yield Enhancement (YE) operations. In addition to this, the need to be fully integrated into the fab DMS (Defect Management System) and TI's Automation system is crucial for automating many routine functions for the YE group. With the YE group personnel freed from the many tedious data management tasks, they can work on yield issues in real-time. The SEMVision cX differs from usual fab SEM's in that it employs MPSI^TM (Multiple Perspective Imaging) which is three detectors, one at normal incidence to the wafer and two on either side of normal from the electron beam. This configuration of detectors gives added information to the ADC system, provides for robust redetection, and establishes a paradigm for automatic defect classification based on topography and material perspectives. The SEMVision cX met all of the requirements during the evaluation with the exception of the tilt and rotate capabilities. There were two areas that were involved in this evaluation, one was for the defect review SEM itself and the other was for Automatic Defect Classification (ADC). Also included in this evaluation was the integration of the SEMVision cX into TI's DMS (Defect Management System) and Automation networks.

The automatic classification of defects found on semiconductor wafers using a scanning electron microscope (SEM) is a complex task that involves many steps. The process includes re- detecting the defect, measuring attributes of the defect, and automatically assigning a classification. In many cases, especially during product ramp-up, and when multiple products are manufactured in the same line, there are few training examples for an automatic defect classification (ADC) system. This condition presents a problem for traditional supervised parametric and nonparametric learning techniques. In this paper we investigate the attributes of several approaches to ADC and compare their performance under a variety of available training data scenarios. We have selected to characterize the attributes and performance of a traditional K-nearest neighbor classifier, probabilistic neural network (PNN), and rule-based classifier in the context of SEM ADC. The PNN classifier is a nonparametric supervised classifier that is built around a radial basis function (RBF) neural network architecture. A basic summary of the PNN will be presented along with the generic strengths and weakness described in the literature and observed with actual semiconductor defect data. The PNN classifier is able to manage conditions such as non-convex class distributions and single class multiple clusters in feature space. A rule-based classifier producing built-in core classes provided by the Applied Materials SEMVision tool will be characterized in the context of both few examples and no examples. An extensive set of fab generated data is used to characterize the performance of these ADC approaches. Typical data sets contain from 30 to greater than 200. The number of classes in the data set range from 4 to more than 12. The conclusions reached from this analysis indicate that the strengths of each method are evident under specific conditions that are related to different stages within the VLSI yield curve, and to the number of different products in the line.

Process induced defects in sub-0.15 micrometer devices patterned on 193-nm photoresists have been studied and related to the physical and rheological properties of these polymers, as well as to the interaction of the photoresists with the two principal track-related unit operations: spin-coating and development. Studies on unpatterned wafers with these photoresists were conducted to elucidate the dependence of defectivity and defect types on spin coating parameters. Imaging was done on a full-field ASML 193 nm scanner and the resist processing was performed on a TEL MARK-8 track. Defect inspection was performed with a KLA 2132, KLA SP1 bright field inspection systems, and defect review was carried out with JEOL 7515 SEM tool. Results indicate that defectivity of an optimized 193-nm resist process is comparable to a well- optimized 248-nm baseline resist process. It was found that 193-nm resists suffer from the same residue problems as those of 248-nm. Yield data obtained on 193-nm and 248-nm resists processed under optimized conditions demonstrate that the 193- nm resist process is capable performance comparable to that of a baseline 248-nm resist process.

The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N₂) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan III^TM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface particle/residual contamination, (2) wafer flatness, and (3) control of contaminant materials such as copper (Cu). Data associated with the SpCE process, optimized for flatness improvement, particle removal, and Cu contamination control is presented in this paper, as it relates to excessive consumption of the usable depth of focus (UDOF) and comprehensive yield enhancement in photolithography. Additionally, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm - 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ SpCE clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality.

Defect monitoring is increasingly required for advanced line maintenance. A critical decision is how to proceed with lot deposition if an excursion is detected. A methodology based on defect inspection and defective die count analysis was employed which provided effective process monitoring and yield maintenance. The methodology allows rapid decision-making with a minimum of information for lot disposition. The purpose is to separate significant excursions from temporary fluctuations in order to appropriately focus defect reduction resources. Wafers are systematically inspected post-litho with a patterned wafer inspection system, the WF736, and the number of die with killer defects is counted and then monitored with time. Every lot is inspected, full wafer inspection is performed, and all defect types are captured. By determining the killer defect progression after re-work, it is possible to establish lot disposition. If the count is still high, defect reduction analysis is then applied. Various defects were flagged and addressed, arising both from litho and from prior steps. In addition, the wafer inspection was utilized for dose forecasting with a feed-forward to appropriately modify the optimal dose. Good line control and yield maintenance were observed.

Scan speed, defect capture, false and nuisance rate are just some of the important metrics used in evaluation inspection methodologies. With newer methodologies such as SEM-based inspection, it is difficult to find samples suitable to study these parameters as the nature of some of the defects in the sample cannot be characterized by other methods. It is for this reason that specific defects were designed and placed on a reticle set in both the array and the random logic areas of the device layout. At different layers, knowing exactly the number and placement of these 'intentional defects' allowed the assessment of scan speed, defect capture, false and nuisance rate at various process levels. This method provided a means of evaluating the inspection methodology as well as optimizing recipes to find the best capture rate at the optimum scan speeds.

Optical lithography is pushed more to extend to sub-wavelength region for very low k1 patterning processes; in which, alternating PSM is the solution for isolated patterns, without changing the wavelength of exposure tools' light source. With this prospect, the critical issues such as design layout complexity, light intensity imbalance between shifted and unshifted space area, and phase defect controllability have recently been studied in order to apply alternating PSM for device mass production. In this paper, we studied to find out the maximum non-printable phase defects for 130 nm and 100 nm lines by printing the wafer using a KrF DUV scanner. With the limitations of the mask making process for very small programmed defects, we made the masks with duty ratio around 1:3. After we verified the resist simulation for our test pattern by wafer printing results, printable defects for denser pattern were predicted. In addition to defect printability study, the mechanical repair tool for phase bump defects was tested using 248 nm AIMS, AFM, and CD SEM metrology as well as wafer printing. Electromagnetic Field 3 dimension simulation was also compared with commercialized 2D simulation tool for phase defect printability.

The reduction of the CD budget is one of the key challenges of current and future semiconductor manufacturing technologies. There are many sources of CD dispersion, one of these is reticle errors, usually split into components such as linearity, uniformity across the field and mean to target offset. Reticle repairs are now emerging as another critical aspect to be added to the list of Mask Error Factors (MEF). As critical dimensions shrink down to 0.18 micrometer, 0.15 micrometer and even below, it becomes more and more difficult to build a defect free reticle right away. The frequency of reticle repairs increases with the technology complexity. It is therefore a necessity to fully characterize these defects. While repairs impact is sometimes evaluated by simulation, characterization on wafers is a lot scarcer. The purpose of this study was to link the observations made on repairs during the reticle inspection with their impact in terms of CD and process window on wafer. Reticle repairs have been characterized on various production reticles, using KLA STARlight SL300 (488 nm) and AIMS (248 nm) when available. The printability of these reticle repairs has then been studied on wafer. The impact on patterns close to the repair has also been measured. Patterns studied include contacts-holes and lines, on 0.18, 0.25 and 0.35 micrometer technologies. Exposure tools are ASML 248 nm DUV Steppers (/300) and Step-&- Scan (/500). A CD characterization method has been defined and different repair tools have been compared.

As I-line and deep ultraviolet (DUV) photolithography processes grow more complex, yield improvement has become more challenging and critical. Historically, expensive and time consuming monitoring of product wafers themselves has been used to monitor the health of photolithography processes and equipment. In addition, the sensitivity of the inspection scans on product wafers is usually not sufficient due to the vast amount of noise generated by underlying pattern or structures. With the advent of smaller sub-micron geometries using newer chemically amplified photoresists, a high sensitivity, easy to review and trouble-shoot monitor is essential. In order to fully understand what defects may be generated by a process or process tool, it is necessary to fully duplicate the given process on the test wafer or procedure used to monitor the defect level. That concept is called Process Induced Defects Per Wafer Pass (PIDPWP). PIDPWP requires the real and exact product process to be used in creating the defect test monitor. To monitor a photolithography process using the concept of PIDPWP, typically a coat, expose, and develop sequence is used with a selected and simplified mask, such as a diffraction grating. The role that the pattern chosen for the Photo Track Monitor (PTM) was examined. Typical structures such as diffraction grating (equal lines/spaces), contact arrays, clear and resist areas, and typical product patterns were evaluated for the types of defects that they can detect and monitor. Certain types of defects were more clearly observed depending on the structure of the pattern and the nature of the defect mechanism. Simultaneous printing of various structures on the same PTM reticle may not be allowed due to limits of the photo process, so care must be used in choosing which structures to include on the same reticle. Other factors examined included the pattern inspection by trained technicians performing the role of classification and troubleshooting when a tool goes out of control. While the inspection tools were extremely sensitive regardless of the pattern density, the defect must still be examined so that the technician can determine if the defect was of concern or not. Such factors as the resolution capability of the review optics and review SEM on the choice of the PTM reticle were examined. The results showed that no one pattern was optimal for a PTM reticle, and may require multiple fields or multiple PTM reticles to successfully monitor the photolithography process without scanning product wafers.

As photomask critical dimensions extend well into the submicron range, optical measurement techniques are approaching the end of their useful life. While offering advantages of being nondestructive, relatively fast, and very precise, optical measurement tools may have accuracy problems due to diffraction. Linearity between measured and actual values is typically lost due to interference, resonance, and shadowing effects even before the diffraction limit is reached. In addition, standards for submicron features do not exist for optical tools. These limitations have given rise to using a Scanning Electron Microscope (SEM) for reticle dimension measurement. Another complication is that no NIST standard exists for chromium photomask dimensions. A CD SEM must therefore be calibrated to some other trusted standard or measurement method. A Stylus NanoProfilometer (SNP) has better inherent resolution than a SEM and was chosen as the standard measurement instrument for both CD SEM and optical tool metrology. This paper describes the cross-calibration of the Leica LWM-250 (white light) optical metrology tool and the KLA-Tencor 8100XP-R CD SEM, with reference to a Surface Interface SNP9000. The primary motivation was to define the usable ranges of both SEM and optical CD measurement systems, allowing for flexible implementation into a photomask manufacturing environment.

CD AFM (Critical Dimension Atomic Force Microscopy) offers a potential advantage in mask metrology not found in more common techniques: sidewall profiling. The uncertainty of CD width measurement can be reduced because the sidewall positions are found directly, instead of relying on an interpretation of brightness as with other methods. And, unlike with the other techniques, a thickness measurement is available. To demonstrate that this potential could be realized in a production environment, a real CD AFM tool was used to run CD long-term precision measurements on etched masks. Results indicate that a precision in width measurements of 3 nm at 3(sigma) can be achieved. Preliminary results for resist masks indicate that a similar performance is possible. Masks, as opposed to wafers, present additional complications for CD AFM. These problems and their solutions are discussed. Calibration techniques are also presented, as they are a crucial concern in metrology.

Atomic force microscopes (AFMs) generate three dimensional images with nanometer level resolution and, consequently, are used in the semiconductor industry as tools for sub-micrometer dimensional metrology. Measurements commonly performed with AFMs are feature spacing (pitch), feature height (or depth), feature width (critical dimension), and surface roughness. To perform accurate measurements, the scales of an AFM must be calibrated. We have designed and developed the calibrated AFM (C-AFM) to calibrate physical standards for other AFMs. The C- AFM has displacement metrology for all three axes traceable to the 633 nm wavelength of the Iodine-stabilized He-Ne laser. This is accomplished through the integration of a flexure x-y translation stage, heterodyne laser interferometers, and a z- axis piezoelectric actuator with an integrated capacitance sensor. This capacitance sensor is calibrated with a third interferometer. We have performed both pitch and height measurements for external customers. Recently, we performed pitch measurements on holographic gratings as part of an ongoing international comparison driven by BIPM (Bureau International des Poids et Measures). We have also completed a preliminary design of a prototype pitch/height standard and are evaluating preliminary test samples. Additionally, we are working toward the development of linewidth standards through the comparison of C-AFM width measurements with values obtained from other methods. Our step height and linewidth measurements are in good agreement with those obtained by other methods, and we are working to improve the lateral resolution and hence the uncertainty of our probe-based linewidth measurements by studying the use of nanotubes and other types of sharp tips as linewidth probes.

A mapping reflectometer has been integrated into the load robotics of a multi-chamber, thin film deposition tool. Normal incidence reflectance metrology is used to monitor PE-CVD silicon oxynitride films. Reflectance data is modeled to obtain film thickness and extrapolate refractive index and extinction coefficient at DUV wavelengths using an interpolation dispersion model. The interpolation model is an empirical, process specific dispersion model that uses one or two adjustable parameters to interpolate between well- characterized 'node' films. The node film dispersions are characterized by multiple-angle spectroscopic ellipsometry over the spectral range of 200 nm to 800 nm. The model parameters are correlated to process variables which affect the index of the deposited oxynitride film directly such as the SiH₄:N₂O flow ratio and the total flow. The capabilities of the instrument are demonstrated by measuring a 5-layer, ILD stack for a dual damascene/copper process.

Spectroscopic ellipsometry is one of the more important tools for thin film metrology. It is now intensively used in microelectronics and especially for the microlithographic applications. Instrumentation for the next generation of UV lithography at 157 nm requires special optical setup since oxygen and water are extremely absorbing below 190 nm. The ellipsometer discussed in this paper works into a purged glove box to reduce the oxygen and water contamination in the part per million range. The optical setup has been especially studied for microlithographic applications with a premonochromator in the polarizer arm to avoid resist photobleaching. Technical details of the system and measurements results on substrates and thin films are reported hereafter. Results are compared to those obtained with more standard ellipsometers and correlated to other results obtained with grazing x-ray reflectance technique.

As device feature sizes shrink below 0.18 micrometer, shorter wavelength exposure tools are being investigated to meet the requirements for higher resolution. Understanding the optical properties of thin films and substrate materials at short wavelengths (193 nm, 157 nm, and shorter) will be necessary to develop the lithographic process. Variable Angle Spectroscopic Ellipsometry (VASE) offers nondestructive and precise measurement of thin film thickness and refractive index in the wavelength range from 146 nm to 1700 nm. VASE measurements provide a complete description of the thin film optical properties, which can be used to track process changes or variations in sample structure. Recent hardware innovations have extended VASE into the vacuum ultraviolet to meet lithography requirements at 157 nm.

As design rules decrease, tighter tolerances are placed on imaging and overlay. With the SIA National technical roadmap indicating that overlay control will be one of the top challenges facing lithography in the future and achieving the overlay specifications of future products will require greater dependence on accurate prediction of total overlay errors. Contributions to product registration include lens distortions and image alignment. Understanding how these errors effect measurement sampling and modeling of product registration will be key to achieving stricter overlay tolerances. This paper investigates the impact of lens distortions on the accuracy of the modeling. Initial testing is performed using a standard matching test reticle and procedure to determine the raw overlay errors. Corrections from three different measurement scenarios are applied to this data and the resulting residuals analyzed and plotted. The ability to enhance the modeling capability through optimized measurement sampling and location of measurement sites is also evaluated using a 'device feature' SEM measurement routine. The paper concludes with a simulation of feature specific distortion errors, a near future concern.

An advanced control system providing modeling and predictive data simulation for pass-fail criteria of overlay production control has been used in 0.18 micrometer Design Rule production facilities for over a year. During this period overlay was measured on both product wafers and during periodic process qualification tests. The resulting raw data is modeled using exposure tool specific and layer-focused models. Modeled results, measured process statistics and tool signatures are combined in a real-time simulation to calculate the true overlay distribution over the entire wafer and lot. All results and raw data are automatically gathered and stored in a database for on-going analysis. In this manner, tool, product technology and process performance data are gathered for every overlay process-step. The data provides valuable insights into not only tool stability but also the process- step characteristic errors that contribute to the overlay spectrum of distortions. Data gathered in this manner is very stable and can be used to predict a feed-forward correction for all correctable coefficients. The technique must take into consideration algorithm modeled coefficient variations resulting from: (1) Reticle pattern-to-alignment mark design errors. (2) Process film variations. (3) Tool-to-tool static matching. (4) Tool-to-tool dynamic matching errors which are match-residual, process or time induced. This extensive database has resulted in a method of conducting Predictive Process Control (PPC) for overlay lithography within an advanced semiconductor line. Using PPC the wafer production facility experiences: (1) Improved Yield: Lots are always exposed with optimum setup. Optimized setups reduce rework levels and therefore wafer handling. (2) Capacity Improvement: Elimination of rework tacitly improves capacity in the facility. WIP is also simplified because lots do not have to wait for a dedicated exposure tool to become available. (3) Dynamic Matching^TM: Matching of multiple exposure tools is continuously monitored by the use of the feedback loop. Tool precision can be monitored as well as the setup systematic offsets. In this manner, the need to remove an exposure tool from production for match-maintenance can be predicted and scheduled. Residual matching errors can also be removed from the production cycle. The benefits of full production lot modeling and the contributors to production errors are presented. Process and Tool interactions as well as control- factor coefficient stability indicate the level of control to be well beyond manual methods. Calculations show that these contributors are predictable, stable and are a necessary tool for competitive sub-0.2 micron production. An analysis of the overlay error sources within two facilities results in consistent facility process response and a well-defined error budget derivation. From this analysis, the control added to semiconductor overlay is shown capable of extending mix-and- match exposure tool operations in production down to 0.12 micrometer design rules.

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As design rule shrinks down, the role of CMP process is important for obtaining available depth of focus margin in optical lithography. However, the alignment mark deformed by CMP process contributes to the total overlay error budget. This study examines the effect of alignment accuracy with various CMP polishing targets in STI process and optimizes for stable overlay control in gate pattering. At first, polishing uniformity was monitored as polishing targets in STI process and results show that uniformity is getting worse as increasing polishing target. Also, the signal contrast of alignment mark becomes lower and thus, modeled alignment residual is increased. The investigations of modeled alignment residual with signal profile and overlay result as alignment mark type show that convex alignment mark is more sensitive than concave in varying a polishing target. And, the effect of Tungsten gate film stack was considered. In order to make alignment topology, oxide between alignment marks was removed by wet etching process. Then, gate film stack materials, poly, Tungsten, Nitride, oxide, were successively deposited over alignment mark. For stable overlay control, alignment mark type and the optimization of the width of segment alignment mark with concave was examined using modeled alignment residual with signal profile and overlay result. From this study, it is found that narrow width with segment alignment mark and concave type is better than normal bar alignment mark with convex type for overlay control in Tungsten gate patterning.

The impact of alignment mark structure, mark geometry, and stepper alignment optical system on mark signal contrast was investigated using computer simulation. Several sub-wavelength poly silicon recessed film stack alignment targets of advanced memory products were studied. Stimulated alignment mark signals for both dark-field and bright-field systems using the rigorous electromagnetic simulation program TEMPEST showed excellent agreement with experimental data. For a dark-field alignment system, the critical parameters affecting signal contrast were found to be mark size and mark recess depth below silicon surface. On the other hand, film stack thickness and mark recess depth below/above silicon surface are the important parameters for a bright-field alignment system. From observed simulation results optimal process parameters are determined. Based on the simulation results some signal enhancement techniques will be discussed.

As the integration density of VLSI device increases, the overlay accuracy in the photolithography becomes more and more important. In the sub-quarter micron technology, the registration budget is less than 70 nm. Registration error can be induced by the repeatability error of alignment sensor, mask fabrication error, tool induced shift, process induced shift, and so on. One of these misregistration error sources, overlay parameter difference between DI and FI, can cause significant damage to the device because, in most cases, overlay accuracy is checked only in the mask step. In this paper, we studied the relationship of the Edge Detection Algorithm (EDA) and the overlay mark structure to the wafer scale difference.

The role of process simulation in microlithography is becoming an increasingly important part of process control as wafer feature sizes become smaller than the exposure wavelength, because the pattern transfer from photomask to wafer is nonlinear. An important factor hindering the increased use of simulation applications, however, is their inclination to be standalone applications not easily integrated into the overall process. These observations have led to the concept of The Neolithography Consortium. Neolithography is a realization and acceptance that the pattern on the photomask is not replicated exactly on the wafer because of diffraction effects, subresolution mask features and imperfections, and other effects. It is characterized by the full integration of process simulation and metrology into the IC microlithography process, leading to a comprehensive and logical approach to photomask design and wafer exposure. All of the relevant optical projection, resist exposure and development, and etch parameters, and resolution enhancement techniques are optimized and incorporated into the photomask design before the first wafer is printed. The Neolithography Consortium is being formed for the purpose of accelerating the adoption of neolithography, by identifying impediments to the integration of simulation and metrology tools into the microlithography process and finding solutions to remove these impediments. It is comprised of companies who create or use commercial IC microlithography simulation software, or who supply metrology or production tools which will interface with simulation software. Any company or organization with a legitimate interest is welcome to join.

We present the results of a DARPA sponsored study on the application of Focused Ion Beam (FIB) systems to metrology in advanced lithography for production and process development. Data on top-down measurements, on the effects of FIB imaging, and on milling strategies for cross-sectional preparation are presented for fine-line resist structures. In addition, some preliminary aspects of Ga contamination are addressed in the context of the residual dose and concentration leftover from FIB processing. A standard deviation of 8 nm for the measured line width was observed, which makes FIB metrology competitive with the more established technique of CD SEM analysis.

As exposure wavelengths decrease from 248 nm to 193, 157, and even 13 nm (EUV), small process defects can cause collapse of the lithographic process window near the limits of resolution, particularly for the gate and contact structures in high- performance devices. Such sensitivity poses a challenge for lithography process module control. In this work, we show that yield loss can be caused by a combination of macro, micro, CD, and overlay defects. A defect is defined as any yield- affecting process variation. Each defect, regardless of cause, is assumed to have a specific 'kill potential.' The accuracy of the lithographic yield model can be improved by identifying those defects with the highest kill potential or, more importantly, those that pose the highest economic risk. Such economic considerations have led us to develop a simple heuristic model for understanding sampling strategies in defect metrology and for linking metrology capability to yield and profitability.

Defectivity in spin-coated, but unpatterned ultrathin resist (UTR) films (<EQ 1000 Angstrom) was studied in order to determine whether defectivity will present an issue in EUV (13.4-nm) and 157-nm lithographic technologies. These are the lithographic regimes where absorption issues mandate the use of ultrathin resists. Four resist samples formulated from the same Shipley UV6 polymer batch and having the same polymer molecular weight properties but different viscosities, were spin-coated at spin speeds ranging from 1000 to 5000 RPM on a production-grade track in a Class 1 pilot line facility. Defect inspection was carried out with KLA SP1/TBI tool, while defect review was carried out with JEOL 7515 SEM tool and KLA Ultrapointe Confocal Review Station (CRS) Microscope. The results obtained are related to the physical properties of the resist polymers, as well as to spin coating parameters. Also, the results of the defect inspection, review, characterization, and pareto are compared to those obtained on baseline thick resists (>= 3500 Angstrom) processed under similar condition as the ultra-thin resists. The results show that for a well-optimized coating process and within the thickness range explored (800 - 4200 Angstrom), there is no discernible dependence of defectivity on film thickness of the particular resists studied and on spin speed. Also assessed is the capability of the current metrology toolset for inspecting, reviewing, and classifying the various types of defects in UTR films.

The novel radioactive tracer technique was applied to investigate the migration of cesium, manganese and zinc impurities from deep ultraviolet photoresist into underlying substrate. Two important process parameters, viz., baking temperatures and substrate types (i.e., bare silicon, polysilicon, silicon oxide and silicon nitride), were evaluated. Our results indicated that the migration ratios were all below 6%, irrespective of baking temperatures and substrate types. The substrate types did not appear to strongly affect the metallic impurity out-diffusion from deep ultraviolet photoresist. However, solvent and/or water evaporation due to temperature change was found to have a significant effect on metal migration. The net driving force of impurity changes with temperature and the impurity diffusion can be classified into four types. Based on the proposed types, the obtained migration ratios can be realized. A new model, together with a new parameter, was proposed to describe the out-diffusion behavior of impurities from deep ultraviolet photoresist. The diffusion profile of photoresist was depicted based on diffusion equations and the migration ratios. This model could explain the migration ratios of metallic impurities in photoresist layers under various baking conditions.

This paper discusses state-of-the-art technology for controlling contamination and defects during shipping, handling, or storage of reticles. Reticles are used for printing IC patterns onto semiconductor wafers. In lithography process, defects in images are converted to wafers after each exposure, leading to classic failures such as short circuits or opens. Since a large batch of wafers might be processed before the defects are detected, high quality pattern images are very important for yield enhancement. Pattern defects can be created through particle deposition or damage of chrome lines due to Electrostatic Discharge (ESD) events. Airborne Molecular Contamination (AMC) may cause problems such as T- topping of photoresists or optics hazing which reduces image homogeneity and energy transmission. As the critical dimensions shrink to deep submicron regime, the susceptibility of reticle patterns to contaminant continuously increases. To meet increasingly stringent requirements of patterning technology, Reticle SMIF Pods (RSP) are developed. Reticles are encapsulated in the sealed pod to avoid particulate contamination in storage, as well as in manual or automatic transport. Constructed exclusively with static dissipative materials, the RSP provides effective protection for reticles from ESD-induced damage. Molecular contamination is minimized by carefully selecting construction materials. Equipped with an electronic data tracking/controlling device, the RSP can be integrated into OEM tools for automatic reticle management. With optional purge capability, the reticle environment is protected by chemically clean inert gas, which offers additional contamination control. These technologies are extensively discussed in this paper. Design principles and experimental data that support performance evaluations of RSP are presented.

The following paper describes a modular monitoring approach for the photolithography environment, which takes individual measurements and generates three-level monitor. This method is aiming to simplify the process monitoring activity and make it more constructive. The basic monitoring level consists of Normalized indexes for each cell (cluster) -- each raw measurement is transformed into a value between 0 and 1. Second level is Cell index that unites all the Normalized indexes of each cell into one index. The upper level is the Photo index, which combine all the Cell indexes into one parameter. The concept that underlies this approach has few levels. The process engineers that monitor the equipment and process can use the Cell index as a qualitative tool for viewing the current general state of each cell and follow trends. When degradation is observed the Normalized indexes will be used for targeting the source of the degradation. The Photo index and the Cell index will also allow the management personnel to easily track the overall performance of the photolithography equipment and process, and achieve long term improvement by defining goals for the Cell and Photo indexes. The paper describes different options for generating each index in order to manipulate its sensitivity to the characteristic behavior of each individual measured parameter. Additionally, experimental data is presented to demonstrate the performance of the suggested methodology. The raw data is based on more than 120 individual parameters obtained from eight clusters.

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch² regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.

The radioactive tracer technique was applied to investigate the diffusion and adsorption behaviors of metallic impurities (i.e., Ba, Cs, Zn and Mn) from chemically amplified photoresist onto silicon-based underlying substrates. Two important process parameters, i.e., baking temperatures and substrate types (e.g., bare silicon, polysilicon, silicon dioxide, and silicon nitride) were evaluated. Our results indicated that the transition metals (Zn and Mn) could have lower diffusion ratios than alkali metal (Cs) and alkaline earth metal (Ba), irrespective of the substrate types and baking temperatures. It was found that the transition metals would form stable complex with the coexisting solvents and/or hydrolysis species in the photoresist layer. The size of metal complex, the drag force of solvent evaporation, and the baking process were found to have significant effects on impurity migration. In addition, a new diffusion-adsorption model was proposed to explain the effect of substrate types. Our model successfully explained the substrate effect for bare silicon with lower diffusion ratios as compared with silicon nitride. The coverage of substrate surface with silanol group could be attributed to the formation of native oxide. The effects, including the concentration of surface adsorption metal, the equilibrium constant, the surface concentration of silanol group, the concentration of metallic impurity and the pH value, played very important role on the diffusion ratios for Ba, Cs, Zn and Mn.

A new voltage contrast imaging method using single scan of high current electron beam has been developed. This method achieved the automatic inspection system, which detects electrical failures in acceptable amount of time. The sensitivity of the system is evaluated using open failure of via holes. First, the image contrast of poly-Si deposited on defective via holes is measured. Then the cross section of the defects is examined to obtain the correlation between contrast and the thickness of resistive residue at the bottom of the defective via holes. The result shows that this imaging method is capable of detecting 2 nm oxide remaining at the bottom of via.

Stepper autofocus systems can involve reflecting a light beam off the top surface of the wafer (i.e. the top of the photoresist). The density of underlying circuitry causes this relative position to vary, and this will then cause focus errors comparable to the step-height of the underlying pattern. The typical depth of focus in sub-micron lithography is of the same order of magnitude as the maximum step-height on the wafer surface due to topography, so these effects have become significant. Therefore, the optimum focus offset may need to be experimentally determined for each product. For a fab which deals with many products (e.g. a foundry) this requires significant amounts of work. This paper investigates the pattern density effect for metal layers and considers the influence of layer thickness, and the planarization properties of the intermetal dielectric on the optimum focus offset. The possible method for calculating the optimum focus offset by taking the average pattern density under the area of the focus beam from a CAD layout is presented. The usefulness of techniques such as Multi-Point Autofocus is also discussed. Finally, the side-benefits of CMP in reducing this effect are quantified.

Macro defect inspection in the photolithography process has been operated by the operator's naked eye. Operator's inspection performance is not constant and depends on his skill, even if these macro defects are determined as the large scale defect. This paper reports our fully automated macro inspection system and its performance data that were evaluated in the production Fab. Our new system, Nikon AMI-2000, is designed to use the diffraction light imaging which is very effective to detect defocus defects and is designed to use an image processing method. This system has much higher sensitivity than operator inspection, the capability of constant yield management and has a high throughput performance.

This paper proposes a new approach to reducing an effect of floor vibration on an image of a scanning electron microscope. An image-shifting coil is used to move the electron probe in order to cancel undesirable motion of a specimen due to the floor vibration. The floor vibration is structurally transmitted through the microscope and detected by two acceleration sensors at the root of the specimen chamber of the microscope. The outputs of the acceleration sensors are fed forward into a controller to move the electron probe by the image-shifting coil. The feed-forward controllers are designed in two ways. The first one is based on a transfer function from the sensor outputs to the relative displacement of a specimen to the electron probe being at rest. The microscope is put on a table attached to a shaker. Sinusoidal excitation tests are done many times to estimate the transfer functions from vibrating images of a micro scale. Moreover, the second controller is designed by manually amplifying and delaying the sensor outputs so as to minimize amplitude of the vibrating images on a CRT. Those two controllers are implemented as a digital filter running on a digital signal processor.

A production application of optical proximity correction (OPC) aimed at reducing corner-rounding and line-end shortening is described. The methodology, using critical shape error analysis, to calculate the correct serif size is given and is extended to show the effect of OPC on the process window (i.e. depth-of-focus and exposure latitude). The initial calculations are made using the lithography simulation tools PROLITH/2 and SOLID-C, the results of which are transferred to the photo-cell for practical results.

A new metric for set-up of resist processes on transparent films is described using CMOS active area layer as a test vehicle for lithography simulations. Results show that the metric Es/Ec, where Es is exposure to size and Ec exposure to clear a high resolution feature, is more useful than the conventional ratio Es/Eo and where Eo is exposure to clear an open field area. High values of Es/Ec can protect against resist scumming if film thicknesses are chosen correctly, but if not accounted for at the sub-half-micron scale can be as low as 1.1. Where film thicknesses predict low Es/Ec, the ratio can be increased by use of bottom ARC.

A simple model for light scattering by a Crystal Originated Particle (COP) was studied using surface scattering theory. By use of this model, we can explain the base of the separate detection technique for COPs and particles, which is one of the important features of the Wafer Surface Analyzer WM-3000 (Topcon, Japan). As the first approach, Angle Resolved Scattering (ARS) formula was applied and the cross-section of a COP was assumed to be a square in general, but it sometimes changed the shape from a triangle to a trapezoid due to a beam scanning path on a wafer. The intensity distribution of the scattered light was calculated for each shape of many kinds of cross-section, and was averaged over them. Then, the relative intensity distribution of the scattered light was calculated. The optical system of WM-3000 has two incident beams with different conditions. It is possible to detect COPs and particles separately using difference between their scattering characteristics. To compare the results of calculation with the measurement, the ratio between two scattered beams caused by two different incident beams was calculated. It was shown that calculated ratio is qualitatively agreed with the value measured with WM-3000.

The variation of dimensional control between center and edge of a stepper lens field is measured both practically and by lithography simulation for both lines and slots at various pitches. Results for lines show that the sign of the center- edge offset is pitch dependent but for slots the dimension is always larger at center field irrespective of pitch.

Although the subject of frequent concern, criticism, and attention in the modern semiconductor fabrication facility, human after develop inspection (ADI) does not catch the major scrap and yield events early enough, if at all. The overall success of scrap and photo redo reduction programs over past years has resulted in residual problem levels which are difficult to improve upon -- yet still very costly. Detected 'events' are few and far-between, although evidence of their prevalence is frequently seen at subsequent inspections, or finally at probe. In the ASIC fab, they put on-time delivery to customers at risk, because individual wafer lots in an ASIC facility have a designated customer. The sampled area is limited by human throughput to less than 10% of the wafers in a lot. The visual ADI process step is unpopular among manufacturing technicians. It is often a bottleneck in the photo area. Statistically, in a photo area with capacity of 5000 wafer starts per week, only a few wafers processed per day are destined for scrap. Since wafer events occur in sporadic clusters, the photo area experiences only a few significant incidents per month. The typical operator can expect to intercept such an event less than once during several months of otherwise uneventful ADI inspection haystack.' Hence the stubbornness of our residual problem. Going beyond the statistical problem, our current manual macro-inspection equipment is engineered appropriately to ancient IC generations. A collimated, oblique-oriented light was an effective darkfield illumination source, when line widths were much larger than the wavelength of light. When line width is comparable to, or smaller than, the wavelength, the collimated light source produces scintillating diffracted colors on the wafer. Thus diffraction 'noise' significantly buries the defect 'signal' in the typical bright light visual macro inspection. In addition, there is the problem of variability between human inspectors, and the impossibility of accurate classification and recording of defect types, locations, and layer of occurrence. In this paper, we discuss a pilot implementation of an automated macro inspection system at Motorola, Inc., which has enabled the early detection and containment of significant photolithography defects. We show a variety of different types of defects that have been effectively detected and identified by this system during production usage. We introduce a methodology for determining the automated tool's ability to discriminate between the defect signal and process noise. We indicate the potential for defect database analysis, and identification of maverick product. Based upon the pilot experience, we discuss the parameters of a cost/benefit analysis of full implementation. The costs involve tool cost, additional wafer dispositions, and the engineering costs of recipe management. The most tangible measurable benefit is the saved revenue of scrapped wafers. An analysis of risk also shows a major reduction due to improved detection, as well as reduced occurrence because of better containment. This reduction of risk extends both to the customer -- in terms of field failures, OTD, maverick product -- as well as to the production facility -- in terms of major scrap incidents, forced inking at probe, redo, and containment.

Optical proximity correction in terms of linewidth correction at different pitches is used to demonstrate improvement in critical dimension control at the polysilicon layer of a sub- half-micron CMOS process. Further measurements across the image field show the effect on wafer linewidth distributions of different generations of the laser write tool used in reticle manufacturing.

With the large field sizes scanners offer today, lens mapping (dense across-the-field CD measurements to quantify illumination and coherency aberrations) requires an extensive number of line width measurements to be taken for accurate lens evaluation. There are concerns that the accuracy required for field mapping may not be possible with a Top-Down SEM, pushing the industry to move to electrical CD (ECD) measurement. However, the etch process required for ECD can induce systematic error, either from the iso-dense etch bias or from the equipment itself. This paper explores the capability of utilizing an in-line CD SEM for extensive CD measurement collection and the requirements to achieve statistically valid data for lens mapping.

Fused silica and calcium fluoride are the standard lens materials for the 193 nm (ArF excimer laser) generation step and scan systems. In this paper, the author reports measurements of induced birefringence in both fused silica and calcium fluoride samples exposed to ArF excimer laser irradiation. A new birefringence measurement instrument, known as the Exicor^TM system, was used for mapping birefringent images. Different patterns of induced birefringence in fused silica samples were observed for samples irradiated with 'unpolarized' and polarized excimer lasers. Birefringence induced in fused silica with linearly polarized excimer laser irradiation contradicts the traditional compaction model. The measurement result of a CaF₂ element confirms that 193 nm excimer laser irradiation induces no observable birefringence in CaF₂.

Defect reduction for both process development and line monitoring requires not only capturing the defects, but also determining which are yield limiting, and then systematically eliminating these defects. A methodology has been successfully implemented at VLSI-Phillips providing for defect reduction and monitoring based on automatic defect classification. A wafer inspection tool (WF700 series) with 'on-the-fly' automatic defect classification (OTF-ADC) is utilized to capture and segregate defects of interest during the inspection with no loss in throughput. After determination of which defects have yield impact, the inspection is optimized to capture, classify, and track these defects with separate SPC limits. With the OTF-ADC segregation, the key defects of interest can be separately monitored for excursions. If an excursion is manifest, the corrective action can then be immediately implemented. Various cases are discussed including missing vias, metal bridging, and metal sidewall defects. Yield loss analysis was used for defect prioritization.

Charging effects on beam deflection of incident electrons in electron beam lithography are investigated. We shows first in detail how the non-unity yield of electron generation in insulator resist leads to local charging accumulation and affects the beam deflection of incident electrons as charging develops. Then the amounts of beam deflection are identified for various operating and resist dimension conditions, and then we conclude that the beam deflection should be avoided for more accurate manufacturing semiconductor devices by the control of charging effects.

The common baseline for lithography process control is the assumption of the presence of a uniform substrate. This assumption may lead one to disregard variations introduced by the substrate thickness and optical properties. With the reduction of lithographic feature size, the impact of the substrate optical parameters, neglected until now, increases and reaches a level that has a tangible contribution to the CD budget. Non-uniformity of substrate and/or ARC create CD variations. A first step should be the measurement of the actual reflectivity variations, then compare the process reflectivity variations relative to the exposure latitude. The reason is the impact of the reflectivity of the substrate/photoresist interface on the amount of absorbed energy inside the photoresist itself. In this paper we present measurement data from the NovaScan 420 Integrated Thickness Monitoring (ITM) system that has been gathered during CMP process steps of several 0.18 and 0.25 technologies. Data was extracted from a large database collected worldwide. We analyzed the actual thickness scatter of the top polished oxide layer as well as measurements of the thickness variations of layers below the top oxide (e.g. TiN, Oxynitrides). These data were used for the analysis of the substrate/photoresist interface reflectivity variations at lithography steps. The analysis enabled simulation of 'across the wafer' reflectivity profiles at the DUV wavelengths. It appeared that some applications (e.g. photoresists on dielectrics) presented 20% 'across the wafer' variations in substrate reflectivity while others (e.g. photoresist on metal) did not show any variations. 'Wafer-to-wafer' trends reveal that the average values of the wafer indicate small changes, while site-to-site differences are consistent and non-negligible. Usually the tests that investigate the CD sensitivity to ARC or other substrate layers reflectivity do not reveal the expected correlation since the substrate optical reflectivity is not the dominant factor. PEB temperature, develop uniformity, dose control, focus control and metrology noise may have similar contributions that hide the CD correlation to reflectivity. Estimations for the actually achieved improvements for each application will be presented, together with the data collection requirements necessary to show the reduction of CD variations (such as: large sampling, integrated tool, angstrom level repeatability). Using the measured ITM system data, we suggest to use 'wafer-to-wafer' trends and wafer reflectivity maps to create compensation for the reflectivity variations by adjusting the coating thickness or the exposure dose respectively. In some cases the 'across the wafer' and 'wafer to wafer' data will illustrate the need for Integrated Metrology. This will enable the monitoring of the ARC thickness, refractive index, optical extinction coefficient, and also other layers that have an important contribution to the reflectivity.

This paper studies the characteristics of a solvent-rich coating process which has demonstrated its abilities to provide wider resist thickness range and better coating uniformity on square substrates. The coating recipe being studied consists three spin steps, spread spin (1st spin), snap spin (2nd spin), and dry spin (3rd spin). A two-level, six-factor fractional factorial design of experiment (the screening test) is conducted first to determine which process parameters the film thickness and coating uniformity is sensitive to. A response surface model is then built for those significant factors. The screening test found that 3rd spin speed and time do not affect film thickness significantly, but should not be ignored in controlling coating uniformity. On the other hand, both 1st and 2nd spin speed and time are important to film thickness as well as coating uniformity. This is contrary to traditional coating systems where spin time is typically not an important factor in determining coating thickness. The central composite design was used to obtain the response surface model (RSM). Analysis shows that the model is adequate to represent the characteristics of a solvent-rich coating system. The four major factors, i.e., 1st spin speed and time, and 2nd spin speed and time are the dominant independent variables in determining film thickness. The first-order interactions between these major factors are weak. It is interesting to notice that the response surface model for coating uniformity is very unreliable, represented by poor model fitting statistics and high p values for individual factors. This is possibly due to the exclusion of 3rd spin speed and time in the central composite design.

Fused silica is the optical material of choice for deep ultraviolet (DUV) lithographic systems. However, this material is subject to irradiation-induced compaction with ArF excimer radiation. Here we report direct, at-wavelength, wavefront measurements of DUV-laser-damaged fused silica samples performed using phase-shifting point diffraction interferometry (PS/PDI). Experimental results show that the damage anneals in the temperature range of 200 to approximately 600 degrees Celsius. Finally, the interferometric measurements are compared to birefringence studies performed on the same samples.

An effective methodology has been utilized at AMD to ensure a reliable lithography step. This methodology is based on short loop test wafers that are scanned for defects by a patterned wafer inspection system. The defects are classified during the initial inspection, and with the classified defect count and results, the lot disposition is then determined. The key requirement is to rapidly obtain information on the various yield-limiting defects, so that these defects can be sourced and then eliminated. It proved possible to capture, classify, and analyze defects that could have lead to yield loss. A WF736 wafer inspection tool was utilized with 'on-the-fly' automatic defect classification (OTF-ADC) capability that segregates defects during the inspection. A wide variety of defects were detected, and the OTF-ADC permitted the separate counting of the critical defects and facilitated both excursion detection and defect analysis. Defects included scumming, surface particles, embedded particles, developer residue, drip, irregular pattern, missing pattern, and other pattern defects. With the classification, more rapid sourcing and elimination was possible. In one example, an excursion was detected which would have been hidden using simple total count inspection. In addition, it proved possible to identify and segregate defects not associated with the litho step.

With the rapid advances of deep submicron semiconductor technology, identifying defects is converted into a challenge for different modules in the fabrication of chips. Yield engineers often do bitmap on a memory circuit array (SRAM) to identify the failure bits. This is followed by a wafer stripback to look for visual defects at each deprocessed layer for feedback to the Fab. However, to identify the root cause of a problem, Fab engineers must be able to detect similar defects either on the product wafers in process or some short loop test wafers. In the photolithography process, we recognize that the detection of defects is becoming as important as satisfying the critical dimension (CD) of the device. For a multi-level metallization chemically mechanical polish backend process, it is very difficult to detect missing contacts or via at the masking steps due to metal grain roughness, film color variation and/or previous layer defects. Often, photolithography engineer must depend on Photo Cell Monitor (PCM) and short loop experiments for controlling baseline defects and improvement. In this paper, we discuss the findings on the Poly mask PCM and the Contact mask PCM. We present the comparison between the Poly mask and the Contact mask of the I-line Phase Shifted Via mask and DUV mask process for a 0.18 micron process technology. The correlation and the different type of defects between the Contact PCM and the Poly Mask are discussed. The Contact PCM was found to be more sensitive and correlated to contact failure at sort yield better. We also dedicate to study the root cause of a single closed contact hole in the Contact mask short loop experiment for a 0.18 micron process technology. A single closed contact defect was often caused by the developer process, such as bubbles in the line, resist residue left behind, and the rinse mechanism. We also found surfactant solution helps to improve the surface tension of the wafer for the developer process and this prevents/eliminates a single closed contact hole defects. The applications and effects of using different substrates like SiON, different thicknesses of Oxides, and Poly in the Contact Photo Mask is shown. Finally, some defect troubleshooting techniques and the root cause analysis are also discussed.

In this paper, I will present a methodology of using post etch wafers with multiple overlay targets to characterize the Wafer Induced Shift (WIS). The overlay targets consists of both embedded and exposed structures that represent the post develop and post etch measurements respectively. This methodology provides a metric to quantify the WIS in the process, defined as the difference between post develop measurement, or develop check (DC), and post etch measurement, or final check (FC). It also allows us to characterize the overlay tool, the overlay target and the process variability altogether and to improve the correlation between DC and FC measurements.

Critical dimension (CD) control is very important for the successful fabrication of integrated circuit (IC) devices. Line-widths of patterns such as chrome lines or clear lines on the reticle have to be monitored. In this work, reticles with optical proximity correction (OPC) assist features intended for deep ultraviolet (DUV) exposure have been investigated using the atomic force microscope (AFM). Metrology issues related to using AFM to measure CD are presented. A line-width determination method to produce a consistent CD measurement is proposed. The CD uniformity for a 4X, 6' reticle intended for DUV exposure is found to be within plus or minus 20 nm over a range of 2.00 micrometer to 0.4 micrometer and to be worse when the widths of the lines are nominally less than 0.4 micrometer.

The Wafer-Induced-Shift (WIS) is the overlay measurement error due to the reflection trick of the metal film by Physical Vapor Deposition, specially sputtering. The WIS happens to the wide open type mark because this sputtering method can cause a non-symmetric edge deposition by the self-shadowing of mark depth. But the marks with a wide width and space, which are currently used in the industry, have not detected the WIS. It is the modification of overlay measurement mark that has to be primarily improved to solve this problem. So we suggest the new methodology using the overlay mark with the narrow space. The concept of this mark is to use the geometrical property of deposition and detect the optical contrast signal of the space-type mark instead of the edge contrast signal of wide bar-type mark. This will reduce the non-symmetric deposition property by the self-shadowing. In this paper, we conformed the WIS using the overlay errors after and before etching film, and reported the effectiveness of our new mark by using the sputtered Pt film being one of the electrodes of BST capacitor. Several marks with a space 0.2 micrometer up to 0.5 micrometer were examined for the various thicknesses of the film by comparing the overlay measuring error between the standard mark and the new mark, and correlating the degree of the metal filing into the narrow space of overlay mark with the wafer scale factor. From the experimental results, we can find that the major component of WIS is the wafer magnification factor, and the new mark had a good feasibility for the WIS and might be called the WIS-free mark. Additionally we will discuss more details of our experimental results.

In the next few years, advanced process technologies in Wafer Fabs will migrate rapidly to ArF lithography for the 100 nm node and beyond. Reticle enhancement techniques (OPC, PSM) will be used more widely in multiple masking layers. However, a challenge in the manufacturing of OPC/PSM reticles is the lack of a precise specification for defect inspection to reflect the printability on wafers. In this paper, a binary mask with OPC/SB and with both CF/DF polarities comprising of 3 design rules: 0.13, 0.15 and 0.18 micrometer, will be used for the defect printability study. Polysilicon test wafers with SiON anti-reflective film will be processed with a standard 248 nm DUV resist on the ASM5500/500 scanner and with a 193 nm resist on the ASM5500/900 scanner, using the highest NA (0.63) an the highest sigma (0.60) possible. Differential SEM CDs between defect features and nominal features (without defect) will be analyzed for each design rule and for each wavelength respectively. SEM images of Clear and Dark field patterns for 193 nm exposure will be shown qualitatively. Finally, the impact of scattering bar sizing and reticle repairs to the wafer printability at 193 nm will be discussed.

The significant optical absorption of most currently available commercial single layer 193 nm resists, even at a coating thickness of 0.4 micrometer, implies increased sensitivity to process control fluctuations of the kind that negatively impact critical dimension (CD) uniformity, process latitude, resist sidewall profile, and line edge roughness. These problems, although less severe on reflective substrates, are particularly acute on wafers with bottom anti-reflection coatings (BARCs), which are useful in CD control. With different intensity of light reaching different levels in the resist film on a BARC, a gradient is thus established in the extent of the chemical amplification reactions on which semiconductor lithography is based. The result is the familiar sloped sidewall profile and poor CD uniformity after the resist is developed. Further, with most of the photoacid generators and the polymer resins in the 193 nm resists having very low quantum efficiencies and significant absorption at 193 nm, respectively, most of the absorbed light in the resist is used up in energy dissipative processes, instead of in generating photoacids which catalyze the chemical amplification chemistry of these resists. One approach to overcome this absorption problem is to use significantly thinner resist films, but etch considerations preclude such option as these materials do not have very good etch stability. The purpose of this paper is to quantitatively assess the impact of absorption on the process control of sub- 0.15 micrometer features patterned on a full field ASML 193 nm scanner, interfaced to a TEL MARK-8 track. Optical properties of different resist films/BARC stack combinations are characterized by UV spectroscopic ellipsometry and broad band spectrometry, and sidewall profiling is done by atomic force microscopy.

A novel method of measuring absolute position using broad band laser interferometry is presented. The interferometer has been designed and implemented as the metric for a real-time stage focus micro-lithography application. Highlights of the metric are high precision (less than 100 nm) and wide range (300 microns).

Dual Damascene (DD) process has been implemented in manufacturing semiconductor devices with smaller feature sizes (<EQ 0.20 micrometer), due to increased use of copper as a metal of choice for interconnects. Copper is preferred over aluminum due to its lower resistance which helps to minimize the effects of interconnect delays. Via first DD process is the most commonly used process for manufacturing semiconductor devices since it requires less number of processing steps and also it can make use of a via fill material to minimize the resist thickness variations in the trench patterning photolithography step. Absence of via fill material results in non-uniform fill of vias (in isolated and dense via regions) thus leading to non-uniform focus and dose for exposure of the resist in the deep vias. This results in poor resolution and poor critical dimension (CD) control in the trench-patterning step. When a via fill organic material such as a bottom anti- reflective coating (BARC) is used, then the resist thickness variations are minimized thus enhancing the resolution and CD control in trench patterning. Via fill organic BARC materials can also act as etch blocks at the base of the via to protect the substrate from over etch. In this paper we review the important role of via fill organic BARCs in improving the efficiency of via first DD process now being implemented in semiconductor manufacturing.

Measurement system analysis is essential for determining the quality of data used for process control. Analysis of variation, or ANOVA, is a commonly used technique for measurement system analysis. Recently, the Advanced Metrology Advisory Group at SEMATECH has proposed using the Latin Square technique for determining the reproducibility and repeatability of a CD SEM. Advantages and disadvantages of the two techniques will be discussed.

An accurate measurement technique for effective exposure dose in optical microlithography has been developed. The effective exposure dose can be obtained by a dose monitor mark in a photomask named effective dose-meter, consisting of plural segments including grating patterns with a pitch below the resolution limit and different duty ratios gradually. Since the effective dose-meter does not resolve on a wafer but it makes flood exposure with the dose as a function of the duty ratio, residual thickness of the photoresist after development changes according to the duty ratio. Therefore, the effective exposure dose can be obtained by grasping the duty ratio of the grating patterns in the effective dose-meter corresponding to the position that the photoresist had cleared completely. A calibration technique utilizing an aerial image measurement system also has been proposed to avoid the influence of intra- wafer process variation. The advantages of this method are (1) completely focus-free, (2) the effective dose-meter is small enough to ignore the influence of the intra-wafer process variation on the accuracy, and (3) highly dose resolution of less than 0.5%. It was found that this technique function effectively. The variation of the effective exposure dose in a wafer in the current krypton-fluoride-excimer-laser lithography process was measured as a demonstration of this technology.

To have a more complete and clear picture for resist characterization, a second metric is needed to supplement the traditional linewidth data. A fast and non-destructive metrology system is desired to provide resist profile information. Electron scan and SEM image correlation capability will provide this second metric to effectively select the correct and precise process window. Monitoring for high electron line scan correlation values allows one to maintain a sharp sidewall profile of photoresist while supporting high aspect ratios. This is ideal for magneto- resistive (MR) and inductive thin film recording head coil plating and many other mission-critical applications. An automated top-down CD-SEM technique, capable of acquiring and analyzing electron waveform profiles of resist lines in addition to the traditional linewidth values is reported here. These measurements were made using a KLA-Tencor 8100 CD SEM, taking advantage of its new Pattern Quality Confirmation (pQC) feature. Process engineer using pQC can correlate signal intensity and images against stored templates, and then output the correlation scores. The technique has been applied to silicon wafers coated with various AZ^R photoresists, such as AZ^R 3300, AZ^R7200, AZ^R7500, and AZ^R7900, with thickness of 1 - 3 microns. Wafers were exposed using a Nikon I line stepper and then developed by AZ^R 300 metal ion free developer. Focus-Exposure dose-array fields were measured to investigate their profiles transformation as well as CD through and beyond their exposure latitude. Correlation scores were derived using aspect ratio of film thickness vs. CD size in each resist family. The study was extended by inspecting 'image correlation' values of high aspect ratio Contact Holes. Possibility of automating determination of open versus closed Contact Holes printed in these photoresists is also discussed. The goal of this study is to optimize determination of acceptable process window, by utilizing line and image correlation to compliment CD data.

Besides feature size control of advanced semiconductor device manufacturing, critical dimension (CD) measurement SEMs are also indispensable tools for the development of advanced semiconductor manufacturing equipment or new semiconductor manufacturing materials. Especially in the case of advanced stepper and resist development for ultra micro patterns where the role of CD-SEMs is particularly important for evaluation specific samples, such as focus exposure matrix (FEM). An FEM sample is a wafer that has hundreds to thousands of patterns created with varying resist exposure dosage and Stepper focuses. As a result, the pattern shape and the line width vary dramatically within one wafer and the number of CD-SEM measurement points necessary to evaluate such FEM samples also increases drastically with decreasing semiconductor design rules. Thus, a CD-SEM that can measure FEM samples with high throughput and high reliability is strongly desired. For this purpose Hitachi has developed a new pattern detection algorithm. This algorithm detects a target and judges the quality of the actual pattern by using criteria similar to those a human operator might use when measuring the sample. With this method implemented on a Hitachi CD-SEM S-9200 we achieved a highly automated, fast and accurate measurement of FEM samples on which conventional algorithms failed.

The accurate measurement of an exposure dose reaching the wafer on an extreme ultraviolet (EUV) lithographic system has been a technical challenge directly applicable to the evaluation of candidate EUV resist materials and calculating lithography system throughputs. We have developed a dose monitoring sensor system that can directly measure EUV intensities at the wafer plane of a prototype EUV lithographic system. This sensor system, located on the wafer stage adjacent to the electrostatic chuck used to grip wafers, operates by translating the sensor into the aerial image, typically illuminating an 'open' (unpatterned) area on the reticle. The absolute signal strength can be related to energy density at the wafer, and thus used to determine resist sensitivity, and the signal as a function of position can be used to determine illumination uniformity at the wafer plane. Spectral filtering to enhance the detection of 13.4 nm radiation was incorporated into the sensor. Other critical design parameters include the packaging and amplification technologies required to place this device into the space and vacuum constraints of a EUV lithography environment. We describe two approaches used to determine the absolute calibration of this sensor. The first conventional approach requires separate characterization of each element of the sensor. A second novel approach uses x-ray emission from a mildly radioactive iron source to calibrate the absolute response of the entire sensor system (detector and electronics) in a single measurement.

Specular Spectroscopic Profilometry (SSP), or Phase Profilometry (PP), has been proposed for in-situ/in-line patterned thin-film measurements. This is usually accomplished by using a rigorous electromagnetic theory to simulate the optical responses of gratings with different profiles, and by using spectroscopic ellipsometry/reflectometry to measure 1-D gratings. In this paper, specular spectroscopic profilometry is applied in DUV lithography and etch processes as a profile extraction metrology. One focus-exposure experiment is conducted by using 0.18 micrometer lithography technology, another focus-exposure experiment is conducted by using 0.18 micrometer lithography and etch technology. Comparison between the measurement from CD-SEM, CD-AFM and PP are discussed and explained.

According to the classical calculation of overlay margin as 1/4 design rule, the overlay control requirement for sub-0.15 micrometer design rule device is nominally below 40 nm. To meet this demand, it is necessary that one should analyze every part in global alignment and overlay measurement procedure, then factor out the parameter that is known to affect overlay control, and correct it as much as possible. One of the major causes degrading overlay budget seems to be the nonoptimized wafer sampling method. Compensated but undercorrected overlay errors usually fitted as linear terms can be amplified due to improper sampling method e.g. asymmetric one. In this paper, we have investigated the possible causes that yield global alignment noise and the sampling method dependency of global alignment repeatability and overlay model calculations. The achievement of better alignment repeatability is critical for improving not only in- wafer overlay but wafer-to-wafer overlay control. It is thus evident that overlay control can be improved by reducing alignment noises or by optimizing sampling method. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected as global alignment purpose. This result can be understood as noise margin is different for each sampling plan and there exists an optimal sampling method. We tested several sampling methods that belong to symmetric group (translation, inversion, rotation symmetric), which are known to show better noise margin. The criteria to select the best sampling method were residual and linear term reproducibility which are significantly affected by raw data noise. The raw data variations include stage position errors and process induced alignment signal abnormality. We found among the candidates the optimal sampling method which leaves the least residual and shows as good repeatability as full chip measurement. Similar results could be obtained for overlay sampling method.

It has been well documented that DUV lithographic processes are sensitive to airborne contamination such as ammonia and n- methyl-2-pyrrolidone (NMP). Chemical filtration technologies have aided in minimizing the problems associated with these contaminants in the photolithographic process. As the demand for smaller features increases, so will the need to operate within even cleaner environments than are available today. One such area where airborne contamination has proven to be of significant concern, is within the lensing system of the tool. With decreasing feature size, the lithographic process has proven to be more sensitive to contamination of the lens itself, and within the environment surrounding the lens. Condensation on the lens (hazing) and the presence of contamination between the lens and substrate can result in poor optical transmission. To minimize these problems, a purge gas is typically employed. Even though high purity gases are used, contamination within the gas still is an issue. This work describes our efforts directed at understanding the purge gas and lens environments. In addition, we will address our efforts that have focused on the development of chemical filters that provide environments for optimized optical transmission in lithographic applications.

As process technology in high volume production fabs hits the 180 nm window, overlay metrology of the most critical layers needs to be managed very carefully. As feature sizes and other device characteristics shrink, the overlay requirement becomes a larger component of the overall process specification. It is no longer sufficient to measure overlay for only two layers at a time. In no other part of the process is this more critical than the poly and active layer to first contact. The contact layer needs to be aligned to both active and poly within tight tolerances. Since adjustments to overlay for these levels are not independent, it is essential to understand the relationship between all three layers. TSMC in particular, because it is a foundry, is not able to optimize customer circuit design that would allow two-layer registration to be sufficient. Previously, the only method to accomplish this has been to make two sets of overlay measurements and having an engineer analyze the relative overlay between the three layers. The proposed solution to solve this problem is a multi-layer overlay measurement algorithm and measurement target. This paper will report on the analysis of the process improvements that have and can be achieved using this unique measurement capability.

With the advent of deep sub-micron semiconductor technology, metrology for metal interconnects becomes more critical. In addition to the line width, information about the height and the sidewall profile is needed to ensure good circuit performance. Conventional metrology tools such as CD SEMs and AFMs are either unable to measure the profile, or too slow for production process control. Scatterometry is a promising candidate as in situ, full-profile metrology tool. In this method, scattering of broadband light (240 nm to 760 nm) on periodical structures is simulated by approximating the structure with a finite series of Fourier expansion terms. By comparing the measured spectrum and the simulated spectra for various possible profiles in a precalculated library, the profile can be extracted. Previous work has shown good results on resist structures. For metal structures, however, more diffraction orders need to be included to accurately simulate light scattering. In this study, a library for 0.22 micrometer line and 0.44 micrometer space metal grating structures is generated using 31 orders. The profiles of metal grating structures of the same size are extracted using this library. Our data shows that the correlation between CD-SEM and scatterometry-based profile extraction appears to be related to the sidewall angle of the profile. These discrepancies will be analyzed and discussed.

The influence of sample charging in CD measurements by a SEM based metrology system has been continuously decreased through lower electron beam landing energy, lower electron dose (a combination of lower beam current and less integration time) and faster scan speed. However, as IC industry marches towards 100 nm gate width, the demand for less than 1 nm precision CD- SEM grows. Charging continues to be the one of the biggest hurdles to reach that goal. Additional charge control measures are needed. We propose an approach to utilize extraction voltage in charge control. When varying extraction voltage strength, a CD-SEM can be tuned (through the combination of beam energy and extraction voltage) to operate at energy of balancing the total injected charge and the total emitted charge for a specific substrate. The preliminary experiment results support such a proposal.

Tool cost of ownership and manufacturing productivity continue to be key factors in equipment selection discussions. Products that differentiate themselves by maximizing tool utilization and minimizing engineering resources make the best economic impact in a time of increasing fab capital costs. This paper will demonstrate the use of a single off-line recipe database manager (RDM) in conjunction with multiple optical misregistration measurement tools for the purpose of misregistration recipe creation and management in a high volume ASIC manufacturing line. A strategy for minimizing the number of recipe elements and the amount of time required to create and maintain all recipes will be discussed. Data will be presented which demonstrates significant reduction in tool time required for recipe setup, leading directly to increased tool availability for production use. In addition, the RDM allows for standardization of misregistration measurement setup for similar process levels across multiple product devices within a single product family. Data will be shown demonstrating TIS stability and consistency as a result of the standardized setup. Future work, including fully automated recipe creation via CAD output data would be discussed.

Photolithography using 157-nm pulsed F₂ lasers has emerged as the leading candidate technology for the 0.1 micrometer lithography node for the post-193-nm generation. The extension of operating wavelength to the VUV range presents new challenges for thin film metrology tools, such as ellipsometers and spectrophotometers, most of which have not yet shown robust performance at high accuracy at wavelengths below 193 nm. Knowledge of material optical properties near 157 nm is essential for several areas of microlithography, such as (1) optimization of resist and bottom antireflectance coating (BARC) and lithographic performance modeling; (2) development of thin dielectric layers for lens coatings, including antireflectance, beamsplitter and high reflectance designs; and (3) development of resolution enhancement techniques, such as attenuating phase shifting masks. In this work we review our experience with VUV spectrophotometers, as well as techniques for obtaining stable reflection and transmission measurements necessary for deriving optical constants of thin films. In particular, we find that reliably accurate reflection data can be obtained only using absolute reflectance methods. Extraction of optical constants is performed utilizing global optimization methods with a commercially available software package. Kramers-Kronig- consistent dispersion relations are used to describe the material dielectric constants. We will present real and imaginary refractive index values of various thin films, as determined from reflection/transmission data into the deep UV wavelengths to as low as 140 nm. A separate study designed to understand scatter losses of materials at 157 nm will also be described. We have constructed a 157-nm laser-based scatterometer for obtaining bidirectional reflection distribution function (BRDF) measurements. By correlating scatter signals with total transmission losses, we are able to separate absorption from scatter effects.

Due to the continuing decrease of the Rayleigh lithographic K1 factor used in advanced semiconductor technology, the non- linearity between designed and printed circuit images continues to increase. This increasing non-linearity has significant implications for the layout design rules with advanced technology. Recently, industry pundits have speculated that lithographic K1 factors can go far below current value. This paper aims to understand the impact of low K1 lithography upon a set of basic, company independent, layout design rules, the lambda based rules proposed by Mead and Conway. The results show that even with the use of aggressive optical proximity correction (OPC) techniques, significant changes in layout design rules will have to be made in order to extend lithographic capability to the low K1 regime.

CD-SEM dynamic accuracy and stability is fundamentally linked to the quality of beam tuning. One source of beam instability is stigmation drift. Uncorrected stigmation drift can account for, in extreme cases, up to 20 nm of CD error on a 0.18 micrometer linewidth. As most current CD-SEMs do not feature robust auto-stigmation systems, periodic beam tuning is usually performed manually. This solution, however, does not yield the desired results, as a 0.18 micrometer linewidth can still err by unacceptable amounts due to human variability. One method of monitoring beam quality is the use of fast- Fourier transform (FFT) techniques, as first described by Postek and Vladar of NIST, where an FFT of an image of a very fine, random, isotropic, high-contrast defect surface is used to calculate beam sharpness and eccentricity. Advantages of this are: (1) beam-tuning is controlled to the point that measurements of 0.18 micrometer linewidths after the beam tuning vary by only 2 nm, (2) this result is rendered operator-independent, and (3) the resulting sharpness and eccentricity values quantify the beam quality and do not bias with time due to charging, as do repeated linewidth measurements (i.e. as in a 'hammer test'), allowing trend- chart to be used for process control. This FFT technique has been implemented in SEM Monitor, a software package from Spectel Company, under contract by Sematech AMAG. This software is now used for periodic qualification of our production CD-SEMs. This article demonstrates our evaluation data of the Spectel SEM Monitor workstation, resulting beam- stability trend data of our OPAL 7830Si CD-SEMs, and details about the sample used with this technique.

Effective sample planning requires a careful combination of statistical analysis and lithography engineering. In this paper, we present a complete sample planning methodology including baseline process characterization, determination of the dominant excursion mechanisms, and selection of sampling plans and control procedures to effectively detect the yield- limiting excursions with a minimum of added cost. We discuss the results of our novel method in identifying critical dimension (CD) process excursions and present several examples of poly gate Photo and Etch CD excursion signatures. Using these results in a Sample Planning model, we determine the optimal sample plan and statistical process control (SPC) chart metrics and limits for detecting these excursions. The key observations are that there are many different yield- limiting excursion signatures in photo and etch, and that a given photo excursion signature turns into a different excursion signature at etch with different yield and performance impact. In particular, field-to-field variance excursions are shown to have a significant impact on yield. We show how current sampling plan and monitoring schemes miss these excursions and suggest an improved procedure for effective detection of CD process excursions.

Precision is deemed the most important aspect of a measurement for process control. This paper discusses the role of accuracy in process control and product quality. Although the discussion is emphasized for CD SEM metrology systems, the idea can be extended to other metrology areas such as thickness measurement where in addition to thickness, material characteristics also play a role. In 1999, the characteristics of accuracy were published in a landmark paper. The authors introduced the concept of characteristic slope and offset for the purpose of tool evaluation. Slope and offset were obtained from correlation plots of a measurement tool under test with a reference measurement system. The measurands were features that represent the range of process variations in a line. This paper builds on the ideas put forth in that reference and discusses the impact of measurement accuracy on process control. First, the issue is considered in an abstract sense, by comparison of the measurement method under test to a standard reference method. Then practical implications are discussed in more detail when tools from different suppliers are used in a fab to manufacture products.