Two primary tracks of DfM, one originating from physical design characterization, the other from low-k₁ lithography, are described. Examples of specific DfM efforts are given and potentially conflicting layout optimization goals are pointed out. The need for an integrated DfM solution than ties together currently parallel DfM efforts of increasing sophistication and layout impact is identified and a novel DfM-enabling design flow is introduced.

As manufacturers employ emerging advances in lithographic technologies, the need for complementary improvements in design processes becomes critical. In moving to nanometer technology nodes at 90nm and below, semiconductor companies will face increased challenges for optimizing yield beyond traditional post-processing methods. Instead, increasing responsibility for yield improvement will focus on lithography-friendly design methodologies and adoption of improved design-for-manufacturability (DFM) practices able to address manufacturing yield issues from first silicon, into production ramp-up and during volume manufacturing. Among emerging DFM practices, "yield-focused" design tools and methodologies address yield-loss mechanisms arising with nanometer technologies. By employing these emerging tools and methodologies, engineers can address manufacturing-induced yield problems early in the design process and through manufacturing.

We consider modern design for manufacturing (DFM) as a manifestation of IC industry re-integration and intensive cost management dynamics. In that regard DFM is somewhat different from so-called design for yield (DFY) which essentially focuses on productivity (yield) management (that is not to say that DFM and DFY do not have significant overlaps and interactions). We clearly see the shaping of a new "full-chip DFM" infrastructure on the background of the "back to basics" design-manufacturing re-integration dynamics. In the presented work we are focusing on required DFM-efficiencies in a "foundry-fabless" link. Concepts of "virtual prototyping of manufacturing", "design process optimization", and "foundry-portable DFM" models are explored. Both senior management of the industry and leading design groups finally realize the need for a radical change of design styles. Some of the DFM super-goals are to isolate designers from process details and to make designs foundry portable. It requires qualification of designs at different foundries. In their turn, foundries specified and are implementing a set of DFM rules: "action-required", "recommended", and "guidelines" while asking designers to provide netlist and testing information. Also, we observe strong signs of innovation coming back to the mask industry. Powerful solutions are emerging and shaping up toward mask-centered IP as a business. While it seems that pure-play foundries have found their place for now in the "IDM+" model (supporting manufacturing capacity of IDMs) it is not obvious how sustainable the model is. Wafer as a production unit is not sufficient anymore; foundries are being asked by large customers to price products in terms of good die. It brings back the notion of the old ASIC business model where the foundry is responsible for dealing with both random and systematic yield issues for a given design. One scenario of future development would be that some of the leading foundries might eventually transform themselves into IDMs. Another visible trend: some of the manufacturing capacities started to diversify business by providing services for new emerging markets (for example, new energy and medicine applications). Finally it is very unclear what’s going to happen to fabless players. We continue building on the "Think SPICE again!" methodology introduced last year and expanding on previous platforms' discussion. Model expression of DFM, most probably, will be supplied by the equipment suppliers and yield management community. Actual content for a design intent model will be provided by manufacturing. Much like SPICE it describes the behavior and not what the actual measurement in manufacturing is. When the model is available and populated, a design automation solution can be created that will allow a designer to extract, analyze, simulate, and optimize the circuit prior to handoff to manufacturing.

Until recently little has been done to formalize the concept of design for manufacturability (DFM) for integrated circuits. This is a complex problem that has been addressed from multiple angles with different degrees of success . While there can be certain operations which improve one manufacturability component, they can also adversely affect another. For this reason a framework that systematically addresses multiple manufacturability tradeoffs is required. This work proposes a pattern-centric DFM framework which emphasizes pattern robustness and introduces the concept of process variability bands (pv-Bands) to create a ranking system to measure the manufacturability of any design. The ranking system is composed of manufacturability indices, and their behavior is presented for different process nodes as well as across multiple processing layers (i.e. metal1, active, poly, etc). As an example of the necessity of such a framework, lithography-compliant rules are defined to suggest how other manufacturing processing steps need to be characterized in order to be successfully integrated in the framework. Examples of pinching (necking), bridging and CD control rules based on a pv-Band description are also discussed. In addition this work includes a description on how the process models derived from this study can be used to improve electrical analysis via a more accurate device description. As an example, timing-process-windows are defined as the link between design requirements and pattern manufacturability, and indicate why electrical models need to explicitly account for pattern induced effects at conditions other than nominal.

As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are be-coming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance ex-cursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or Process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM’s 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

The Geometry Verification System NGR2100 enables verification of the entire die, on a resist or an after-etch wafer, by comparing images of a die with corresponding target CAD data. The system detects systematic defects by variable criteria setting for allowable deformation quantities and obtains a CD distribution diagram. The result of systematic defects can then be used to make root cause analysis. The CD distribution diagram can achieve stepper aberration analysis, process windows extraction, macro-loading effect analysis, FEM measurement, and trend analysis more efficiently. Consequently, the Geometry Verification System NGR2100 will contribute to quicker TAT for DFM in Design, Lithography and Mask production.

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

Design tools should take manufacturing foibles into account, on this everyone agrees. But specifically, which DFM issues should IC design software take into account, and how should they be conveyed from the fab to the design tools? Here we examine an approach that expresses four of the most pressing DFM concerns - point defect densities, via yield, lithographic process windows, and cell yield - in a way design tools can easily understand. We show these data types can be combined, they can be read quickly, and that they allow designs to be analyzed (and potentially optimized) with speeds commensurate with other existing algorithms that run on large designs. The major concern that remains is getting useful DFM data from the manufacturing firms. Without this, for example, IC design tools cannot trade off one effect against another.

Dummy fill insertion in Chemical-mechanical Planarization (CMP) can change the coupling and total capacitance of interconnect. Moreover, dishing and erosion phenomena change interconnect cross-sections and hence significantly affect interconnect resistance. This work first studies interconnect parasitic variations due to (1) different fill patterns that are nominally "equivalent" with respect to foundry rules; and (2) dishing and erosion of conductors and dielectric using an accurate density-step-height model for multi-step CMP from the literature. Our results show that for long parallel wires the variation of coupling capacitance between adjacent wires can be up to 25% and 300% for wires that are 3x and 6x minimum space apart respectively, and the variation of total wire capacitance can be more than 10%. We also show that the variation of wire resistance due to dishing and erosion can be over 30%. This work also evaluates how CMP effects (fill insertion, dishing and erosion) impact the achievable delay of buffered global on-chip interconnects. We obtain the delay of buses from accurate SPICE simulations considering CMP-related parasitic variation. Our studies show that the interconnect design considering fill and buffer insertion simultaneously with CMP effects reduces the unit length delay of global interconnect bus by up to 3.3% over the design which does not consider any CMP effects.

A target of the 45nm node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge. Following the requirements of the ITRS Roadmap requires challenging k₁ values. A classical 6-transistor SRAM design is difficult to scale to lower k1 values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314μm² 45nm node 6-transistor SRAM cell. The design was scaled to a k₁ value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k₁ of 0.280 and a cell size of 0.274μm² for a working cell and imaging with a k₁ of 0.265 on a higher NA tool. Various resolution enhancement techniques have been used for the three most critical layers of the SRAM cell: active area, poly gates and contact holes. Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers. For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k₁ of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow. In this paper we show that all the above-mentioned resolution enhancement techniques have been successfully integrated and that it resulted in a working 45nm node SRAM cell.

Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in subwavelength lithography. As focus levels change during manufacturing, CDs at a given "legal" pitch can fail to achieve manufacturing tolerances required for adequate yield. Furthermore, adoption of off-axis illumination (OAI) and SRAF techniques to enhance resolution at minimum pitch worsens printability of patterns at other pitches. Our previous work [Gupta et al.] described a novel dynamic programming-based technique for Assist-Feature Correctness (AFCorr) to account for interactions within a cell row. We now extend the AFCorr methodology to handle vertical interactions of field polys between adjacent cell rows in the detailed placement of standard-cell designs. Pattern bridge between field poly geometries becomes a major reason for yield degradation even though CD variation of gates determines circuit performance. In this paper, AFCorr is validated in all possible horizontal (H-) and vertical (V-) interactions of polysilicon geometries in the layout. For benchmark designs, forbidden pitch count between polysilicon shapes of neighboring cells is reduced by 89%-100% in 130nm and 93%-100% in 90nm. Edge placement error (EPE) count is also reduced by 80%-98% in 130nm and 83%-100% in 90nm. AFCorr facilitates additional SRAF insertion by up to 7.4% for 130nm and 7.9% for 90nm. In addition, AFCorr provides substantial improvement in CD control with negligible timing, area, or CPU overhead. The advantages of AFCorr are expected to increase in future technology nodes.

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. Design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect.

Recently, "design for manufacturability" (DFM) has become a veritable buzzword in the semiconductor manufacturing community. DFM activities cover a broad spectrum ranging from the improvement of the electrical and structural robustness against process variations to the reduction of layout parts critical for statistically distributed defects or sensitive to systematic process weaknesses. In our work we focus only on those aspects of DFM concerned with the structural integrity of patterns on the wafer. We show that a purely geometrical analysis of product layouts offers a powerful tool to strengthen the link between design and manufacturing. It allows, for instance, a visualisation of the extent to which intra- and inter-layer design rules determine the geometry configurations dominating the layout and the identification of patterns occurring only rarely. Furthermore, in combination with the geometry-resolved information about the accuracy of "optical proximity correction" (OPC) models and "critical dimension" (CD) control, such an analysis provides valuable input for systematic improvements on both, the product layout and manufacturing process side. In this sense it supports the progress towards making real designs still manufacturable at the limits of process tool capabilities.

Quality of a layout has the most direct impact in the manufacturability of a design. Traditionally, layout quality is ensured in the first order by design rules, i.e. if a layout is free of design rules violation, it is a good layout. It is assumed such a layout will be fabricated to specification. Moreover, a design rule clean layout also ensures the electrical performance of the circuit it represents. There are other layout quality measures, e.g. random defects yield of a layout is modeled by critical area, systematic defects yield is sometime measured by a weighted score of recommended design rules. All the traditional layout quality measures are computed with drawn layout shapes. In the advent of low K1 lithography and the increasing variability of process technologies beyond 90nm, nominal layout quality measures need to be revisited. Traditionally, nominal electrical properties such as L-eff and W-eff are extracted from drawn layout, and the corner cases are estimated with worst case process conditions. Most of these parameters are layout pattern dependent. As a matter of fact, they can be systematic through process and can have large impact in the modeling of circuit parameters [1]. In this paper, we investigate a through process layout quality measure, in which we extract through process electrical parameters from simulated through process resist contours. We showed a mechanism to compute a statistical model that predicts through process electrical parameters from the process parameter variation. We demonstrated that such computation is practical.

Variability of digital integrated circuits is becoming an increasing concern with shrinking transistor geometries due to process scaling. As a result, the electrical properties of MOS devices can exhibit significant deviation from their design specifications, causing substantial variation in the performance of high-end designs. Lithography perturbations can affect a number of layout geometries, although the most critical parameter for circuit performance is the transistor channel length or Critical Dimension (CD). Key sources of CD variation include dose, focus, lens aberration and mask errors. In this paper, we compare the impact of above sources of CD variation on circuit performance. We present a new design analysis methodology which models the CD variation from each individual source in static timing analysis for different circuit blocks. Using this analysis capability, we study the impact of lithographic perturbations on block-level circuit performance for two adders. Furthermore, we study the correlation between the CD variability resulting from a lithographic perturbation source, and the resulting circuit performance variability. Through this analysis we determine the suitability of CD variability as an accurate predictor for circuit performance.

Pelgrom's model suggests that a spatial correlation structure is inherent in the physical properties of semiconductor devices; specifically, devices situated closely together will be subject to a higher degree of correlation than devices separated by larger distances. Since correlation of device gate length values caused by systematic variations in microlithographic processing is known to carry a significant impact on the variability of circuit performance, we attempt to extract and understand the nature of spatial correlation across an entire die. Based on exhaustive, full-wafer critical dimension measurements collected using electrical linewidth metrology for wafers processed in a standard 130nm lithography cell, we calculate a spatial correlation metric of gate length over a full-field range in both horizontal and vertical orientations. Using a rudimentary model fit to these results, we investigate the impact of correlation in the spatial distribution on the variability of circuit performance using a series of Monte Carlo analyses in HSPICE; it is confirmed that this correlation does indeed present a significant influence on performance variability. From the same dataset, we also extract both the across-wafer (AW) and within-field (WIF) contributions to systematic variation. We find that the spatial correlation model’s shape is strongly related to these two components of variation (both in magnitude as well as by spatial fingerprint). By artificially reducing each of these components of systematic variation-thereby simulating the effects of active, across-field process compensation-we show that spatial correlation is significantly reduced, nearly to zero. This implies that Pelgrom's model may not apply to die-scale separation distances, and that a more accurate correlation theory would combine Pelgrom's model over very short separation distances with a systematic variation model that captures variability over longer distances by means of non-stationary distributions.

For current and upcoming technology nodes (90, 65, 45 nm and beyond) one of the fundamental enablers of Moore's Law is the use of Resolution Enhancement Techniques (RET) in optical lithography. While RETs allow for continuing reduction in integrated circuits’ critical dimensions (CD), layout distortions are introduced as an undesired consequence due to proximity effects. Complex and costly Optical Proximity Correction (OPC) is then deployed to compensate for CD variations and loss of pattern fidelity, in an effort to improve yield. This, together with other sources for CD variations, causes the actual on-silicon chip performance to be quite different from sign-off expectations. In current design optimization methodologies, process variation modeling, aimed at providing guardbands for performance analysis, is based on "worst-case scenarios" (corner cases) and yields overly pessimistic simulation results which makes meeting design targets unnecessarily difficult. Assumptions of CD distributions in Monte Carlo simulations, and statistical timing analysis in general, can be made more rigorous by considering realistic systematic and random contributions to the overall process variation. A novel methodology is presented in this paper for extracting residual OPC errors from a placed and routed full chip layout and for deriving actual (i.e., calibrated to silicon) CD values, to be used in timing analysis and speed path characterization. The implementation of this automated flow is achieved through a combination of tagging critical gates, post-OPC layout back-annotation, and selective extraction from the global circuit netlist. This approach improves upon traditional design flow practices where ideal (i.e., drawn) CD values are employed, which leads to poor performance predictability of the as-fabricated design. With this more accurate timing analysis, we are able to highlight the necessity of a post-OPC verification embedded design flow by showing substantial differences in the silicon-based timing simulations, both in terms of a significant reordering of speed path criticality and a 36.4% increase in worst-case slack. Extensions of this methodology to multi-layer extraction and timing characterization are also proposed. The paper concludes by showing how the methodology implemented in this flow also provides a general design for manufacturability (DFM) tool template. In particular, by passing design intent to process/OPC engineers, selective OPC can be applied to improve CD variation control based on gates' functions such as critical gates and matching transistors. Furthermore, back-annotated process-based data can be used during early stages of circuit design verification and optimization, driving tradeoffs when significant variability is unavoidable.

In this paper we will describe the implementation of a system for model-based verification of post OPC data into a manufacturing data flow. Verification is run automatically, upon OPC completion, on the critical levels for every chip run in the 130nm node and beyond to ensure that OPC errors are caught before hardware is committed in the manufacturing line. The checks are derived from the design rule manual, and are written to cover the intent of the design rules. Some of the challenges of implementing a robust model-based verification solution for manufacturing will be discussed, including resource requirements, data management, cycle time, and the creation of a closed loop system to ensure that verification is completed on all chips. The benefits of implementing model-based verification include improved feedback to lithography and OPC teams, enabling constant improvement, as well as increasing the probability of first time right manufacturing of a new chip design.

There is a growing realization of the need for highly integrated solutions enabled by new bi-directional data 'pipes' between design and manufacturing. Traditional EDA applications should be able to communicate and collaborate with yield analysis software. Simply adding such capabilities to existing EDA applications is not feasible. Thus, there is a need for an infrastructure that would enable such interaction in a standard way. We call this infrastructure the DFM Platform. In this article we present new approach to building such a platform. Brief descriptions of potential applications follow the platform architecture. "Via analysis" application includes test chips capabilities, critical area and critical parameter analysis to predict yield for a real design. The "DFM Cell Grading" module applies the concept of DFM to IP Libraries.

Systematic design for manufacturability ( DfM ) scheme including triple gates for hot spot elimination under the low-k₁ lithography condition is proposed and efficient approaches to the hot spot elimination at each development stage in the DfM scheme are discussed in view of the actual situation under the concurrent development of design rule ( DR ), layout, process, optical proximity correction ( OPC ) and resolution enhancement technique ( RET ) technologies. Integrated-type lithography simulation system with OPC tool is much available for the fast processing at the initial stage and promising to be complementarily used for the verification of chip-level layout with conventional-type one at the final development stage. Low order of the lithography empirical model originating moderate prediction accuracy for all kinds of patterns is hopeful to be used at the initial development stage because it is difficult to obtain a lot of reliable experimental data for making the accurate empirical lithography model due to frequent improvement of the process, OPC and RET technologies. At the final development stage, sufficient and reliable experimental data for device pattern variations allow us to implement the higher order of the empirical model. The DfM scheme with efficient approaches in view of the actual situation under the concurrent development is found to be promising for the robust pattern formation under the low-k₁ lithography condition.

Immersion lithography at 193nm has emerged as the leading contender for critical patterning through the 32nm technology node. Super-high NA, along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control at intra-wafer and intra-field levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint DFM and APC strategies at the 65nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control.

This paper investigates variability across multiple lithographic domains, as experienced in typical manufacturing environments, and assesses the impact on achievable post-OPC image fidelity and CD control. Across scanner field and tool-tool effects are considered, and a distinction is made between systematic phenomena, which typically manifest within chip, and random fluctuations, which predominantly impact chip-to-chip mean distributions. The paper will outline which lithographic parameters can effectively be accounted for in OPC models, and over what temporal/spatial extents. The non-correctable phenomena assessed include misalignment, projection optic aberrations, illumination source profile, mask CD, focus and exposure dose variation, and flare. Specific analyses are applied to the case of gate edge placement error (EPE) control as a function of these manufacturing variables. Recommendations are made for "field-aware" metrology sample plans during model creation, such that globally optimized models can be realized. With knowledge of manufacturing input parameter variation, CalibreTM enables a detailed understanding of realistic post-OPC CD control, and can guide judicious product metrology sampling and specifications. It is highlighted that even for the case of a "perfect" OPC model, the post-OPC CD variation within chip can still be substantial, due to manufacturing variability.

Model-based optical proximity correction (OPC) calculates pattern adjustments by simulating the layout with calibrated lithography and process models. OPC can only correct systematic lithography deviations, those error components that repeat chip to chip. OPC cannot compensate random deviation error components from unpredictable process variations, such as defocus and dose. However the ranges of variation from random effects is predictable, and OPC can optimize correction shapes to minimize this range where possible. Current techniques for supporting this optimization involve applying a set of models covering the range of expected process variations in defocus and exposure. Variation is assessed by comparing process corner-point model evaluations. Because there is a significant runtime cost simulating multiple process conditions, most production OPC jobs use a single, representative model (typically the "nominal" process condition) aided with rules and other heuristics to help handle process window effects. In this paper the application of a new type of model that can be used to predict process variation with a single simulation call. The model involved in these studies targets pattern behavior as the focus offset deviates from the nominal focus setting. Used in conjunction with a nominal process model, this model can support process-window optimized OPC without the need for multiple models at various defocus settings. This model can also be used by itself to assess the defocus robustness of any configuration before or after OPC, thereby supporting efficient model-based layout verification.

At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

Perhaps the most critical lithographic challenge at teh 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k₁ imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such annular and Quasar. At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Moreover, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.

As the semiconductor industry goes into the 65nm generation, designs become more complex, mask cost increases exponentially, and the industry is pushing very hard on the lithography process. It is more and more challenging to achieve and maintain acceptable yield. Yield is not only a problem for the Fabs but also an issue that has to be considered by the chip designers. In order to save turn around time, save mask and process development cost and improve the yield, the lithography problems need to be resolved at the design stage. The designers need to be aware of the lithography behavior of their design and be able to modify the design if it causes yield problems in the lithography process. In this paper, we discuss a new tool, a Litho Yield Checker, which can be run stand-alone but is also fully integrated with a Layout Editor, that provides its user with an easy way to visualize how the layouts are to be printed on wafer, and see the common process window (CPW) for the most important locations in the design.

As lithography continues to increase in difficulty with low k1 factors, and ever-tighter process margins, model-based optical proximity correction (OPC) is being used for the majority of patterning layers. As a result, the engineering effort consumed by the development and calibration of OPC models is continuing to increase at an alarming rate. One of the major focal points of this effort is the increasing emphasis on improving the accuracy of the model-based OPC corrections. One of the major contributors to final OPC accuracy is the quality of the resist model. As a result of these trends, the number of sample points used to calibrate OPC models is increasing rapidly from generation to generation. However, this increase is largely due to an antiquated approach to the construction of these calibration sets, focusing on structure variations. In this study, a new approach to the calibration of a resist model will be proposed based upon the location of calibration structures within the actual resist space over which the resist model is expected to be predictive.

Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because of the designer’s lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.

Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.

Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs. In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test maks design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance. We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution ehancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.

As the industry moves to 90nm and below, the size of our process windows are rapidly decreasing. The process window is often not considered during optical proximity correction (OPC) which must match the printed wafer to the original design target for a single process point. This process point is usually at 'best exposure' and 'best defocus'. The results can be verified under different defocus conditions but it is generally assumed that the printed pattern will yield well for a range of defocus and exposure conditions. At 90nm or smaller this assumption is breaking down as the final yield of products is greatly reduced due to low pattern quality under even relatively small process variations. Instead of optimizing the OPC results using a single model a multi-model approach is proposed where the pattern is optimized using two or more process points. The final printed image is optimized to both minimize the overall CD variations across a process as well as centering this variation with respect to the original target edges in CD critical areas. To maximize the benefits of this technique we also provide more freedom to OPC by making use of design intent to vary the print requirement in different areas of the design. In this paper we describe the process centering methodology and its use of design intent. To evaluate the benefits of this technique a metric is also proposed and used to quantify experimental results. Results are compared with those of a traditional OPC flow.

The shrinking of the dimensions for each new process generation increases the challenges for lithography significantly. In order to guarantee manufacturability for future process generations, a strong interaction between lithography and design is required. A quantitative measure for the manufacturability is of key importance for driving the improvements in the design for manufacturing process. Aerial image slopes or contrasts in simulated images provide a measure for the sensitivity to process variations, but do not take the statistical process variation into account. This may result in sub-optimal choices in the design for manufacturing process. This paper discusses the process capability analysis and provides an optimal design with corresponding imaging conditions, taking the statistical fluctuations of exposure dose and focus into account. The mean CD value and the CD spread are calculated as a function of the amount of variation in the process variables like focus and exposure dose. Comparing these distribution parameters to the process specifications yields the so-called process capability index as a quantitative measure for the manufacturability. Another advantage is the possibility to include the effect of mask errors on the manufacturability. Until now, however, this method had only been demonstrated for line space features. In this paper we extend the process capability analysis method for calculating the manufacturability of arbitrary layouts. The analysis is demonstrated in an evaluation of the manufacturability of various gate layer designs, both conventional as well as litho-driven re-designs.

The drive of the semiconductor industry towards smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making. The wavelength gap in lithography and process effects as well as dependencies on the design content have led to the tremendous variety of resolution enhancement techniques and process correction approaches that are currently applied to a design on its path to manufacturing. As the 65nm nodes become production ready and the 45nm node shifts into the focus of the development effects like flare in wafer exposure, fogging effects in ebeam mask exposure and others that previously could be ignored are becoming significant so that their correction prior to manufacturing is required. That means additional correction steps are necessary to complete the data preparation. These put a larger burden on the data processing path and raise concerns over data volume and processing time limitations. Hierarchical processing methods have proven very effective in the past to keep data volumes and processing time in control. The paper explores the design trends and the potential of hierarchical processing under the new circumstances. Extended data flows with a variety of correction steps are investigated. Experimental results that demonstrate the benefit of hierarchical methods in conjunction with parallel processing methods like multithreading and distributed processing are provided. The benefit of introducing more effective data formats like OASIS in these flows will be illustrated.

Design tools exploit design hierarchy for speed, efficiency and reuse. Conventional OPC solutions, however, do not fully exploit such structures and hence are not very efficient. Since a cell may be instantiated thousands of times in a design, this implies that redundant OPC operations are usually applied, at the cell instance level, repeatedly to the same master cell within the context of the design. Some cell-based OPC studies have been performed in an attempt to alleviate such inefficiency. For example, Gupta, Heng and Lavin have shown that a simple cell-based (book-based) OPC approach has negligible OPC imperfectness around cell boundaries but has an average P/D speed-up, where P is the number of master placement cells and D is the number of master cells. This article presents an alternative approach to the above mentioned works. Here, we illustrate that it is not only possible to apply OPC on a per-cell basis, but also to "stitch" already corrected cells along their interacting areas together to form a proximity corrected final layout. Because of the stitching steps, our approach can handle more practical and complicated hierarchical layouts than those described in Gupta et al. and achieve OPC quality equivalent to that obtained using conventional OPC methods. In addition, since our approach performs the majority of OPC work at the cell level, we can maintain the runtime savings comparable to that demonstrated by Gupta et al. This technique of localized OPC reconfiguration can be extended to handle applications such as manufacturing ECO handling and design re-spins.

The X Architecture offers the potential to produce smaller and faster integrated circuits through the pervasive use of 45° wirings on the upper metal layers. The X Initiative members have demonstrated its manufacturability and integration-worthiness at the 130nm, 90nm and 65nm process technology nodes. This paper explores the use of off-axis lithography illumination to print 45° diagonal wires at leading technology nodes. The paper also describes the RET strategies employed for the X Architecture and the effectiveness of various illumination sources at various process nodes. Process window and metal wiring CD variation of Manhattan and X Architecture are compared in the simulations using different types of illuminators. Simulation shows that using 193nm light source, Manhattan and X designs can easily be printed with different types of illuminating source in either 90nm or 65nm process node. Silicon test chips at 90nm that include typical X routing patterns are designed to verify the printability of X Architecture wirings. Electrical measurements as well as SEM analysis are conducted and results show that the fidelity of diagonal wirings is as good as traditional Manhattan routings.

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples: -design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. -Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

The relentless pursuit of Moore's Law is pushing lithographical equipment to its limits. Extensive use of Resolution Enhancement Technologies (RET) during mask synthesis has allowed the industry to meet demand for density and performance at the 0.13um node and below. RET has been used to sustain the traditional model of printing edges as close as possible to the corresponding edges in the design layout. As technology moves to sub-100nm processes this model is proving to be both challenging and expensive to sustain. Pushing the RET tools to do an aggressive match between layout geometries and the printed pattern results in a large increase in mask cost. Even if this optimization is successful the resulting pattern may not provide the highest possible yield. In previous papers we demonstrated the use of design intent (DI) during mask synthesis to both reduce mask cost and improve yield. In this paper more results are described of how much improvement is possible on mask shot count and sliver count. We also investigate the cell level timing impact of our proposed methodology. Detailed timing results are presented and analyzed along with their impact on the design flow.

In this paper, a technique for full chip gate CD(critical dimension) error prediction based on empirical models will be presented and discussed. In order to be compatible with existing common terminologies, this technique can also be called model-based full chip gate CD verification, which has become an integral part of closed-loop design-to-silicon flow of gate layer masking processes at 90nm and 65nm technology nodes. The empirical optical-and-process models can be same or different (such as with defocus) from the ones which are widely used in model based OPC and ORC. Similar to but different from conventional ORC, which normally addresses the minimum feature check or fatal error check, the model-based gate CD verification technique will focus on CD error prediction and CD error distribution analysis for gate CD related yield improvement efforts. Current commercial ORC or model-based verification tools provide the capability of EPE (edge placement error) check and analysis, and with certain additional techniques they may also provide the capability of gate CD prediction or simulation for selected targets or figures. The new model-based gate CD verification technique will provide the capability of full chip CD error prediction and CD error distribution analysis for all concerned small gate CD targets.

This paper focuses on reticle/field placement methodology issues, the disadvantages of typical methods used in the industry, and the innovative way that the WAMA software solution achieves optimized placement. Typical wafer placement methodologies used in the semiconductor industry considers a very limited number of parameters, like placing the maximum amount of die on the wafer circle and manually modifying die placement to minimize edge yield degradation. This paper describes how WAMA software takes into account process characteristics, manufacturing constraints and business objectives to optimize placement for maximum stepper productivity and maximum good die (yield) on the wafer.

Semiconductor foundries need to have a single, standard mask preparation procedure to deal with the large number of designs they receive. This data is typically of two sorts; the random logic over which they have little control of how the design intent is represented; and cells from dense arrays such as memory, often with design rule violations, whose OPC correction needs to be precisely optimized to achieve best yield and device performance. Occasionally the input data will contain sub-resolvable notches and extensions, which while not violating DRC specifications, would, if filled, result in DRC violations. This may be due to a non DFM aware automated layout tool, or a designer aggressively trying to minimize circuit density. In practice it is worthwhile to clean up these notches to ease OPC correction. Doing this should not result in printability errors as these notches typically represent a more complex curved design intent that cannot be accurately represented due to the restrictions imposed by the limited number of polygon edge directions available for layout. Similarly, memory cell layouts often have significant implied curvature. These may only be corrected properly if the OPC target point is defined precisely for each individual segment. In general, letting the OPC correction engine correct a layout defined by a realistic, curved target shape gives better quality corrections with greater process window. The challenge for the OPC engineer working in a foundry is therefore to determine a clean-up methodology for incoming data and to correctly apply the design intent, where necessary, from the original pre-cleanup data. A programmable OPC engine gives the user flexibility in optimizing the set of rules embedded in the OPC cleanup and correction recipes. These embed within them the algorithms to interpret the rounding on the desired silicon image not only for line-ends and corners of random logic but also the more complex curved silicon images and tolerances required by memory cells.

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. Process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive Design-for-Manufacturing (DFM) flow. Process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

It has been published that there is potential benefit to utilizing an OPC model based upon defocus instead of best focus processing, to give more robust patterning. While this is true with respect to gross opens and bridging problems, the available CD budget and the anticipated manufacturing consumption of defocus budgets must be considered. The net result will almost certainly always be that for gate layer processing, defocus model based OPC is not desirable. For other layers there may be favorable yield implications to running in such a manner, but the average CD in manufacturing will deviate from the design target. This paper will explore the interplay between variable focus distributions in manufacturing and the required CD control, pointing to those conditions under which a defocus model is advisable, and where it is not. Furthermore, the optimum magnitude of defocus is a compromise and has implications for final electrical performance.