After more than 2 years of development, Design-Driven Metrology (DDM) is now being introduced into production flows for semiconductor manufacturing, with initial applications targeted at 65 nm and below, but also backward-compatible to 90 nm and above nodes. This paper presents the fundamental components of the DDM framework, and the characteristic architectural relationships among these elements. The discussion includes current status and future prospects for this new metrology paradigm, which represents the true enabler for Design For Manufacturability (DFM) flows and applications. At the core of Design-Driven Metrology lies the simple but powerful concept of utilizing physical design layouts, and more specifically (X,Y) coordinates and polygonal shapes, to automate the generation of metrology jobs. Derived from 10 year old practices of Optical Proximity Correction, the adoption of CAD tools for visualization and manipulation of design layouts, in everyday lithography work, has provided the essential infrastructure for metrology automation. The in-depth discussion of data-flow and system architecture is followed by a presentation of key DDM applications, with specific emphasis on CDSEM metrology, ranging from process development and yield optimization to circuit design. The study concludes with an analysis of the extendibility of DDM and derived flows to other metrology areas in semiconductor manufacturing.

Optimal Proximity Correction (OPC) models are calibrated with Scanning Electron Microscope (SEM) data where the measurement uncertainty vary among pattern types (i.e., line versus space, 1D versus 2D and small versus large). The quality of the SEM measurement uncertainty's impact on OPC model integrity is mitigated through a weighting scheme. Statistical methods such as relating the weight to the SEM measurements standard deviation require more measurements per calibration structure than economically feasible. Similarly, the use of experience and engineering judgment requires many iterations before some reasonable weighting scale is determined. In this paper we present the results of OPC model fitness statistics associated with metrology based weights (MtBW) versus model based weights (MBW). The motivation for the latter approach is the promise for an unbiased, consistent, and efficient estimate of the model parameters.

As described by the ITRS roadmap [1], introduction of next generation processes in semiconductor fabrication continually requires tighter control in order to insure optimal device characteristics. Recent process development has shown an increased amount of charged layers, which in turn affects the inline critical dimension scanning electron microscope's (CD-SEM) ability to generate quality measurements thereby impacting process control. This paper reports on the investigation of techniques to measure and compensate for this charge dynamically to yield quality measurements. New capabilities of the CD-SEM were evaluated and tested at various process steps including processing steps not measured by the CD SEM. This capability not only means the CD-SEMs are essentially immune to charged layer affects but the capability can also be used to feedback to other tool-sets suspected of causing the charge build-up. These charge measurements help provide an understanding on how the device performance might be impacted. In order to establish charged wafer monitoring in the future along with feedback loops, studies of the reproducibility and the persistency of the charge across sequential processes in the back-end layers have been made. Studies were also conducted to determine the origin of the charge by observing the distribution before and after known problematic process steps.

How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.

Comprehensive CD characterization of low-k trench etch for 65nm nodes are performed through a specially designed mask with global pattern density (GPD) in the range from 25% to 60%. Unlike traditional means, through this mask we systematically demonstrate global pattern density effects on etch behaviors in correlation with CD uniformity, CD proximity, and CD linearity without local etch loading effect contributed from nearby environment [1-3] and position dependent effect contributed from resist developing or aberrations of the wafer-imaging lens [4]. From our study, CD proximity is the most sensitive item. Wider trench shows larger CD variation as compared with narrow trench when global environment vary. Moreover, we find that low pressure etch conditions in a small chamber volume etcher exhibits less CD variation of global pattern density effect. On the other hand, pressure in a large chamber volume etcher provides better tuning capability in the adjustment of CD variation. The results suggest that residence time might be an influential factor for the GPD dependent CD control.

Without the ability to detect potential yield-limiting defects in-line, the yield learning cycle is severely crippled, compromising the financial success of chip makers. As design rules shrink, device yield is seriously affected by smaller size particle and patterned defects that were not important in the past. These mechanisms are becoming more difficult to detect with current defect detection tools and techniques. The optical defect inspection tools that are currently available do not adequately detect defects, while scanning electron microscope (SEM) based inspection tools are too slow. With each successive technology node, optical inspection becomes less capable relative to the previous technology. As sensitivity is increased to detect smaller defects, the nuisance defect rate increases commensurately. Line-edge roughness (LER) and subtle process variations are making it more difficult to detect defects of interest (DOI). Smaller defects mean smaller samples available for energy dispersive x-ray analysis (EDX), necessitating an improved or new methodology for elemental analysis. This paper reviews these and some other challenges facing defect metrology at the 45nm technology node and beyond. The challenges in areas of patterned and unpatterned wafer inspection, defect review, and defect characterization are outlined along with proposed solutions. It also provides an overview of several ongoing projects conducted at International SEMATECH Manufacturing Initiative (ISMI) to address these challenges.

In order to stay competitive in the rapidly advancing international semiconductor industry, a manufacturing company needs to continually focus on several areas including rapid yield learning, manufacturing cost, statistical process control limits, process yield, equipment availability, cycle time, turns per direct labor hour, customer on time delivery and zero customer defects. To hold a competitive position in the semiconductor market, performance to these measurable factors mut be maintained regardless of the technology generation. In this presentation, the methodology applied by Freescale Semiconductor to achieve the fastest yield learning curve in the industry, as cited by Dr. Robert Leachman of UC Berkley in 2003, will be discussed.

Electrical failure due to incomplete contacts or vias has arisen as one of the primary modes of yield loss for 130 nm and below designs in manufacturing. Such failures are generally understood to arise from both random and systematic sources. The addition of redundant vias, where possible, has long been an accepted DFM practice for mitigating the impact of random defects. Incomplete vias are often characterized by having a diameter near the target dimension but a depth of less than 100% of target. As such, it is a difficult problem to diagnose and debug in-line, since bright and dark field optical inspection systems cannot typically distinguish between a closed, partially open and fully open contact. Advanced metrology systems have emerged in recent years to meet this challenge, but no perfect manufacturing solution has yet been identified for full field verification of all contacts. Voltage Contrast (VC) SEM metrology biases the wafer to directly measure electrical conductivity after fill / polish, and can therefore easily discern a lack of electrical connection to the underlying conductor caused by incomplete photo, etch, or fill processing. While an entire wafer can in principal be VC scanned, throughput limitations dictate very sparse sampling in manufacturing. SEM profile grading (PG) leverages the rich content of the secondary electron waveform to decipher information about the bottom of the contact. Several authors have demonstrated an excellent response of the Profile Grade to intentional defocus vectors. However, the SEM can only target discreet or single digit groupings of contacts, and therefore requires intelligent guidance to identify those contacts which are most prone to failure, enabling protection of the fab WIP. An a-priori knowledge of which specific contacts in a layout are most likely to fail would prove very useful for proactive inspection in manufacturing. Model based pre-manufacturing verification allows for such knowledge to be communicated to manufacturing. This paper will focus on 130 nm node contact patterning, and will correlate SEM Profile Grade output to the extensive suite of model-based image tags from the Calibre^TM opc-verification engine. With an understanding of which image parameters are most highly correlated to the occurrence of incomplete contact formation for a given process, the process model can be used to automatically direct inspection metrology to those layout instances that pose the highest risk of patterning failure through the lithographic process window. Such an approach maximizes the value content of in-line metrology.

Missing via has been a very annoying defect in semiconductor manufacture especially to foundry. Its solution can be rather attractive in yield improvement for relatively mature technology since each percentage point improvement will mean significant profit margin enhancement. However, the root cause for the missing via defect is not easy find since many factors, such as, defocus, material re-deposition, and inadequate developing can lead to missing via defects. Therefore, being able to know the exact cause for each defect type is the key to the solution of the problem. In this paper, we will present the analysis methodology used in our company. In the experiments, we have observed three types of missing vias. The first type consists of large areas, usually circular, of missing patterns, which are primarily located near wafer edge. The second type consists of isolated sites with single partially opened vias or completely unopened vias. The third type consists of relatively small circular areas, within which the entire via pattern is missing. We have first tried the optimization of the developing recipe and found that the first type missing via can be largely removed through the tuning of the rinse process, which improves the cleaning efficiency of the developing residue. However, this method does not remove the missing via of the second type, or the third type. For the second type missing via, we have found that it is related to local defocus caused by topographical distribution. To resolve the third type missing via defects, we have performed extensive experiments with different types of developer nozzles and different types of photomasks and the result is that we have not found any distinct dependence of the defect density to either the nozzle and mask types. Besides, we have also studied the defect density from three resists with different resolution capability and we found a correlation between the defect density and the resist resolution. It seems that, in general, lower resolution resist also has lower defect density and the results will be presented in the paper.

Design Based Metrology (DBM) implements a novel automation flow, which allows for a direct and traceable correspondence to be established between selected locations in product designs and matching metrology locations on silicon wafers. Thus DBM constitutes the fundamental enabler of Design For Manufacturability (DFM), because of its intrinsic ability to characterize and quantify the discrepancy between design layout intent and actual patterns on silicon. The evolution of the CDSEM into a DFM tool, capable of measuring thousands of unique sites, includes 3 essential functionalities: (1) seamless integration with design layout and locations coordinate system; (2) new design-based pattern recognition and (3) fully automated recipe generation. Additionally advanced SEM metrology algorithms are required for complex 2-dimensional features, Line-Edge-Roughness (LER), etc. In this paper, we consider the overall DBM flow, its integration with traditional CDSEM metrology and the state-of-the-art in recipe automation success. We also investigate advanced DFM applications, specifically enabled by DBM, particularly for OPC model calibration and verification, design-driven RET development and parametric Design Rule evaluation and selection.

There are numerous metrology challenges facing photolithography for the 45 nm technology node and beyond in the areas of critical dimension (CD), overlay and defect metrology. Many of these challenges are identified in the 2005 International Technology Roadmap for Semiconductors (ITRS) [1]. The Lithography and Metrology sections of the ITRS call for measurement of 45/32/22/18 nm generation linewidth and overlay. Each subsequent technology generation requires less variation in CD linewidth and overlay control, which results in a continuing need for improved metrology precision. In addition, there is an increasing need to understand individual edge variation and edge placement errors relative to the intended design. This is accelerating the need for new methods of CD and overlay measurement, as well as new target structures. This paper will provide a comprehensive overview of the CD and overlay metrology challenges for photolithography, taking into account the areas addressed in the 2005 ITRS for the 45 nm technology generation and beyond.

A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

In this paper, we present a study on the robustness comparison of several process feedbacks controllers. The feedbacks include those based on either EWMA or Kalman Filter estimation. In addition, a new multiple dimension feedback controller is introduced, which has a significantly improved robust stability and reduced sensitivity to unknown noise. In the robustness study, we assume model mismatch and unknown disturbances. Two issues of robustness are addressed in this paper, namely the region of model mismatch in which a process feedback is stable; and the H-infinity gain of the controlled process from unknown noise to the system performance. Simulations are shown to compare the performance of the feedbacks under model mismatch, system drifting, and random noise.

For several years, integrated scatterometry has held the promise of wafer-level process control. While integrated scatterometry on lithography systems is being used in manufacturing, production implementation on etch systems is just beginning to occur. Because gate patterning is so important to yield, gate linewidth control is viewed by many as the most critical application for integrated scatterometry on etch systems. IBM has implemented integrated scatterometry on its polysilicon gate etch systems to control gate linewidth for its 90 nm node SOI-based microprocessors in its 300 mm manufacturing facility. This paper shows the performance of the scatterometry system and the equipment-based APC system used to control the etch process. Some of the APC methodology is described, as well as sampling strategies, throughput considerations, and scatterometry models. Results reveal that the scatterometry measurements correlate well to CD-SEM measurements before and after etch, and also correlate to electrical measurements. Finally, the improvement in linewidth distribution following the implementation of feedforward and feedback control in full manufacturing is shown.

Downscaling of microchip production technology continually increases requirements to precision of process control, and demands improvement of critical dimension (CD) measurement and control tools. In this paper we discuss the application of in situ method of critical dimension measurement for improvement of photomask development process. For this purpose scatterometry and fitting methods are applied to the CD end point detector system (CD EPD). The CD EPD system is different from the commonly used EPD system, which mainly detects the thickness of remaining resist. Measurement can be performed directly during development process, thus there is an advantage of measurement time decreasing in comparison with the ex situ method. In situ method allows one to control development precisely, and gives possibility to meet the requirements of process control. For the application of scatterometry to the CD measurement, diffraction analysis is carried out by using of rigorous coupled wave analysis (RCWA). We calculate the library of reflected spectra with various CD and heights of the pattern. These spectra are used for fitting with an experimentally measured one to get the CD and height. To increase precision and speed of measurements interpolation of spectra and various fitting methods are used.

Scatterometry is gaining popularity in recent years as it shows itself as a worthy contender among existing metrology systems. Scatterometry provides fast, accurate and precise profile information, which is valuable for in-line process control in production environment. Scatterometry applications widely adopted in IC fabs include poly gate ADI and AEI, and shallow trench isolation depth measurements. Recently, the mobility enhancement by compressive strain at source/drain is reported which improves greatly PMOS Idsat. In this work, we extend the application domain of scatterometry technology to two-dimensional recessed Si profile used in strained source and drain (SSD) structures. Complexity of SSD structures measurement by scatterometry requires the use of many parameters in modeling, which hinders a stable library setup. Our approach in circumventing this issue is to identify the most sensitive parameters first and then further reduce the number of variables through an effective medium approximation (EMA). This paper will discuss the preparation, experiments, and results of the scatterometry measurements. The extracted data have been compared with transmission electron microscopy results. Good correlation in depth and profile are observed. In addition, we have performed repeatability test and fault detection checks and the trend chart indicates that our methodology is very robust for in-line process monitor.

The resolution of an optical microscope is limited by the optical wavelengths used. However, there is no fundamental limit to the sensitivity of a microscope to small differences in any of a feature's dimensions. That is, those limits are determined by such things as the sensitivity of the detector array, the quality of the optical system, and the stability of the light source. The potential for using this nearly unbounded sensitivity has sparked interest in extending optical microscopy to the characterization of sub-wavelength structures created by photolithography and using that characterization for process control. In this paper, an analysis of the imaging of a semiconductor grating structure with an optical microscope will be presented. The analysis includes the effects of partial coherence in the illumination system, aberrations of both the illumination and the collection optics, non-uniformities in the illumination, and polarization. It can thus model just about any illumination configuration imaginable, including Koehler illumination, focused (confocal) illumination, or dark-field illumination. By propagating Jones matrices throughout the system, polarization control at the back focal planes of both illumination and collection can be investigated. Given a detailed characterization of the microscope (including aberrations), images can be calculated and compared to real data, allowing details of the grating structure to be determined, in a manner similar to that found in scatterometry.

We have implemented back focal plane (conoscopic) imaging in an optical microscope that has also been modified to allow selection of the illumination angles and polarization at the sample, and collected back focal plane images of silicon on silicon grating scatterometry targets with varying line widths. Using a slit illumination mask, the zero-order diffraction versus angle for −60° to +60° incident angles at a given polarization was obtained from a single image. By using reference images taken on a flat silicon background, we correct the raw target images for illumination source inhomogeneities and polarization-dependent transmission of the optics, and convert them to reflectance versus angle data for s- and p-polarizations, similar to that obtained from angle-resolved grating scatterometry. As with conventional scatterometry, the target lines need not be resolved for the reflectance signature to show sensitivity to small changes in the grating parameters. For a series of 300 nm pitch targets with line widths from 150 nm to 157 nm, we demonstrate nanometer-level sensitivity to line width with good repeatability, using 546 nm illumination. Additionally, we demonstrate a technique for separating the zero order from higher order diffraction on targets with multiple diffraction orders, allowing collection of both zero and higher order diffraction versus angle from the back focal plane image. As conventional images can be easily collected on the same microscope, the method provides a powerful tool for combining imaging metrology with scatterometry for optical critical dimension measurements in semiconductors.

In this paper we present a unique method of evaluating the angular illumination homogeneity in an optical microscope using the through-focus focus metric. A plot of the sum of the mean square slope throughout an optical image as the target moves through the focus is defined as the through-focus focus metric. Using optical simulations we show that the angular illumination inhomogeneity causes the through-focus focus metric value to proportionately increase at specific focus positions. Based on this observation, we present an experimental method to measure angular illumination homogeneity by evaluating the through-focus focus metric values on a grid across the field of view. Using the same through-focus focus metric, we present a detailed study to measure critical dimensions with nanometer sensitivity with the aid of simulations.

In our work we discuss two approaches of offline CD-SEM recipe creation for both OPC qualification wafers and the introduction of new products to the manufacturing line using the Applied Materials OPC Check and Offline Recipe Editor (ORE) applications. We evaluate the stability of the offline created recipes against process variations for different OPC test layouts as well as for production measurements on multiple lots per week and compare the results to the performance of recipes created directly on the tool. Further, the success rate of recipe creation is evaluated. All offline recipes have been generated in advance of wafer availability using GDS data. The offline created recipes have shown pattern recognition success rates of up to 98% and measurement success rates of up to 99% for line/space as well as for contact-hole (CH) measurements without manual assists during measurement. These success rates are in the same order of magnitude as the rates typically reached by an experienced CD-SEM engineer creating the recipes directly on the tool.

Interference microscopes are a widely used tool in many parts of production processes where exact information about surfaces is needed. Users appreciate the high accuracy and resolution but often ignore the possible errors which cannot be neglected in high precision metrology. Besides the measurement result, the uncertainty is the most important information necessary to evaluate the quality of a measurement. At the moment standardized calibration strategies for interference microscopes are missing. In order to receive comparable results, standardized information about the uncertainty is needed. Thus, models for the determination of the uncertainty of interference microscopes have to be developed. Therefore a simulation environment is being created, which is able to simulate all processes occurring inside interference microscopes. In particular, influences of real environments like laboratories or production processes are important. Furthermore user induced influences are considered. With the tool, based on a ray tracing procedure, systematic variations of the disturbing influences are possible and the consequences on the interferogram and the measurement result can be simulated and analyzed. Hence it is possible to manage the error influences of these complex systems as well as the generation of and an uncertainty budget. The findings help to set up process orientated calibration strategies for interference microscopes to improve the comparability und the traceability of measurements.

We are developing a transmission X-ray scattering platform capable of measuring the average cross section and line edge roughness in patterns ranging from 10 nm to 500 nm in width with sub-nm precision. Critical Dimension Small Angle X-ray Scattering (CD-SAXS) measures the diffraction of a collimated X-ray beam with sub-Angstrom wavelength from a repeating pattern, such as those in light scatterometry targets, to determine the pattern periodicity, line width, line height, and sidewall angle. Here, we present results from CD-SAXS with an emphasis on line edge roughness characterization. Line edge roughness measurements from CD-SAXS are compared with top-down scanning electron microscopy values and comparative definitions are discussed.

The National Institute of Standards and Technology (NIST) and SEMATECH are working to address traceability issues in semiconductor dimensional metrology. In semiconductor manufacturing, many of the measurements made in the fab are not traceable to the SI definition of the meter. This is because a greater emphasis is often placed on precision and tool matching than accuracy. Furthermore, the fast pace of development in the industry makes it difficult to introduce suitable traceable standard artifacts in a timely manner. To address this issue, NIST and SEMATECH implemented a critical dimension atomic force microscope (CD-AFM)-based reference measurement system (RMS). The system is calibrated for height, pitch, and width and has traceability to the SI definition of length in all three axes. Because the RMS is expected to function at a higher level of performance than inline tools, the level of characterization and handling of uncertainty sources is on a level usually seen for instruments at national measurement institutes. We have implemented a performance monitoring system to help us check the long-term stability of the calibrations. In this paper, we discuss progress in improving the uncertainty of the instrument and the details of our performance monitoring. We also present a method for accounting for some of the uncertainty due to the higher order tip effects.

The National Institute of Standards and Technology (NIST) has a multifaceted program in atomic force microscope (AFM) dimensional metrology. There are two major instruments being used for traceable AFM measurements at NIST. The first is a custom in-house metrology AFM, called the calibrated AFM (C-AFM), and the second instrument is a commercial critical dimension AFM (CD-AFM). The C-AFM has displacement metrology for all three axes traceable to the 633 nm wavelength of the Iodine-stabilized He-Ne laser. In the current generation of this system, the relative standard uncertainty of pitch and step height measurements is approximately 1.0 x 10^-3 for pitches at the micrometer scale and step heights at the 100 nm scale, as supported by several international comparisons. We expect to surpass this performance level soon. Since the CD-AFM has the capability of measuring vertical sidewalls, it complements the C-AFM. Although it does not have intrinsic traceability, it can be calibrated using standards measured on other instruments - such as the C-AFM, and we have developed uncertainty budgets for pitch, height, and linewidth measurements using this instrument. We use the CD-AFM primarily for linewidth measurements of near-vertical structures. At present, the relative standard uncertainties are approximately 0.2% for pitch measurements and 0.4% for step height measurements. As a result of the NIST single crystal critical dimension reference material (SCCDRM) project, it is possible to calibrate CD-AFM tip width with a 1 nm standard uncertainty. We are now using the CD-AFM to support the next generation of the SCCDRM project. In prototypes, we have observed features with widths as low as 20 nm and having uniformity at the 1 nm level.

The need for absolute accuracy is increasing as semiconductor-manufacturing technologies advance to sub-65nm nodes, since device sizes are reducing to sub-50nm but offsets ranging from 5nm to 20nm are often encountered. While TEM is well-recognized as the most accurate CD metrology, direct comparison between the TEM data and in-line CD data might be misleading sometimes due to different statistical sampling and interferences from sidewall roughness. In this work we explore the capability of CD-AFM as an accurate in-line CD reference metrology. Being a member of scanning profiling metrology, CD-AFM has the advantages of avoiding e-beam damage and minimum sample damage induced CD changes, in addition to the capability of more statistical sampling than typical cross section metrologies. While AFM has already gained its reputation on the accuracy of depth measurement, not much data was reported on the accuracy of CD-AFM for CD measurement. Our main focus here is to prove the accuracy of CD-AFM and show its measuring capability for semiconductor related materials and patterns. In addition to the typical precision check, we spent an intensive effort on examining the bias performance of this CD metrology, which is defined as the difference between CD-AFM data and the best-known CD value of the prepared samples. We first examine line edge roughness (LER) behavior for line patterns of various materials, including polysilicon, photoresist, and a porous low k material. Based on the LER characteristics of each patterning, a method is proposed to reduce its influence on CD measurement. Application of our method to a VLSI nanoCD standard is then performed, and agreement of less than 1nm bias is achieved between the CD-AFM data and the standard's value. With very careful sample preparations and TEM tool calibration, we also obtained excellent correlation between CD-AFM and TEM for poly-CDs ranging from 70nm to 400nm. CD measurements of poly ADI and low k trenches are also reported, and both show good correlation to in-line CD-SEM results.

We fabricate three kinds of carbon nanotube (CNT) probes to be employed in critical dimension atomic force microscope (CD-AFM). Despite unique advantages in its size and hardness, use of nanotube tip has been limited due to the lack of reproducible control of CNT orientation and its shape. We proposed that CNT alignment issues can be addressed based on the ion beam bending process, where a CNT free-standing on the apex of an AFM tip aligns itself in parallel to the FIB direction so that its free end is directed toward the ion source, with no external electric or magnetic field involved. The process allowed us to embody cylindrical probes of CNT diameters, and subsequently two additional types of CNT tips. One is ball-ended CNT tip which has, at the end of CNT tip, side-protrusions of tungsten/amorphous carbon in the horizontal dithering direction. The other is 'bent' CNT tip where the end of CNT is bent to a side direction. Using the former type of CNT tip, both sides of trench/line sidewall can be measured except for bottom corners, while the corners can be reached with the latter type, but the only one sidewall can be measured at a tip setting. The three types of tips appear to satisfy the requirements in both the size and accessibility to the re-entrant sidewall, and are awaiting actual test in CD-AFM.

Downscaling of semiconductor fabrication technology requires continuous improvements in production process control. To ensure tool-to-tool matching and compatibility of critical dimension-scanning electron microscopy (CD-SEM) measurements to measurements from other technologies, such as optical CD, or from other fabrication entities, accuracy has become a much more important factor than in the past. CD-SEM measurements have always yielded a bias, which can be quite significant, but also typically neglected since it does not vary much over a process window. However, the standard CD-SEM metrology approach to algorithm accuracy (which can be formulated "Accuracy= Precision + Calibration") does not work for small features; i.e., the measurement bias is not constant for small features. Limitations of the standard measurement algorithm, based on the treatment of the singular point of the waveform for CDs smaller than 30 nm and the new model library-based approach, were considered. The implementation of reliable measurement algorithms for features at the 45 nm node and beyond requires development of more sophisticated approaches to SEM signal treatment. A three-dimensional (3-D) physical model that takes into account physical processes related to the beam interaction with material is considered. Reliability of the new approach is verified using Monte-Carlo SEM simulation and real SEM images as compared to reference measurements; total measurement uncertainty (TMU) is improved with the better models. The relation of the developed method to the standard SEM measurement algorithm and model-based approach is also considered.

It is important to be able to quantify the imaging performance of CD-SEMs for such purposes as verifying the specification, rechecking after a routine maintenance, or for tool matching. To perform tests such as these it is necessary to have both appropriate software for image analysis and suitable test samples. A package of 2-D Fourier transform and analysis software, designed as a plug-in for the shareware IMAGE-Java program, has been developed and is freely available on line. The requirement for a reproducible and well characterized sample has been met by using direct-write electron beam lithography to fabricate suitable Fresnel zone plate structures.

Managing a fleet of metrology tools is becoming an extremely daunting task. This is especially so in manufacturing lines where it is not unusual to have many tools in the fleet and a very large mix of product and technologies. It is this large mix of product and technologies which pushes the number of recipes created into the thousands. Combine the large number of recipes with a poorly calibrated, monitoring and managed fleet of tools and productivity can be negatively impacted many ways. In this paper, these productivity detractors are explained in more detail to help understand the numerous ways a fleet of metrology tools can negatively impact the productivity of the manufacturing and development lines. In the pursuit of reducing metrology tool induced productivity detractors, the concept of metrology tool fleet management is presented. Categories of fleet management are also introduced along with a comprehensive discussion of requirements. It is hoped that this discussion of requirements and solutions concerning the metrology tool fleet management concept will launch efforts in coordinating the comprehensive solutions needed between suppliers and tool owners. Some recommendations are made regarding long term solutions to needs with respect to integrating fleet management into manufacturing fab systems.

As Critical Dimensions (CD) for semiconductor devices shrink to few tens of nanometers, the Line Edge Roughness (LER) or Line Width Roughness (LWR) becomes a critical issue because it can degrade resolution and linewidth accuracy [1] and causes fluctuations of transistors performances [2-8]. LER is currently calculated with top-view SEM images [9-10]. However, these values do not take into account the sidewall variation along the height of the feature (feature's geometry). Therefore, roughness information might get lost. In addition several issues impact the roughness measurement accuracy for example: blooming effect, resist slimming, algorithm used (...). Alternatively, the last generation of CD-AFM, [11,12] has been developed to measure pattern in three dimensions with a dynamic repeatability of around 1nm (3σ). By smartly tuning AFM parameters and choosing suitable AFM tips, CD, LER and LWR of both isolated lines and dense line are measured as a function of the position on the feature. This metrology technique can be used on a large range of materials: photoresist, silicon oxide and poly-silicon, without any pattern damage. Hence, it enables to fully characterize the evolution of the sidewall roughness after each technological step of a typical device fabrication. In this paper we will compare CD-SEM and CD-AFM techniques as a mean to measure LER and LWR on real resist structures and hard-mask structures (SiO₂) that show significant variations due to different chemical compositions or processes conditions. In order to well understand the limitations of each technique, we have generated and mixed various roughness amplitudes with various feature's shapes (different top rounding, sidewall angle...). Depending on the technique and feature's shapes, the roughness measurements trends are different which can lead to wrong process tuning and therefore degrade device performances at the end.

Although various approaches can be used to quantify linewidth roughness (LWR), it is essential to determine it with sufficient confidence. Statistical fluctuations inherent to the measurement process are making correlation between performance and LWR challenging. To reduce uncertainty, line width variations and LWR need to be monitored online in full automation by CDSEM. In this paper, we use this methodology to investigate the effect of LWR on electrical performance for various device applications. Our results quantify the impact of LWR by using matching techniques.

Line edge and line width roughness (LER/LWR) is commonly estimated by standard deviation sigma. Since the standard deviation is a function of sample line length L, the behavior of sigma(L) curve is characterized by the correlation length and roughness exponent. In this paper, an efficient and practical macro LER/LWR analysis is implemented by characterizing an arbitrary array of similar features within a single CD-SEM image. A large amount of statistical data is saved from a single scan image. As a result, it reports full LER/LWR information including correlation length, roughness exponent, sigma at infinite line length, and power spectrum. Off-line, in-house software is developed for automated investigation, and it is successfully evaluated against various patterns. Starting with the detailed description of the algorithm, experimental results are discussed.

The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.

An overview of the challenges encountered in imaging device-sized features using optical techniques recently developed in our laboratories is presented in this paper. We have developed a set of techniques we refer to as scatterfield microscopy which allows us to engineer the illumination in combination with appropriately designed metrology targets. The techniques have previously been applied to samples with sub-50 nm sized features having pitches larger than the conventional Rayleigh resolution criterion which results in images having edge contrast and elements of conventional imaging. In this paper we extend these methods to targets composed of features much denser than the conventional Rayleigh resolution criterion. For these applications, a new approach is presented which uses a combination of zero order optical response and edge-based imaging. The approach is, however, more general and a series of analyses based on theoretical methods is presented. This analysis gives a direct measure of the ultimate size and density of features which can be measured with these techniques and addresses what measurement resolution can be obtained. We present several experimental results, optical simulations using different electromagnetic scattering packages, and statistical analyses to evaluate the ultimate sensitivity and extensibility of these techniques.

A novel approach to overlay metrology, called Blossom, maximizes the number of layers measurable within a single optical field of view (FOV). As chip processing proceeds, each layer contributes a set of at least four marks, arranged symmetrically on concentric circles, to create a 90° rotationally invariant array of marks that "blossoms" to fill the FOV. Radial symmetry about the target center is maintained at each layer to minimize susceptibility to metrology lens aberrations. Overlay combinations among detectable marks within the target can be measured simultaneously. In the described embodiment, 28 distinct layers are represented within a 50μm square FOV. Thus, all the layers of a functional chip can be represented in a single target. Blossom achieves several benefits relative to overlay methods currently in practice: * Compression (>30X) of area required for overlay targets. * Nullification of within-target proximity effects. * Suppression of optical mark fidelity (OMF) errors. * Reduction of sensitivity to across-target detection noise.* Elimination of overlay error random walk among layers. * Reference mark redundancy for detection flexibility and robustness. * Integration of multi-layer and within-layer overlay control schema. * Simplification of overlay recipe creation and management. * Capture and visualization of overlay performance through the entire chip fabrication. Blossom results from 65-nm products in manufacturing are described.

The National Institute of Standards and Technology (NIST) and The International Sematech Manufacturing Initiative (ISMI) have been involved in a project to evaluate the accuracy of optical overlay measurements in the presence of measurement target asymmetries created by typical wafer processing. The ultimate goal of this project is to produce a method of calibrating optical overlay measurements on typical logic and memory production stacks. A method of performing accurate CD-SEM and CD-AFM overlay measurements is first presented. These measurements are then compared to optical overlay measurements of the same structures to assess the accuracy of the optical measurements. Novel image rotation tests were also performed on these structures to develop a method to decouple errors from metrology target asymmetries and measurement system optical asymmetries.

Overlay tool matching and accuracy issues are quickly reaching a comparable complexity to that of critical dimensional metrology. While both issues warrant serious investigation, this paper deals with the matching issues associated with overlay tools. Overlay tools need to run and measure as if they are a single tool - they need to act as one. In this paper a matching methodology is used to assess a set of overlay tools in a multiple of overlay applications. The methodology proposed in a prior² SPIE paper is applied here to a fleet of two generations of overlay tools to detect measurement problems not seen with convention Statistical Process Control techniques. Four studies were used to examine the benefits of this matching methodology for this fleet of overlay tools. The first study was a matching assessment study. The second study was a hardware comparison between generations of tools. The third study was a measurement strategy comparison. The final study was a long term matching exercise where one example of a traditional long term monitoring strategy was compared to a new long term monitoring strategy. It is shown that this new tool matching method can be effectively applied to overlay metrology.

In this publication, the contributors to in-field overlay metrology uncertainty have been parsed and quantified on a back end process and compared with results from a previous front end study¹. Particular focus is placed on the unmodeled systematics, i.e. the components which contribute to residuals in a linear model after removal of random errors. These are the contributors which are often the most challenging to quantify and are suspected to be significant in the model residuals. The results show that in both back and front end processes, the unmodeled systematics are the dominant residual contributor, accounting for 60 to 70% of the variance, even when subsequent exposures are on the same scanner. A higher order overlay model analysis demonstrates that this element of the residuals can be further dissected into correctible and non-correctible high order systematics. A preliminary sampling analysis demonstrates a major opportunity to improve the accuracy of lot dispositioning parameters by transitioning to denser sample plans compared with standard practices. Field stability is defined as a metric to quantify the field to field variability of the intrafield correctibles.

The feasibility of measuring overlay using small targets has been demonstrated in an earlier paper¹. If the target is small ("smallness" being relative to the resolution of the imaging tool) then only the symmetry of its image changes with overlay offset. For our purposes the targets must be less than 5μm across, but ideally much smaller, so that they can be positioned within the active areas of real devices. These targets allow overlay variation to be tested in ways that are not possible using larger conventional target designs. In this paper we describe continued development of this technology. In our previous experimental work the targets were limited to relatively large sizes (3x3μm) by the available process tools. In this paper we report experimental results from smaller targets (down to 1x1μm) fabricated using an e-beam writer. We compare experimental results for the change of image asymmetry of these targets with overlay offset and with modeled simulations. The image of the targets depends on film properties and their design should be optimized to provide the maximum variation of image symmetry with overlay offset. Implementation of this technology on product wafers will be simplified by using an image model to optimize the target design for specific process layers. Our results show the necessary good agreement between experimental data and the model. The determination of asymmetry from the images of targets as small as 1μm allows the measurement of overlay with total measurement uncertainty as low as 2nm.

Self-interferometric based electrical test patterns are proposed for highly-sensitive systematic projection printing field mapping and production wafer monitoring. The strategy is to adapt the high sensitivity of Pattern-And-Interferometric-Probe monitors for aberrations to electrical testing by means of short loop and within process flow process step sequences. For this application the measurement of the presence or absence of contact sized hole in the resist in a focus-exposure matrix would be replaced by the creation of an electrical open or short in a nominally conducting minimum sized feature. Both double exposure and single exposure test patterns are presented. Detailed image simulations have been used to demonstrate the principles, create layout designs, characterize performance and compare the enhanced sensitivity relative to typical circuit layout features. Sensitivities of 8% of the clear field per 0.01λ RMS have been verified through simulation of the electrical test pattern. Layouts of these patterns have been placed on multiple-student PSM test reticles for future experimental validation.

We have developed a new measurement techniques employing digital probing with AFM (Atomic Force Microscope) that can examine sidewalls of fine patterns. This new technique employs digital probing operations, such sample-tilt step-in operation, tilt-step-in operation with a sharpened tilted tip, and multi-angle step-in operation with a flared tip. First, we examined the validity of digital probing operation using a carbon nanotube (CNT) tip, showing the measurement repeatability of approximately 1 nm (3σ) on a fine trench pattern with 50 nm width and 300 nm depth. After the slip calculation between the tilted-tip and the sidewall for the new sidewall measurement technique, we measured a perpendicular reference sidewall with two types of operations, namely, tilt-step-in and multi-angle step-in operations. We then obtained 3D images of ArF resist patterns that involved measurement of sidewall surface roughness. Finally, we demonstrated a possibility of extending the technique for measuring denser trench patterns by using sample-tilt method and a tilted CNT tip.

Full wafer dual beam FIB-SEM systems have received a lot of industrial interest in the last years and by now are operational in several 200mm and 300mm fabs. These tools offer a 3D-physical characterization capability of defects and device structures and as such allow for more rapid yield learning and increased process control. Moreover, if SEM resolution is insufficient to reveal defect origin or the necessary process details, it is now also possible to prepare TEM samples using a controlled, easy to learn in-situ process and to efficiently continue the characterization with a high resolution TEM inspection. Thanks to latest hardware developments and the high degree of automation of this TEM sample preparation process, wafers no longer need to be broken and remain essentially free from contamination. Hence, the TEM lamella process can be considered as non-destructive and wafers may continue the fabrication process flow. In this paper we examine the SEM and TEM application capabilities offered by in-line dual beam systems. To qualify the wafer return strategy, the particle contamination generated by the system hardware as well as the process-induced contamination have been investigated. The particle levels measured are fully acceptable to adopt the wafer return strategy. Ga-contamination does exist but is sufficiently low and localized so that the wafer return strategy can be applied safely in the back-end of line process. Yield analysis has confirmed that there is no measurable impact on device yield. Although yet to be proven for the frond-end of line processes, the wafer return strategy has been demonstrated as a valuable one already in the backend of line processes. The as developed non-destructive 3-D SEM-TEM characterization capability does offer value added data that allow to determine the root cause of critical process defects in almost real-time and this for both standard (SEM) and more advanced (TEM) technologies.

The ability to measure profiles of high-aspect structures is important for the development of new integrated circuit fabrication processes. Delays in the development learning cycle frequently occur due to turn-around time associated with the logistics of off-line laboratory sectioning and analysis. Sample preparation techniques associated with existing cross-sectional imaging methodologies also necessitate destruction of the whole sample. Focused ion beam (FIB) sectioning has recently been used in conjunction with SEM imaging for profile acquisition inside the fabrication facility. However, full acceptance of FIB inside the cleanroom processing area has been slowed by concerns over the threat of Gallium contamination arising from the ion beam. There also exists uncertainty in the fidelity of FIB-based profile acquisition, due to the various artifacts associated with the ion beam mill sectioning process. In this article, the application of and difficulties associated with electron beam induced processing (etch and deposition) for obtaining feature profile shape information on masks and wafers will be described. Purely chemical reactions with much higher material selectivity and less damage have been employed to obtain microstructure profile information using various scanned electron beam tools. The superiority of electron beam induced deposition (compared to FIB) for passivation and replication of the surface topography prior to etching has also been demonstrated. In addition to electron and ion beam based sectioning, a novel atomic force microscope based nano-machining process has been developed for three-dimensional tomographic imaging of high-aspect features on masks and wafers. Images and profiles of feature regions not accessible with FIB/SEM or CDAFM methodologies will be presented. The challenges encountered for practical implementation of this new, non-beam-based, approach to sectioning will also be discussed. Advantages of this approach are: immunity to maximum aspect ratio limitations, superior lateral spatial sampling in X and Y, and no reliance on high-aspect probes for imaging. Therefore, tip-shape issues associated with currently incumbent CDAFM methodologies can be avoided altogether.

As we move forward to the 45 and 32nm node, MuGFET's (Multi-Gate Field-Effect Transistor) are considered more and more as a necessary alternative to keep pace with Moore's Law. If proven manufacturable, MuGFET's could eventually replace conventional CMOS transistors within a few years. The ability to perform proper and extensive metrology in a production environment is then essential. We investigate here some of the requirements of MuGFET metrology. Accuracy and line width roughness (LWR) metrology will play an essential role, because the small dimension of the features involved. 3D metrology is required when dealing with non-planar devices. Sophisticated check of optical proximity correction (OPC) is needed in order to ensure that the design is respected. We propose here some possible solutions to address the needs of MuGFET metrology in a production-worthy fashion. A procedure to calibrate CDSEM to TEM for accuracy is developed. We performed LWR metrology of fins in a fully automated way by using CDSEM, while the 3D information is obtained by means of scatterometry. Finally, we will discuss the application of design-based metrology (DBM) to MuGFET OPC validation.

CD measurement bias has long been reported as an inherent artifact of CD-SEM measurements. However, as feature dimensions decrease and line-to-space ratios increase, the magnitude of previously acceptable levels of measurement bias requires re-examination. Traditional attempts at correcting the bias has entailed slow, destructive or laborious techniques, such as comparisons of top-down CD-SEM measurements using standard algorithms with cross-section information, or correlating top-down data with complex tilted images. In this paper we expand the application of Critical Shape Metrology - a physics-based metrology technique for 3-D profile acquisition based on CD-SEM, to minimizing CD bias in real-time for a variety of feature dimensions and profiles. Samples used for the experiments were fabricated through E-Beam lithography and 193 lithography with a wide variation of sidewall angles and CDs, so that the measurement bias could be assessed over a sufficiently large range of patterned shapes. Reference measurements were performed using a CD-AFM and FIB-SEM

As the trends in integrated circuit fabrication follow Moore's Law to smaller feature sizes, one trend seen in lithographic technology is the continually increasing use of optical enhancements such as Optical Proximity Correction (OPC). Small size perturbations are designed into the nominal feature shapes on the reticle such that the intended shape is printed. Verifying the success of OPC is critical to ramp-up and production of new process technologies. CD-SEMs are imaging tools which are capable of measuring feature sizes in any part of a chip, either in a test structure or within a circuit. A new trend in CD-SEM utilization is the implementation of automated recipe generation of complex CD-SEM recipes. The DesignGauge system uses design-to-SEM recipe creation and data collection. Once the recipe creation flow is implemented, the task of recipe creation can be accomplished within minutes. These applications enable a CD-SEM to be utilized to collect data for very complex OPC CD-SEM recipe runs which measure many different unique linewidths, spaces, and pattern placements within a circuit to check OPC success and lithographic fidelity. The data collection can provide accurate data results that can be utilized for comparing achieved feature measurements to nominal values from the design layout. This new application adds much value to the CD-SEM compared to other technologies such as OCD, as it completes the evaluation of in-circuit behavior to test structures in a scribe lane, something OCD currently cannot do. The present work evaluates the capabilities of DesignGauge, which is available for the latest-generation Hitachi S-9380II CD-SEMs. The evaluation includes rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation and recipe execution.

This study demonstrates the MPPC (Multiple Parameters Profile Characterization) measurement method utilizing ArF photo resist patterns. MPPC is a technique for estimating the three dimensional profile of patterns which are imaged and measured on the CD-SEM (critical dimension scanning electron microscope). MPPC utilizes the secondary electron signal to calculate several indices including top CD, peak CD, top rounding, bottom footing, etc. This primary focused of this study is to understand the variations in pattern profile caused by changes in exposure condition. The results demonstrate the ability to extract pattern profile shape information by MPPC measurement that could not otherwise be detected by a conventional bottom CD measurement method. Furthermore, the results were compared to cross sectional images collected by STEM (scanning transmission electron microscope) to verify the accuracy of the MPPC technique. The peak CD results accurately estimate the pattern width when the sidewall angle of the feature is nearly vertical. Additionally, line edge roughness (LER) caused by pattern profile variations was evaluated utilizing MPPC. The results suggest that MPPC may be utilized to evaluate the roughness over the entire profile.

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. If this remains the case, the interaction of more complex designs with shrinking process windows will severely limiting parametric yield. The industry is responding with strategies based upon design for manufacturability (DFM) and multi-variate advanced process control (APC). The primary goal of DFM is to enlarge the process yield window, while the primary goal of APC is to keep the manufacturing process in that yield window. In this work, we discuss new and innovative process metrics, including simulation-based virtual metrology, that will be needed for yield at the 32nm technology node.

Optical proximity correction (OPC) plays a vital role in the lithography process of cutting-edge IC fabrication. The quality of lithography models used in OPC is fundamental to the final performance of the OPC in production. Traditionally, two-dimensional proximity features such as line-end, bar-to-bar or bar-to-line were only partially characterized because of the difficulty in transferring the SEM information into the OPC model building process. A new methodology of edge placement error (EPE) measurement using CD-SEM is proposed as part of an OPC model building and process/OPC qualification flow. It is not easy to generate EPE measurements because of the inherent need to overlay the design and the SEM in order to quantify EPE. The quality of the EPE measurement depends on both the accuracy of the SEM image scan rotation and magnification, but also on the accuracy of pattern matching between the design layout pattern and the realized pattern (wafer). These problems do not exist in simulation, but model calibration requires a direct comparison between simulation and measurement. Measuring EPE effectively brings the measurement information into the realm of the design. Hitachi High-Technologies has developed a "fully automated EPE measurement function" based on design layout and detected edges of SEM image as a solution to this issue. This study shows several practical evaluation results using the automated EPE measurement function. The applications that will be discussed are as follows. 1) Design based classification of edges and subsequent quantification of SEM EPE for many types of edge arrangement and orientation. In this study, we will examine line-end-adjacent, line-end, corner, and other critical gate edges. 2) SEM image based classification of EPE fliers as a new population of errors. 3) Comparison between the detected edge of the feature within the SEM image and a polygon shape generated by lithography simulation to determine the quality of the simulation. 4) Conversion of the SEM image edge contour into an OASIS file and construction of a process variability band to quantify CD variability for all 2D contexts in a SEM image.

Measurement bias is a central concept of critical dimension (CD) metrology. Bias is a complex function of sample, tool and time. Bias variation defines the total measurement uncertainty (TMU). TMU is a measure of metrology quality. Precision (or bias variation with time) is only a part of TMU. Often tool-to-tool and sample-to-sample components of bias variation exceed precision. To measure sample-to-sample bias variation, knowledge of the reference CD value for the samples is required. Since bias is sample specific, the technology representative set of calibrated samples has to be created. The described approach has been implemented for a comprehensive evaluation of optical scatterometry (OS) to determine readiness of OS for the 65 nm technology production. The tests covered nine OS applications representative of the technology. The testing revealed that OS metrology is mostly ready to support 65 nm technology production. Both spectral ellipsometry and angular reflectometry OS compete closely on all applications. OS demonstrates acceptable averaged bias for CD and sidewall angle for most applications. Correlation of OS to other metrologies is usually satisfactory. At the same time some problems have been observed. The majority of the tested applications show poor linearity for some measured parameters. Cross-correlation between parameters is usually the cause. OS has trouble to meet the semiconductor industry's tight fleet precision requirements. For all applications, OS tool matching is a major component of fleet precision. The evaluation also exposed some general CD metrology challenges. With accuracy allowance in a sub-nanometer range, it is difficult to find an adequate reference technique to verify and calibrate OS models. Atomic force microscopy (AFM) has been chosen as a reference technique during this evaluation, but it has limitations. Precision, sidewall profile resolution and tip finite dimensions are some of the AFM limitations. OS fleet TMU for many applications is unacceptably high. Further work is needed to better understand the impact of reference data uncertainty on these alarming results. It is clear that to achieve a desired sub-nanometer agreement between reference and OS data, one must pay scrupulous attention to every detail of the experiment.

We used full Mueller polarimetry in conical diffraction geometries to characterize 1D holographic optical gratings etched in bulk silica with a patterned photoresist layer. We studied four different samples corresponding to different stages of etching, with a Mueller polarimeter based on ferroelectric liquid crystals, operated in the visible. Two samples were also characterized by standard spectroscopic ellipsometry (SE) in the UV-VIS range (300-800 nm). The measured spectra were fitted with a Rigorous Coupled Wave Analysis code with different models of grating profiles. With the Mueller spectra the model adequacy could be assessed from the stability of the optimal values of the fitting parameters when the azimuthal angle was varied. The conclusions were found to be in agreement with AFM images of the sample, while the fits of the SE data were too poor to provide any information in this respect. A key issue for process control is resist-silica interface localization, a difficult task due to the low index contrast for these two materials. In fact, strong correlation occurs between resist and silica thicknesses when SE spectra, taken in the usual planar diffraction geometry, are fitted. Our approach clearly reduces such parameter correlations, leading to a reliable localization of this interface.

In this work we demonstrate the application of a unique type of scatterometer to the measurement of advanced geometry semiconductor devices. Known as a dome scatterometer, the technology is capable of measuring multiple diffraction orders at multiple angles of incidence, thereby providing a means for gathering a large amount of scatterometry data in a short period of time. Dome scatterometers are also capable of measuring light scattered as a function of both theta (zenith) and phi (azimuth) incident angles, and for a variety of polarimetric configurations, all of which provide more information about the scattering structure and contribute to improved sensitivity. A dome scatterometer can also measure a grating structure regardless of its orientation, so that horizontal and vertical structures can be measured without the need for a wafer rotation. Prior to initiating measurements with the dome scatterometer, we surveyed available laser sources and modeled their expected sensitivity theoretically to determine the best illumination wavelength for the applications we intended to study. Our findings demonstrated that a wavelength around 405nm is suitable for a wide variety of applications, but provides the best improved sensitivity for etch applications. We then modified our dome scatterometry optical system to accommodate a Using a 405nm laser, and performed measurements were performed on several types of grating structures. Examples of the excellent signal-to-noise ratio of dome scatterometry measurements across these applications are provided. Measurement data from applications including patterned photoresist, patterned poly lines and back-end trench interconnect structures will be presented. Comparisons to metrology tools such as AFM and CD-SEM will be made. Precision data will also be summarized, and the extendibility of dome scatterometry will be discussed.

The influence of semiconductor manufacturing process variation on device parameter measurements for angular scatterometry was studied. Process variations, e.g, temperature and pressure variation of poly deposition, are considered to affect the optical properties of the deposition layer, and hence cause inaccurate model-based scatterometry measurements. This study investigates measurement error of device parameters if the optical properties change but the model stays for the same in angular scatterometry. A series of diffracted signatures was generated whose optical properties change slightly but keep the same structure. This work measured n (refractive index) and k (extinction index) of materials on wafer from the nominal process condition. Then, n and k are used to create a comparison library. The comparison library fixes all parameters other than varying CD (critical dimension) parameter. When poly layer n changes, the scattering signatures also change. The inaccuracy of CD measurement could be evaluated by comparing varying signatures due to optical properties change to the nominal process condition. An optimal structure design and feature region selection algorithm was developed to reduce errors introduced by these process variations to CD measurement. For angular scatterometry, the reflectance at some scan angles performs lower sensitivity to the optical parameters variation than the reflectance at other scan angles. By determining which scan angles contain less sensitivity and further optimize target design within the process variation range, the influence of process variation on device parameter measurement and the number of measurements used in the inversion process can be reduced. By using 65nm and 45nm as design rules, optimized grating structure with most sensitivity to CD measurement and the least influence on poly refractive index variation were obtained. The optimized grating structures are suitable for inline semiconductor process control of CD measurement for scatterometry.

Traditional mask critical dimension (CD) disposition systems with only one or two targets is being challenged by the new requirements from mask-users as the wafer process control becomes more complicated in the newer generation of technologies. Historically, the mask shop does not necessarily measure and disposition off the same kind of CD structures that wafer fabs do. Mask disposition specifications and structures come from the frame-design and the tapeout, while wafer-level CD dispositions are mainly based on the historical process window established per CD-skew experiments and EOL (end of line) yield. In the current high volume manufacturing environment, the mask CDs are mainly dispositioned off their mean-to-target (MTT) and uniformity (6sigma) on one or two types of pre-determined structures. The disposition specification is set to ensure the printed mask will meet the design requirements and to ensure minimum deviation from them. The CD data are also used to adjust the dose of the mask exposure tools to control CD MTT. As a result, the mask CD disposition automation system was built to allow only one or two kinds of targets at most. In contrast, wafer-fabs measure a fairly wide range of different structures to ensure their process is on target and in control. The number of such structures that are considered critical is increasing due the growing complexity of the technology. To fully comprehend the wafer-level requirements, it is highly desirable to align the mask CD sample site and disposition to be the same as that of the wafer-fabs, to measure the OPC (optical proximity correction) structures or equivalent whenever possible, and to establish the true correlation between mask CD measurements vs. wafer CD measurement. In this paper, the development of an automated multiple-target mask CD disposition system with the goal of enabling new sampling strategy is presented. The pros and cons of its implementation are discussed. The new system has been inserted in the production of Intel's 65 nm technologies and has become the POR (plan of record) for the future technologies that are being developed.

As metrology tolerances for photomasks become increasingly tight, the issues of measurement methods and calibration standards become more and more important. This is as true for optical phase metrology as it is for dimensional metrology. To first order, an optical phase standard can be defined by etching a step or trench into a transparent medium like fused silica with a well-characterized index of refraction. The normal-incidence phase shift of such a structure can be calculated with accuracy limited mainly by our ability to measure the physical depth of the trench. Other methods exist for measuring optical phase shifts in alternating aperture masks. For example a Levenson grating exhibits symmetrical behavior through focus only if the phase difference between the phase shifted and unshifted openings is exactly 180°. A measured asymmetry between the phase shifted and unshifted clear features in such a grating can be used to quantitatively measure the deviation from 180° optical phase. This approach is particularly attractive because the measurement can be made on an aerial image metrology system with the numerical aperture and illumination conditions used by the wafer stepper that will eventually project the mask. Calibration of optical phase in attenuating phase masks is more difficult. Until now there has been no accurate way to create and verify a calibration artifact. In this paper we discuss a new phase metrology pattern for attenuating phase masks. The phase error of this pattern can be determined to high accuracy by aerial image measurements. This pattern can be used to create an optical phase standard for calibrating phase metrology equipment for attenuated phase masks, or as a witness pattern on a product mask to verify the phase accuracy of that mask.

Since numerical aperture (NA) becomes greater than 1.0 in immersion lithography, polarization effect will be one of the critical issues in imaging performance. In patterning 40nm or smaller node with 193nm wavelength, transverse magnetic (TM) polarized beam does not contribute to image contrast. Hence most layers will require polarization controlled illumination to prevent the contrast degradation. For this reason, polarization controllability of illumination becomes one of considerable budget of critical dimension (CD) variation. For CD uniformity control of exposure tool and CD budget analysis, it is necessary to measure the polarization performance of illumination system. In-situ or special measurement tools are currently being developed to measure the polarization state of illumination and projection optics. However, each tool maker has its own measurement tool, and consequently in order to compare the polarization performance across different tools, a common measurement method is required. In this paper, a special mask pattern for monitoring polarization state of illumination has been designed. The polarization degrees have been measured for polarized illuminations of 193nm high NA tool. The pattern shape has been designed based on electric magnetic field (EMF) simulation utilizing the diffraction efficiency difference. The actual mask pattern sizes are measured to correct the measurement error. Differences between the EMF simulation and the real exposure results have been investigated for several illumination shapes and for different polarization status.

The concept of using Scanning Electron Microscopy and Die-to-Database techniques to rigorously inspect advanced lithography products such as X-ray Lithography, Imprint, and Stencil masks as well as other Next Generation Lithography (NGL) is compelling. Current optical capabilities reach down to 0.2μm and do so by interpolating pixilated optical data. Applications at 4x magnifications, such as Chrome on Glass or Phase Shift Photomasks mesh with this resolution of inspection and have been able to migrate down the lithography nodes hand in hand. As the demands for resolution progress, optical lithography has been increasing the requirements upon inspection systems presently available through the addition of assist features and serifs, which are difficult to directly verify. These assist features are effectively approaching 1x dimensions. A printed feature that is slightly out-of-tolerance for CD, shape, or position relative to other structures, may still yield acceptable performance. This added resolution challenge of working closer to a 1x Magnification with ever decreasing structure sizes is easily achieved with Scanning Electron Microscope technology. The Die-to-Database inspection technique utilizes the CAD image, which defines the designer's original intended structure, as the reference image. In this paper, we will introduce a revolutionary approach for utilizing the full potential of Scanning Electron Microscope images for inspection purposes. The technique incorporates an aggressive but reliable interpretation of the image data to recreate GDS data files which can then be validated against the desired GDS data for hard defects, abbreviated / missing features, and even shifts or placement errors.

Line edge roughness (LER) has become a standard topic in the semiconductor industry for its possible yield impact on wafer production. Recently a number of studies address its measurement process to increase the reliability of results. Here, we investigated roughness on photo lithographic masks, which is the blue print for wafer production. It is shown that LER influences feature uniformity and thus has a considerable impact on overall mask production yield. To determine the roughness parameters we varied measurement parameters on a scanning electron microscope to optimize reproducibility and repeatability of the obtained values. Two parameters dominate the LER values. The first parameter is the length used to average the signal from the scanning electron microscope and to obtain the position of a single edge point. Good results for this so called summing length were obtained for values above 100 nm. The second important parameter is the total length of the investigated line that is used to calculate the LER. Here, we found that the increase of LER values with increasing investigation length is similar to the well-established behavior on wafers. It was found that the average LER value calculated from various sites saturates at investigation lengths larger than 10 μm, whereas single LER results show no scattering within measurement precision for investigation lengths larger than 30 μm independently of mask position. In comparison to similar investigation on wafer both the summing length as well as the investigation length have to be chosen about one magnitude larger. It is suggested that the multi exposure process of mask creates roughness on length scales of the order of several micrometers.

In this paper, we report on a Scatterometry based metrology system that provides line width, line thickness, and trench depth measurements on APSM and EPSM photomasks. Measurements were made with scatterometer in DUV to visual wavelength range. Calculation of profile information was performed by a library-based analysis software. We characterized the CD uniformity, linearity, trench depth uniformity. Results show that linearity measured from fixed-pitch, varying line/space ratio targets show good correlation to top-down CD-SEM with R² of more than 0.99. EPSM FCCD data was obtained from both scatterometer and CDSEM. Results show that MEEF calculation based on scatterometer CD shows about 40% improvement in removing mask-induced CD non-uniformity, compared to calculation based on CD SEM data. This is thought to be due to 'averaging' effect of scatterometer. Depth measurements from APSM show that scatterometer makes good correlations to AFM, generally within 3nm of each other. The data show that Scatterometry provides a nondestructive means of monitoring PSM profiles combined with relatively little time loss.

Dense repetitive wafer structures, such as memory cells, with a pitch below the wavelength of the illumination light may take on effective birefringent properties, especially in layers of high refractive index materials such as silicon or conductors. Such induced "form birefringence" effects may result in dependency of the optical response on the illumination polarization and direction. In such structures, control over the polarization of the light becomes important to enhance signal-to-noise ratio (SNR) of pattern defects. We present defect detection results and analysis using DUV laser illumination for different polarization configurations and collection perspectives on Flash RAM devices. Improvement in detection SNR of bridge defect type is observed with linear illumination polarization perpendicular to the pattern lines. Generally, for small design rules (smaller than wavelength) polarization effects become more evident. Also, for smaller defect sizes, detection strongly depends on control of the illumination polarization. Linear polarization perpendicular to the pattern showed penetration into the structure even though the pitch is smaller than the illumination wavelength.

This paper discusses the controls benefit accomplished on both product wafers and process tools at IBM's 300mm wafer manufacturing line by using integrated auto-macro defect inspection in all the photolithography tool clusters for after-develop-inspection (ADI). Inspection is supported on all production wafers (with possibility to sample wafers if desired). To get to this level of control the overall 'ADI process' in the line had to be first rendered manufacturable. Therefore, significant effort had to be focused towards decreasing false fails and nuisance holds. As a result, over the last year inspection software related false fails were reduced 3X, hardware related PC communication fails were decreased 5X, and fab automation related nuisance wafer holds were reduced 12X. Fail rate has been sustainable at 6% (± 2%) for over two quarters. At this point only 20% of the fail rate is false and is mostly attributable to hardware related wafer alignment issues during inspection. By decreasing false fails and hold rates, sensitivity and effectiveness in the line towards correctly reacting to real fail signals significantly improved. Product wafers with real fails are now consistently reacted to real-time in the line leading to rework and elimination of photo sector generated macro defects. Contribution of this integrated metrology system to fab rework rate in eliminating yield impacting macro defects from product wafers, as well as examples of captured defects that have identified several process tool problems are also presented. Majority of rework contributors are defects generated from intermittent photo process tool issues that randomly occur and disappear (versus systematic process tool issues that typically end up being flagged within two consecutive failed lots). Typically 0.5 to 1% of the ADI inspected wafers get reworked for macro defectivity translating to a significant number of wafers - thus justifying ADI return-on- investment. Note that real fails as a result of defectivity propagation from prior photolevels - estimated at 15% of the fail rate, do not get reworked. Additionally, real fails determined to be non-reworkable as a result of defectivity from the current photolevel - estimated at 50% of the fail rate, also do not get reworked. Further, by analyzing real fails for intra/inter wafer signatures systematic process tool issues are being consistently flagged on the line. Overall, ADI at IBM's 300mm wafer fab has evolved into a real-time wafer level go/no-go control for both product and process tools.

We analyzed the electron-irradiation damage induced in wafers by SEM inspection, which uses SEM images of voltage contrast formed by the charges on the pattern due to the electron irradiation. MOS capacitors were selected as samples because of their characteristic sensitivity. We studied the effects of electron-beam energy and charging on a MOS-capacitor test element group. To determine flat-band voltage, density of created traps, and oxide fixed charges in the MOS capacitors before and after the irradiations of the capacitors by electron beams under various conditions, we measured high-frequency and quasi-static capacitance-voltage characteristics. We found that the higher-energy electron beam, whose electron range was larger than the thickness of the gate electrode, created traps at the interface between the silicon substrate and the gate dielectric. The flat-band voltage of the MOS capacitor was shifted by the created traps. Although these traps were created by the transmission of the electron beam into the dielectric, they were not created only by charging on the gate electrode; neither was an oxide fixed charge created in the MOS capacitor. Accordingly, for damage-free inspection of MOS devices, the electron-beam energy should be low enough that the electron range is smaller than the thickness of the gate electrode. On the other hand, the flat-band voltage did not shift owing to charging on the pattern surface during the electron irradiation. However, the gate dielectric was broken down by charging on the gate electrode at high voltage. Accordingly, for damage-free inspection, the charging voltage should be controlled so as not to break down the gate dielectric.

This paper presents the application of an innovative concept as potentially very powerful in-line diagnosis techniques in both process window optimization and yield enhancement for 65nm-and-below generations of technology. These applications were fulfilled with a novel methodology of the measurement and quantification of the grey levels on the SEM images and their correlation with the physical/electrical parameters of the semiconductor process steps. With these techniques and the few demonstrations, the virtual in-line semi-electrical measurement is proven to be a feasible technique in achieving technology development with lower cost and faster iteration cycle for continuous improvement. Else than technology development, the same techniques can also be served for the purposes of process window optimization and tool/ recipe/ process monitoring/qualification applications in volume production.

The switch from dry to immersion lithography has important consequences regarding wafer defectivity. It has been shown that for successful and efficient defect reductions related to immersion lithography the capability to distinguish immersion/patterning related defects from stack related defects is very useful during process control. These stack related defects can be observed after careful partitioning of individual layer inspections and the analysis of this data through DSA in Klarity. The optimisation of the dark field inspection SP2 tool, central in this paper, shows that improved sensitivity at adequate signal to noise ratio can be obtained on the resist stacks by using the smaller wavelength as the UV-laser light present in the SP2. For bare Si and BARC oblique incidence illumination gives the best sensitivity and captures the most defects. However monitoring of the resist and stacks with resist requires normal incidence illumination since the nature of defects and film result in a higher scattering intensity using normal illumination. The use of an optical filter and a 10% laser power also contributed to establishing a lower and stable background signal for each inspection scan. As immersion tool development is improved and immersion specific defectivity is reduced, the proportion of the stack related defects will become a significant fraction of the overall target for further defect reduction. This includes point defects (embedded particles) or flow defects (streaks) identified and classified using SURFimage. Finally this information is to be used to identify the defect origin(s) for ultimate elimination of defects in the stacks.

Measurement characteristics in scatterometry and CD-SEM for lot acceptance sampling of inline critical dimension (CD) metrology were investigated by using a statistical approach with Monte Carlo simulation. By operation characteristics curve analysis, producer's risk and consumer's risk arising from sampling were clarified. Single use of scatterometry involves a higher risk, such risk being particularly acute in the case of large intra-chip CD variation because it is unable to sufficiently monitor intra-chip CD variation including local CD error. Substituting scatterometry for conventional SEM metrology is accompanied with risks, resulting in the increase of unnecessary cost. The combined use of scatterometry and SEM metrology in which the sampling plan for SEM is controlled by scatterometry is a promising metrology from the viewpoint of the suppression of risks and cost. This is due to the effect that CD errors existing in the distribution tails are efficiently caught.

Spectroscopic critical dimension (SCD^TM) metrology on line gratings has previously been shown to be a sensitive and useful technique for monitoring lithographic focus and exposure conditions. Line end shortening (LES) effects are sensitive to focus and potentially more sensitive to focus variation than side wall angle or other profile parameters of line gratings. Rectangular line segment structures that exhibit line-end shortening behavior are arranged in a rectangular two-dimensional (2D) array to provide a scatterometry signal sensitive to the profile of the thousands of line ends in the measurement beam spot. Spectroscopic ellipsometry (SE)-based scatterometry measurements were carried out on 2D array targets of rectangular features exposed in a focus-exposure matrix (FEM). The focus and exposure sensitivities of multiple shape parameters were found to be good and uniquely separable. In addition, the side wall angle of the line ends was found to be nearly linearly dependent on focus and provide necessary focus direction information. Focus and exposure can be determined from SCD measurements by applying a model generated to describe the focus-exposure behavior of multiple shape parameters using KLA Tencor's KT Analyzer software. Several different models based on different combinations of shape parameters were evaluated. Focus measurement precision of 3nm 3σ was obtained, which will be useful for lithography processes with tight depth of focus.

Scatterometry is a novel metrology approach for process control that has recently been gaining more momentum in microlithography applications. The method can simultaneously measure Critical Dimension (CD), Side Wall Angle (SWA), and thickness of more than one layer. It analyzes the scattered and diffracted light from a periodic array of lines or holes that represent the surface structure of the measured sample. Scatterometry provides a non-destructive technique offering high precision and stability along with high tool-uptime performance. As such, it offers an excellent approach for real-time high volume production control with significant advantages as compared to traditional technologies such as CD-SEM and Profilometry. As the structure dimension shrinks considerably, producing high precision results becomes more critical. To date, reports on the deployment of scatterometry in real production environment have focused on Front End of Line (FEOL) applications such as STI and Gate. However, Back End of Line (BEOL) process control has not been widely reported. In this work, we will discuss the results of our study specifically for metal trench and contact layer on both patterned and etched wafers for 65nm technology node. We will also report the comparison between Scatterometry results to Critical Dimension Scanning Electron Microscope (CD-SEM) and Atomic Force Microscope (AFM). Finally we will provide a statistical analysis of our scatterometry results including precision, fleet precision, and TMU analysis. In contrast to the relatively simple stacks that comprise a FEOL structure, BEOL layers are typically complex structures with a large number of underlying layers. Generation of simulated scatterometry signatures that constitute a reference library for complex structures can require long computational times and result in large file sizes. To mitigate the computational overhead, it is necessary to intelligently decide which parameters to fix and which to vary. An additional complication is presented due to similarities in the optical properties of BEOL stack materials, which can introduce potential for parameter cross-correlation in the measurement. We will discuss methodologies for optimally selecting parameters to be fixed or varied to minimize these effects.

The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

We introduce a novel in-scanner aerial image sampling technique using a sensor wafer that can be loaded into a production scanner to acquire data at the wafer plane, and under exact production conditions in terms of all optical settings and parameters of the actual scanner and an actual reticle. We demonstrate the applicability of this system to CD uniformity characterization of a production scanner in combination with a test reticle. CD estimates can be directly obtained from the image data by applying a fixed threshold, by employing a calibrated resist model to the sensor data, or by using the sensor data to accurately calibrate a complete lithography model. The linear response of the sensor provides complete information on the imaging process, and CD data can be immediately correlated to other image parameters, such as contrast, ILS, peak signal values, etc. We demonstrate the ability of the system to characterize CD variations and through-pitch curves, and to generate CD uniformity maps across the exposure field. We have extensively studied the repeatability and reproducibility of the system, and show its ability to detect changes in imaging performance over time in a production environment, differences between exposure tools, or different mask manufacturing processes.

Scatterometry has been demonstrated to be a useful measurement technique, which allows to examine a full reconstruction of the measured structure in the semiconductor process, e.g. CD, thickness, and overlay. Even though the potential of such technique has been known for many years, the challenge for extracting quickly and accurately the relevant constitutive parameters from a diffractive signature remains. In general, the device parameters are determined by finding the minimum RMSE (root mean square error) between a measured signature and theoretical signatures in the model-based library without considering the correlation among these parameters, which induces the match error problem. This study presents a novel method, applying neural network algorithm to identify the correlation between device parameters, to reduce the correlation-induced error and increase measurement precision.

Earlier work describes the concept and the design of the Integrated Aerial Image Sensor (IAIS) [1]. This paper focuses on the first principle modeling and the physical construction of the IAIS. Our modeling is based on Abbe's formulation. Assuming a partially coherent illumination source, the partial, total and final detector images are obtained through optical system simulations, combined with a wafer-plane aperture mask simulation, using software provided by Panoramic. The performance of the IAIS under different lithography settings can be predicted accordingly. Our intent is to create a library that captures the aerial image to detector image correspondence in order to facilitate rapid analysis. We also examine several approaches towards the integration of CCD chips onto the test wafer substrate. Although there are several issues that still need to be resolved, a low temperature bonding scheme involving capillary force assisted alignment appears quite promising and is being discussed in some detail.

ArF lithography has shrunk photo resist patterns down to 60nm from 80nm with the help of various RETs (resolution enhancement technologies). Photo resist thickness also has been thinner than ever to increase image contrast and DoF margin and to avoid pattern collapse due to high aspect ratio. Etching process became more difficult and marginal by using thin resist patterning so that new BARC materials having high etching selectivity are required. Since amorphous carbon (a-C) and SiON have good etch selectivity between them, they can be used as hard mask materials for thin resist process. Lithographic alignment system usually uses the light of 400 to 700nm. In general a-C has certain level of light absorption in this wavelength range and the absorption coefficient increases with deposition temperature of a-C. Because a-C film is not suitably transparent to the alignment light, overlay control might get worsen as the thickness of a-Carbon film increased. In this paper, we will present the effect of the thickness of a-Carbon film on alignment signal strength, alignment accuracy and overlay control of various layers. Simulation of alignment signal is conducted and compared with experiment results. It is also studied whether the overlay control can be improved by changing the spectrum of alignment light or structural design of alignment marks. Improvements on alignment accuracy and overlay control are examined by lowering the extinction coefficient, k of a-Carbon film. In conclusion, because photo resist only is not sufficient for a mask during etch step as the thickness decreased further, adoption of new hard mask is inevitable. It is the alignment trouble for a-Carbon that should be cleared before being named as a main stream of new hard mask.

Displacement sensing and estimation (DSE) is important preprocessing task for many image-based processing systems that extract information from multiple images. In last two years, we gained significant insight of the nature of DSE and developed theory and algorithm framework named nanoscale displacement sensing and estimation (nDSE). We also build procedures to apply nDSE to overlay alignment down to the nanoscale. We will introduce two basic theories: Phase Delay Detection (PDD) and Derivatives-based Maximum Likelihood Estimation (DML) and associated DSE algorithms, noticeably Near-Neighbor-Navigation (N-Cubed) algorithm. We presented our best nDSE experimental result of 1 nm (1σ) while tracking 5 nm stepping. To develop nDSE-based nanoscale alignment, we introduced our definition of displacement, alignment and pseudo-displacement. We presented both theoretical and practical procedures to use nDSE to achieve nano-alignment down to the 10s of nano-meters and beyond. Then we compared nDSE-based nano-alignment to other industry standard alignment method and attempt to show the substantial advantages of nDSE based alignment in terms of cost and simplicity of the system design.

The paper describes the operation of a high-precision long range three-dimensional nanopositioning and nanomeasuring machine (NPM-Machine). The NPM-Machine has been developed by the Institute of Process Measurement and Sensor Technology of the Technische Universität Ilmenau. The machine was successfully tested and continually improved in the last few years. The machines are operating successfully in several German and foreign research institutes including the Physikalisch-Technische Bundesanstalt (PTB). Three plane mirror miniature interferometers are installed into the NPM-machine having a resolution of less than 0,1 nm over the entire positioning and measuring range of 25 mm x 25 mm x 5 mm. An Abbe offset-free design of the three miniature plane mirror interferometers and applying a new concept for compensating systematic errors resulting from mechanical guide systems provide extraordinary accuracy with an expanded uncertainty of only 5 - 10 nm. The integration of several, optical and tactile probe systems and nanotools makes the NPM-Machine suitable for various tasks, such as large-area scanning probe microscopy, mask and wafer inspection, nanostructuring, biotechnology and genetic engineering as well as measuring mechanical precision workpieces, precision treatment and for engineering new material. Various developed probe systems have been integrated into the NPM-Machine. The measurement results of a focus sensor, metrological AFM, white light sensor, tactile stylus probe and of a 3D-micro-touch-probe are presented. Single beam-, double beam- and triple beam interferometers built in the NPM-Machine for six degrees of freedom measurements are described.

As IC feature sizes become smaller and smaller, requirements for Critical Dimension (CD) variations control have become a critical issue. A new process for the control and correction of intra-field CD variations (Critical Dimension Control or CDC) was applied and it's influence on defects detection and photo-masks inspection capabilities at different modes of inspection was investigated. CD Control (CDC) of the photomask is a process in which Deep UV transmittance is selectively altered by patterns of small partially scattering shading elements (Shade in Element^Tm) inside the quartz. The shading elements are formed by a process of shooting an ultrafast laser beam focused inside the mask substrate, resulting in localized intra-volume breakdown inside the quartz which creates local pixels of modified index of refraction (delta n). An array of such pixels with constant density constitutes one shading element. Process patterns are predetermined according to a CD variations map which may be supplied from wafer CD SEM, Optical CD or mask aerial imaging simulation tool (AIMS). Thus by changing local photomask transmission levels, it is possible to correct for the CD variations inside the field. Attenuation level, or optical density of the shading elements depends on the laser pulse energy, distance between pixels, number of layers and the size of the shading element itself. Since photomask transmittance is being changed, qualification of the impact of the transmittance changes on the defect detection and analysis capabilities are required. In this study, the principles of patterning of scattering elements inside transparent media by focusing of ultra-short laser pulses were introduced and explained. Analysis of the effects to both mask and wafer due to the CDC process was verified by full printing process applied to wafers, and by aerial imaging simulation tool. More tests for CDC required also tests by automatic reticle inspection tool to be production-worthy for the 65nm node and beyond.

Bright-field inspection is still strongly required for 45 nm semiconductor device processes to detect several kinds of defects on patterned wafers. We have been carrying out verification of our defect inspection system using sub-200nm wavelength light. As part of the verification work, we evaluated the system's inspection imaging characteristics by using a pilot POC tool and by simulations. The image evaluation system used has a sub-200 nm wavelength light source. Two kinds of magnifications, 100x or 250x, can be selected. Test wafers with the same patterns and programmed defects were used. Simultaneously, UV (365 nm) images were taken by an inspection tool. The results of the reflectivity simulations suggest that the average reflectance at 198 nm is basically the same as that for present inspection wavelengths. A three dimensional electromagnetic simulator was used to evaluate the images of patterns and programmed defects described above. Image contrasts for Line and Spaces were also calculated. It is confirmed from both the experimental and simulation results that (1) sub-200 nm images are superior to UV images in contrast, and that (2) the image contrast improves with increasing magnification because of a reduction in pixel size. Further, a quantitative defect detection procedure was taken to identify programmed defects. Several sizes of extrusion defects were evaluated. Examination of the differential images under the three optical conditions showed that sub-200 nm light and 250x were most desirable, followed by sub-200 nm light and 100x. Sub-200 nm provided an enough pixel grey level difference value to detect extrusion defects down to 50 nm.

CD-SEM is currently poised as the primary method of choice for CD metrology because of its nanometer scale spatial resolution, superior precision, and relatively high throughput. However, issues still continue to emerge that can threaten the measurement performance for the various sample types encountered. The impact of issues arising from electron beam induced modification of the sample materials on critical dimensional metrology and lithographic process control will be assessed and approaches to mitigate these effects will be proposed. The two primary issues of interest related to scanned electron beam based measurements of patterned lithographic materials in this article are shrinkage of the ArF 193nm resist and undesired deposition of contaminants occurring during CDSEM measurements.

In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

Design rule shrinkage and the wider adoption of new device structures such as STI, copper damascene interconnects, and deep trench structures have increased the necessity of in-line process monitoring of step heights and profiles of device structures. For monitoring active device patterns, not test patterns as in OCD, AFM is the only non-destructive 3D monitoring tool. The barriers to using AFM in-line monitoring are its slow throughput and the accuracy degradation associated with probe tip wear and spike noise caused by unwanted oscillation on the steep slopes of high-aspect-ratio patterns. Our proprietary AFM scanning method, Step in mode®, is the method best suited to measuring high-aspect-ratio pattern profiles. Because the probe is not dragged on the sample surface as in conventional AFM, the profile trace fidelity across steep slopes is excellent. Because the probe does not oscillate and hit the sample at a high frequency as in AC scanning mode, this mode is free from unwanted spurious noises on steep sample slopes and incurs extremely little probe tip wear. To fully take advantage of the above properties, we have developed an AFM sensor optimized for in-line use, which produces accurate profile data at high speeds. The control scheme we have developed for the AFM sensor, which we call "Smart Step-in", elaborately analyses the contact force signal, enabling efficient probe tip scanning and a low and stable contact force. The mechanism of the AFM sensor has been optimized for the higher scanning rate and has improved the accuracy, such as the scanning planarity, position and height accuracy, and slope angle accuracy. Our prototype AFM sensor can scan high-aspect-ratio patterns while stabilizing the contact force at 3 nN. The step height measurement repeatability was 0.8 nm (3σ). A STI-like test pattern was scanned, and the steep sidewalls with angles of 84° were measured with high fidelity and without spurious noises.

AIM grating targets were optimized and implemented on the metal 2 Aluminum layer in high volume production of 110-nm DRAM devices. Grating target structures are intrinsically more compatible with Aluminum process design rules, allowing overlay target optimization to better fit the process and better cope with the large grain structure of the Aluminum layer. With the implementation of AIM overlay targets we were able to achieve tighter control of the Aluminum patterning, we also achieved smaller overlay residuals, better matching between post litho and post etch measurements, better modeling and less rework. Above all, AIM targets improve the overlay metrology tool capability and provide a better tool-to-tool matching performance.

Chemical mechanical planarization (CMP) is a challenging process step for manufacturers implementing dualdamascene architectures at the 65 nm technology node. The polishing rate can vary significantly from wafer-to-wafer, across a single wafer, and across a single die, depending on factors including electroplate profile, slurry chemistry, pad wear, and underlying structure. The process is further complicated by the introduction of low-k dielectrics that have significantly different mechanical properties than the harder SiO₂ they replace. Picosecond ultrasonics is a nondestructive, small-spot method that can be used for in-line on-product monitoring of metal processes including copper CMP. In this paper we will present gauge-capable picosecond ultrasonic results on copper erosion test structures that also demonstrate excellent correlation with electrical test measurements and TEM results on 65 nm products.

We propose a new method for the evaluation of line-edge or linewidth roughness (LER/LWR). Conventional, directly measured LER/LWR values always contain a random noise contribution, which is called LER/LWR bias. Our method can separate this bias artifact from the true LER/LWR by using a single image of the sample pattern. The idea is based on the dependency of a measured LER/LWR value on the image-processing parameter for noise reduction. Both, the conventional and the new bias-free LER were calculated on series of images with different frame integration numbers but a fixed field of view. In addition, the validity of this method to the gate-LWR measurement on an ArF resist line pattern was examined. The LER/LWR obtained by our method was independent of the frame number, and agreed with the conventional LER/LWR as measured on an image with a sufficiently large frame-number. That is, our method can evaluate LER/LWR without random-noise contribution, suggesting that the method can be applied to images recorded under low-sample-damage conditions (i.e., low signal-to-noise ratio). It is concluded that the proposed bias-free LER/LWR measurement method will be a powerful tool in lithography metrology especially for achieving practical and accurate LER/LWR measurement with low sample damage.

As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1μm. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.

Immersion lithography offers the semiconductor industry an opportunity to extend the current ArF processes to smaller nodes before switching to a shorter wavelength. The transition to immersion will require increased attention to the photomask along with new effects influencing the aerial image formation as the numerical apertures (NA) of scanners move up to at least 0.93 and beyond. Feature sizes on the photomask become comparable to, or even smaller than the wavelength and hence act more like wire grid polarisers which lead to polarisation effects. As of today AIMS^TM fab tools are in operation worldwide, with the novel AIMS^TM fab 193i offering a maximum NA of 0.93 and is the latest aerial image measurement system for ArF-lithography emulation down to the 65nm node. Common adjustments include numerical aperture, illumination type and partial illumination coherence to match the conditions in 193nm scanners. In addition to unpolarised illumination, the AIMS^TM fab 193i allows the user to select linear x and y polarised light for different settings and types, e.g. off-axis annular, quadrupole or dipole illumination. In this paper the polarisation effects of different photomask features are explored by comparing measurement results using linear polarised illumination parallel and perpendicular to line and space patterns and non-polarised illumination. A new scanner mode will be presented for the investigation of contrast loss due to polarisation effects from imaging.

Optical interference leads to errors in the determination of the location of lines and in feature dimension measurements. Multi-peaked focus plots were observed from the metrology tools when the target includes sub-resolution lines. In this paper we present a new algorithm for determining nano-scale feature dimensions of grating structures with a bright-field metrology tool. The algorithm is based on the intensity of images obtained with varying amounts of defocus. By evaluating the variations of the different captured images through analysis of the optical images intensity obtained at various off-focus positions, the through-focus curves experimentally demonstrate nanometer sensitivity with grating structure. An empirical quadratic model was developed to fit the experimental results of image intensity deviation versus critical dimension. Our model and experimental data both shows that the grating structure with critical dimension at half pitch has maximum focus measure. A quadratic symmetry distribution data were shown when the critical dimension increase or decrease with the same dimensional intervals. The results demonstrate that the sub-wavelength feature dimensions can be evaluated using regular optical microscopes with exceptional resolution by implementing this algorithm.

As pattern size is shrinking, required mask specification is tighter and defect on mask is easily transferred to wafer. It is difficult to distinguish a defect what it is and where it is from, even though high NA optic lens is used. According to small pattern size and attenuated PSM material of ArF area, image quality of FIB (focused ion beam microscopy) to repair defect is getting worse. But, recently, SEM (Secondary Electron Microscopy) review tool is used to overcome the limited resolution of optic microscope such as review mode of inspection tool. To use this higher image quality of SEM compared to FIB process, we introduce image processing and replacement to enhance the accuracy of FIB repair on mask pattern. As the image of ion beam generally shows speckle noise, we adopted AND (anisotropic nonlinear diffusion) technology to remove noise without loss of pattern, by different diffusion along pattern edge. Using this AND technique, we enhanced the image quality of FIB and SEM, and productivity of FIB.

In recent years, optical metrology methods, based on spectroscopic ellipsometry (SE), have gained a strong foothold for use in measuring the 2-dimensional profiles of integrated device features. While optical methods generally provide superior metrology performance compared to other metrology methods, there still remain some challenges to meet precision and accuracy requirements as integrated device geometries continue to shrink at an aggressive rate. Process engineers are employing several new techniques in order to meet device patterning requirements while maintaining manufacturing-worthy process windows. These techniques include thinning the photoresist layers and adding additional underlayer films to act as hard masks for subsequent pattern transfer steps. Thinning the photoresist layer reduces the aspect ratio of patterned grating targets, which, in turn, reduces the signal-to-noise (S/N) ratio of the optical profile measurement. The additional films in the process stack below the gratings increase the number of optical interfaces that must be taken into account when building the optical model for the measurement. The increased complexity of the optical model increases the likelihood that there will be cross-correlation between the underlying films and the grating profile parameters (Critical Dimension or CD, Height, and Sidewall Angle or SWA). The reduction in S/N and increase in cross-correlation often have negative impacts on the precision and overall accuracy of the reported values for the grating profile parameters. In this paper, we will discuss a methodology to overcome the issues described above. The methodology involves performing a standard SE film thickness measurement on an open pad area in close proximity to the grating target of interest. The thickness values are then fed forward to a subsequent SE measurement of the grating target. With the underlayer thickness values fixed based on the film thickness measurement, only the grating profile parameters are solved for during the grating measurement. Decoupling the underlayer film measurement from the grating measurement, greatly reduces, and even eliminates cross-correlation between parameters. Both SE measurements are completed with a total move-acquire-measurement (MAM) time that is <10 seconds per pair, and the resulting values reported for CD, Height, and SWA are more accurate when compared to reference metrology such as Atomic Force Microscopy (AFM). Supporting data will be presented from measurements taken on a 65nm technology node gate lithography process. Using the feed-forward process, the correlation and slope of profile parameters measured via SE compared to AFM measurements is greatly improved. Furthermore, systematic anti-correlation between resist height and SWA that was observed during simultaneous measurement of the film stack and grating is eliminated when the film measurement is decoupled and fed-forward into the grating measurement.

As device size is going under the sub-60 nanometer scale, lithography is facing its resolution limit. To solve this resolution limit it has been suggested that one critical device layer could be made from multi photo/etch process, which needs tighter overlay and critical dimension (CD) controls than normal single exposure process. For CD control in this multi photo/etch process, the problem is that we do not know which pattern is made from which photo/etch process after final process. This makes it impossible to measure the specific process pattern's CD independently. In this case the conventional CD measuring method, which measures multi CDs in FOV(Field Of View) of SEM(Scanning Electronic Microscope) and control their average and distribution, couldn't know the average difference between both patterns because the variance from simply measured multi CD is just sum of each variance and their cross terms not including the average difference. In this paper it is pointed out the statistical problem of classical multi CD measurement in the indistinguishable multi-process pattern and a compensative method is suggested with a new statistical formula.

Magneto-resistive Random Access Memory (MRAM), considered the leading candidate for the next generation of universal memory, has moved from research to pilot production. Commercialization of the MRAM devices in mobile computing, cell phones, portable recording and other playback devices, home computing, consumer electronics, enterprise computing and telecommunications, promise to bring in annual revenues exceeding $50 billion during the coming years. CD-SEM correlation of contact physical Critical Dimension to Magnetic Tunneling Junction (MTJ) resistance is critical for MRAM device performance. This paper focuses on a new two-dimensional metric that more accurately characterizes MTJ resistance by calculating total contact area of unique and complex structures. We consider the advantages of the Contact Area metric for measurement of complicated shapes. We illustrate that introduction of the new metric allows for improvement in process control for critical contacts.

With decreasing structure sizes on masks also the acceptable CD variation corridor for printing on the wafer and therefore, the maximum allowed defect size is decreasing. This has not only implications to the accuracy and repeatability of front-end processes such as writers, etchers, etc. but also challenges defect inspection and qualification. Defect qualification is usually done by an AIMSTM tool which optically simulates the aerial image of the structures by applying the same illumination conditions as the wafer fabs' scanners. As lithographers continue to produce smaller and smaller structures, the as well decreasing acceptable design variation pushes the AIMS^TM evaluation step by step towards a metrology method. Thus, an advanced measurement capability of the AIMS^TM tool is mandatory to reliably disposition defects within these small margins. It is influenced by the performance of illumination, imaging homogeneity, and stability. A possible measure for the tool's capability is the (long term) repeatability, i.e. the 3σ-variance of the tool by evaluating the same defect with a certain frequency over several weeks. The AIMS^TM fab 193i platform takes into account the tightened requirements with respect to homogeneity and stability by improved optics such as a new beam homogenizer module, new energy monitoring and vibration isolation concept. In this paper we show data on the long term repeatability compared between the first generation AIMS^TM fab 193SE and the new AIMS^TM fab 193i platform and discuss the implications on the measurement capabilities of the two platforms.

In terms of mass production, the CD variation between exposure tools is not avoidable because of different exposure tool characteristics. The major CD variation is coming from different optical proximity effect (OPE) response between exposure tools. Knowing and control the major contributor to the OPE, ramping up the device will be faster because of one reticle usage in various exposure tools. Therefore, the quantitative measurement and simulation with actual exposure tool characteristics need for analyzing proximity impact to CD. For this purpose, collecting CD data on the wafers and analyzing was carried out to find large ID bias exposure tool. Normal and abnormal exposure tool in terms of proximity matching is inspected using LITEL products of ISI^TM(In-situ Interferometer) and SMI^TM(Source Metrology Interferometer). ISI^TM and SMI^TM were for collecting machine characteristic and Solid-E^TM was for simulation purposes. From this study, the practical procedure is proposed to prevent using of large proximity exposure tool for production line and the impact of actual tools characteristic on proximity matching is known.

Precise measurements of the wavefront aberrations of projection optics with 0.1 nm RMS accuracy are indispensable to develop the extreme ultraviolet (EUV) lithography. In order to study measurement methods, we built the Experimental EUV Interferometer (EEI) that has built-in Schwarzschild-type optics as test optics and was supplied with EUV radiation of 13.5 nm in wavelength from a synchrotron radiation facility as a source light. The EEI can evaluate several methods of EUV interferometory replacing optical parts easily. Those methods are dividable into two categories, namely point diffraction interferometer (PDI) and lateral shearing interferometer (LSI) and those were experimentally compared. Finally, 0.045nm RMS of reproducibility was achieved with PDI method and the residual systematic error after removing specified errors was reduced to 0.064nm RMS excluding axial symmetrical aberrations. In addition, one of LSI-type methods also proved to have almost enough accuracy for the assembly of the projection optics.

Simulation-based scoring of mask defects is useful for technology nodes of 180 nm and below since wafer shapes can be quite different from those on the mask, and therefore not every defect has printing significance. An important issue for simulation-based scoring is calibrating the resist model. Calibration data is scarce for a variety of reasons, among them, (i) the mask shop is not privy to it, and (ii) the reticle-inspection machine may not visit calibration locations. Specifically, while is relatively easy to obtain the target critical dimension (CD) - the intended value of the smallest wafer CD for that mask, the cutline position for that target CD is uncertain. This work focuses on calibrating the simplest of resist models, a threshold, using only knowledge of the target CD. It quantifies the uncertainty in target cutline position with a probabilistic treatment. This shifts the question from, "What is a good threshold?" to, "What is NOT a bad threshold?" The answer is a range of thresholds that does not print sub-resolution features, and that does not grossly distort the ratio of inspection-image CD to wafer CD. Defect dispositioning is then based on the most pessimistic printability score for that threshold range. Given the uncertainty in resist-model calibration, it is appropriate to be conservative and assume the most pessimistic resist threshold.

Lithography in the low k₁ factor regime poses increasingly stringent requirements on the control of critical dimension (CD) of various pitch ratios, also referred to as the OPC (Optical Proximity Correction) curve. Part of the CD budget is consumed by the tool-to-tool variation of the CD metrology tools. Hence, a CD-SEM installed base must be matched for a wide range of pitches within 20% of the OPC litho cell budget. For the 70nm node the matching requirement is 1 nm (20% of 5 nm). Traditionally, scanning electron microscope (SEM) matching consisted of comparing multiple measurements of identical features from different SEMs. The differences found were applied as offsets in the SEMs. These offsets had to be determined for all features. For OPC applications, these features cover a large range of pitches. A full update of the offsets could take a couple of days. An advanced matching methodology has been applied, based upon component wise matching of the SEMs, without the use of matching offsets. This new approach allows to shorten the matching cycle time to a few hours only. A sensitive verification test, using an interlaced sampling scheme on resist layers, proved that better than 0.6nm across pitch matching can be achieved. This matching difference is low enough for successful OPC matching using multiple SEMs from an installed base and is on par with the ITRS and the industry requirement for the 45 nm technology node.

Three significant critical dimension atomic force microscopy (CD AFM) advances are presented in this paper. First, scanning probe image reconstruction methodologies that were formerly limited to parabolic type tip shapes and single-valued surfaces (i.e., non-reentrant topography), are extended to multi-valued surfaces and reentrant tip geometries. This crucial step allows the elimination of image artifacts associated with CD AFM scanning of complex feature shapes using reentrant tips. Second, in situ AFM tip images are provided in an automated tool that enables full image reconstruction. Consequently, for the first time, the combination of in situ tip reconstruction with the inherent reference measurement qualities of the AFM and full morphology reconstruction allow CD AFM metrology essentially free of tip shape effects. CD AFM is now primarily driven by development of tip geometries that contact the entire specimen surface while retaining adequate tip lifetime. The background of CD AFM image dilation is described, and the limitations of "legacy" 1D image reconstruction ("tip width subtraction") are illustrated with idealized probe shapes. Initial validation of the automated software is provided by comparison with TEM micrographs. Tip characterizations are presented for a morphologically complex ~20 nm diameter carbon nanotube tip and reentrant silicon CD32 tips (tip width ~ 30nm). Finally, the capability for CD AFM to scan a reentrant sub-45 nm width trench is demonstrated. An EUV resist trench was scanned with a CD32 tip (tip width = 27.4 nm). Minimum CD ranged from 42 to 45 nm. Reentrant image reconstruction is shown for the scan cross-section.

The classic Bossung Curve analysis is the most commonly applied tool of the lithographer. The analysis maps a control surface for critical dimensions (CD's) as a function of the variables of focus and exposure (dose). Most commonly the technique is used to calculate the optimum focus and dose process point that yields the greatest depth-of-focus (DoF) over a tolerable range of exposure latitude. Recent ITRS roadmaps have cited the need to control CD's to less than 4 nm Across-Chip-Linewidth-Variation (ACLV). A closely related requirement to ACLV is the need to properly evaluate the implementation of Optical Proximity Correction (OPC) in the final resist image on the wafer. Calculation of ACLV and the process points are typically addressed with the use of theoretical simulator evaluations of the actinic wavefront and the photoresist's interactions. Engineers frequently prefer the clean results of the simulation over the more cumbersome and less understood perturbations seen in the empirical metrology data resulting in a loss of valuable process control information. Complexity increases when the analysis assumes a super-positioning of the responses of multiple feature-types in the search for an overlapping process window. Until recently, simulations rarely validated design response to the process and never incorporated the characteristics of the exposure tool and reticle. Fortunately empirical Bossung curve calculations can supply valuable tool, process and reticle specific interaction information if the techniques are expanded through the use of spatial and temporal perturbation models of the actinic image wavefront. In this implementation the classic focus-exposure matrix is shown to be a powerful tool for the determination of optimum focus and focus uniformity across the full exposure field. Although not the tool of choice for pupil aberration analysis, the method is the best implementation for determining the behavior of device critical feature response when the constructs of OPC, forbidden-pitch and inherent reticle variability are involved. Improved process performance can be achieved with algorithms that provide a calculation of the optimum focus ridge whose resulting feature response-to-dose curves are more easily traced to simulation. Response surface models are presented and applied to a calculation of the Best Focus surface for the exposure field. Unlike specialty reticles used in defocus error, the Bossung curve maps the response of the reticle specific feature or OPC design and can provide information on errors induced by the lens/optomechanical system of the exposure tool. The Bossung curve delivers several additional response surfaces needed for proper qualification of any exposure-tool and reticle set. These include the ability to contour-map the critical Feature-Best-Focus surface response across the exposure field of the reticle that accounts for feature and process design variations, the Depth-of-Focus uniformity surface for each critical feature across the full exposure, an Isofocal ridge analysis of the process and the associated process perturbation response and the effective dose-uniformity response needed to achieve target feature size uniformity across the exposure. The Feature-Best-Focus response surface is critical to any systemic analysis because it is the optimum estimation of the reticle feature uniformity without the perturbations induced by exposure defocus. It is shown that when combined in the analysis these techniques provide improved and quick full-field and process-range feature control limit and tolerance calculation for new designs. The exposure limits thus calculated can then provide a realistic and stable process control set for use in the classic process window analysis. Finally, by deconvolving the systemic reticle signature, the original data provides a feature-specific analysis of Dose-Uniformity. The dose-maps created in this step can be linked to local variations in MEEF and can be used for IntraField Dose Compensation in advanced exposure tools.

Scanning Electron Microscope (SEM) has been typical methods for measuring CD of nanopatterns until ArF process was introduced. However in case of ArF process, this method has serious drawback such as shrinkage of organic material by the irradiation of high-energy electron beam. The optical scatterometry system is considered to be promising method for measuring CD due to no damage on organic materials. Sub-80nm node gate was selected because of its measurement stability. CD, profile and thickness are compared with those measured by CD-SEM, cress-section SEM. The correlation degree is shown as GOF, R2, and Profile. Based on merit of speed, easiness and accurate measurement, optical CD method has been applied to CD uniformity. CD uniformity measured by OCD was very similar to that measured by SEM on gate pattern. Based on this result, OCD was applied for the improvement of CD uniformity combined with ASML's does-mapper in technology. We investigated the variation of thickness of organic BARC over topology of various size line and space patterned poly-Si by OCD.

We have developed and proven the viability of a system for massively parallel in-situ sampling of aerial images at the actual wafer plane of a 193nm production scanner, using a wafer-like high-resolution image sensor. The sensor and scanner can be operated under exact production conditions in terms of projection optics, all illumination conditions, laser wavelength and bandwidth, so that the sensor will be sensitive to all effects arising from the interaction of an actual scanner with an actual reticle. We demonstrate the basic image capturing operation of the sensor, using more than 400,000 sampling points across the exposure field, and fundamental capabilities of the system. These include generation of focus maps, line width measurements on the sensor images, sensitivity to sub-resolution features, sensitivity to aberrations, and excellent agreement between experimental data and simulation.

An in-line image quality monitoring system using automated macro-inspection is described. One of the critical problems in reducing yield in CCD manufacture is the production of mura, regions of uneven sensitivity in the device. In this paper, an in-line mura-related yield monitor is presented using the recently developed Tokyo Aircraft Instrument Company EDIS-3000 Automated Macro-Inspection system, which has a high sensitivity and a high resolution optical module developed by IBM^TM Japan. The optical module is designed to focus on reflected light from the pattern edge, not on the traditional diffracted light, so it is expected to register the linearity between the wafer CD and the wafer image. This system is expected to reduce yield loss, resulting in a faster time-to-market for imaging devices.

Bright field imaging based metrology performance enhancement is essential in the quest to meet lithography process control requirements below 65 nm half pitch. Recent work has shown that, in parallel to the lithographic processes themselves, the metrology tools are able to continue to perform despite the fact that the size of the features under test are often below the classical Rayleigh resolution limit of the optical system. Full electromagnetic simulation is a mandatory tool in the investigation and optimization of advanced metrology tool and metrology target architectures. In this paper we report on imaging simulations of overlay marks. We benchmark different simulation platforms and methods, focusing in particular on the challenges associated with bright-field imaging overlay metrology of marks with feature sizes below the resolution limit. In particular, we study the dependence of overlay mark contrast and information content on overlay mark pitch and feature size.

The use of carbon nanotubes (CNT) as probes for atomic force microscopy (AFM) has been studied worldwide for more than a decade; however, the industries have not widely accepted CNT probes in their day-to-day operation. In this work, we present a series of studies on the metrology performance of CNT probes in semiconductor industry. A total of 54 CNT probes were studied for tip geometry, and 11 probes were tested on production wafers from a variety of IC manufacturers. Five out of the 11 probes were further evaluated for tip lifetime in semiconductor manufacturing environments. Statistical measurement data and tip shape characterization results provide insights on the applications of CNT probes in microlithography process control. The recent advancements in AFM scan algorithms that enable the control and use of CNT probes were also discussed in this paper. Sidewall measurement data using tilted CNT probes, and the AFM image of a CNT probe showing a comparable resolution to that of transmission electron microscopy (TEM) were presented for the first time. The combination of advanced AFM system and CNT probes has proven to perform challenging metrology in 65 nm node and beyond.

Scatterometry is one of the few metrology candidates that has true potential to analyse submicrometer critical dimension (CD). This physical constraint restricts initially the scalar theory of diffraction (Kirchhoff, Fraunhofer), where no computation is needed, to describe pattern with such characteristics. Now many techniques based in a rigourous analysis of diffraction (were polarisation is considered) are developped (RCWA), however these vector theory would be difficult to apply in real time due to time consuming by computation. For that reason, we push here scattering measurement of isolated lines, in the limit of the scalar theory. We use the scattering mode of SOPRA's GESP 5 instrument, which measure separately TE and TM polarisations.

We compare substrate current (SC) values for thin SiO₂ films, with thicknesses ranging from 2 nm to 200 nm, between modeled simulation results and actual measurements made by EB-SCOPE, a substrate current measuring instrument. The simulation models use Monte Carlo methods to model the generation of secondary electrons (SE) and holes, and use 1-D charge transfer to simultaneously model SE yield and SC values to quantify thin film thickness in order to predict if a high aspect ratio contact or via hole is closed or open. The simulation results show a strong match with the measurement data. The SC value can be used for assessing process uniformity as well as detecting process related failures, in this case a closed contact hole which can be seen in the qualitative SC images. We can also apply this modeling to monitoring of surface preparation and clean processes to detect residual films such as SiO₂. The method can detect changes in surface state conditions, such as residue or oxide formation, as changes in SC values.

Resolution enhancement techniques (RET), immersion lithography, and Design for Manufacturing (DFM) are all geared towards increasing the lithographic process window to enable the ever more difficult processing demands of semiconductor manufacturing. It is well understood that there is a trade-off between depth of focus (DOF) and exposure dose latitude (EL), as well as best focus (BF) and best exposure dose (BE), in which a Manufacturable Process Window (MPW) must be established and centered. Oftentimes it is overlooked that this balance needs to be maintained across multiple dimensions including spatial (e.g. across field), density (e.g. dense, iso), temporal, tool-to-tool, etc. To maintain this critical balance, both test wafers and product wafers need to be monitored and analyzed in order to support Advanced Process Control (APC) and Automated Equipment Control (AEC). In this work we establish a method to optimize process window by using an integrated analysis workstation based on measurements from both optical and e-beam metrology. By applying this method, we demonstrate a MPW on daily FEM and nominal wafers already used at IMEC for daily process qualification.

The minimum feature size of new generation memory devices is approaching down to 50 nm era. And a very precise CD control is demanded not only for cell layouts but also for core and peripheral layouts of DRAM devices. However, as NA of lens system grows higher and higher and Resolution Enhancement Techniques (RETs) becomes more and more aggressive, isolated-dense bias increases and process window for the core and peripheral layouts decreases dramatically. So, the burden of OPC increases in proportion and it is requisite to verify as many features as possible on wafer. If possible, it would be desirable to verify all the features in a die. Recently, a novel inspection tool has been developed which can verify all kinds of patterns on wafer based on Die to Database copmarison method. It can identify all the serious systematic defects of nm order size error from the original layout target and feed back the systematic error points to OPC for more accurate model tuning. In addition we can obtain the full field CD distribution diagram of some specific transistors with hundreds of thousands of measurement data. So, we can analyze the root cause of the CD distribution in a field, such as mask CDU or lens aberrations and so on. And we can also perform Process Window Qualification of all the features in a die. In this paper, OPC verification methodology using the new inspection tool will be introduced and the application to the analysis of full field CD distribution and Process Window Qualification will be presented in detail.

The next nodes in immersion lithography will require to use the 193 nm laser line with very large numerical aperture and a liquid between the optics and the resist¹. Immersion lithography at 193 nm requests very specific parameters for the fluid. The first generation will use the De-Ionized Water (DIW) very pure and not recycled, but when a new optical material for last lens will be available with a refractive index (RI) larger than 1.85, a higher refractive index fluid can be used, enabling second and maybe third generation of immersion lithography at 193 nm. So the 45 and maybe the 32 nm nodes could be covered with this High Index Fluids (HIF).

In the 65nm process development, use traditional top-view SEM and off-line XSEM and TEM to monitor STI profile became insufficient and inefficient. How to find one non-destructive, in-line monitor method to monitor trench depth, step height, and micro-planarity of STI (Shallow Trench Isolation) module profile become more important and challenge than before. In-line AFM just cover this challenge during 65nm process development stage. In this paper, we report how to use in-line Atomic Force Microscope (AFM) technology to monitor STI module profile. Use of this technology on profile step-height and critical dimension in production facilities offers superior precision, accuracy, non-destructive. high throughput and cost effective measurement result. Meanwhile, this paper outlines the implementation of AFM based metrology in an automatic production facility. We focus on the process step just after nitride removed, two key applications on this step, one is to monitor the step height difference and the other is to monitor divot depth at the interfaces height difference between the active area and the isolation area within the STI module. Because the STI step height and divot after oxide fill might dominate the device threshold voltage value(Vt), we check the step height and divot of STI from SiN removed step to the step of thin gate oxide AEI. Then we check and trace where these defect occurred. We also measured 11 points on 300mn wafer to come out one wafer-level topographic chart to monitor its cross-wafer uniformity. Besides, we compared and correlated the AFM measurement result with FA TEM data. It shows good correlation result between X3D AFM and FA TEM. It means this in-line measurement method could efficient act as one important role on advanced STI module process development.

Scatterometry is a fast, non-destructive critical dimension (CD) optical metrology technique based on the analysis of light scattered from a periodic array of features. With technological advances in manufacturing, semiconductor devices are made in ever shrinking geometries. In recent years, the ability of scatterometry metrology tools to measure these devices at a gage-capable level for parameters such as CD, thickness or profile has become more challenging. The focus of this research is to analyze the acquired diffraction signature and determine an optimum diffraction signature "scan path." An optimized scan path can result in higher precision, reduced development time, smaller pre-generated library databases and faster real-time optimization speeds. In this work, we will first review several methods for scan path selection and optimization. Our results indicate that the method choice can influence the scan path selection, and that some of the methods are complementary to one another. For example, one method, which we term orthogonal sensitivity, uses intelligent algorithms to select optimal scan path points based on enhancing single parameter sensitivity. While the method works well, it neglects parameter correlation effects. Thus, we will also review a method where correlation effects are considered. Finally, we will calculate and summarize the effectiveness of optimal scan path selection techniques using challenging lithography applications.

Immersion lithography has been intensively developed to print features, such as isolated lines and isolated spaces, which are smaller than 35 nm, with good depth of focus at a vacuum wavelength of 193 nm. Because the wavelength of the light in a liquid is reduced from the vacuum wavelength, the numerical aperture, i.e. the resolution (lambda/2NA) can be improved by a factor of the index of refraction of the liquid. At the end of 2005, Nikon scanner achieved 47nm L and S pattern. In order to utilize daily this performance of the immersion lithography apparatus with well-defined resolution enhancement technique in factory to its maximum content, optical parameters such as lens aberration, illuminator NA, pupil-fill annular ratio, and polarization status are to be measured and controlled more accurately than ever. To meet that need, an integrated projecting optics tester (iPot) for an in-situ inspection of wavefront aberration with calibration method to achieve high accurate measurement has been developed. The performance meets the required 47nm L&S pattern while the numerical aperture of immersion projection lens is larger than 1. The deviation between the averaged absolute value of the Zernike coefficient was 0.0022 lambda (0.42 nm). The deviation of the averaged absolute value of the coefficient in the scanned field is 0.0010 lambda (0.19 nm). Measured ratio of specific polarization (RSP) values of H and V polarized illuminated sections are 0.974 and 0.973, respectively. Projection lens with the low birefringence designed value is consistent with the measured value of RSP and the wavefront illuminated by linear polarizing light.

A micro-electromechanical system (MEMS) was designed by following the saggital principle of motion amplification about an output direction which is perpendicular to the input direction. Several displacement-amplification microdevices have been fabricated by means of the PolyMUMPS microtechnology. The experimental testing of these electrostatically-actuated, electrostatically-sensed micromechanisms monitored the output motion by means of a highly-compliant, integrated cantilever, as well as by a vernier system, and revealed that the performance is less than predicted, in some occasions the errors between the defect-free model predictions and the experimental results being quite substantial. This system integration, sensory monitored discrepancy lead the effort of identifying and quantifying the influence of various factors in the less-than-expected response of these compliant micromechanisms. Discussed are the effect of non-parallel disposition of the mobile structure with respect to its substrate, the non-planar shape of the microdevice, which produces at times rubbing or adhesion against the substrate, various misalignments between fixed and mobile components, as well the resulting fringe effects, which sizably hamper the operation of the comb or plate electrostatic sensory actuation. It is demonstrated that by combining all these unwanted effects, which are either inherent to the small-dimensions microdevice, or are simply errors of the microfabrication process, it is possible to account for the experimentally-observed response and create a predictive error-inclusive model of the system.

Overlay accuracy is a key issue in the semiconductor manufacturing process. To achieve overlay requirements, we developed compensation functions, i.e. Enhanced Global Alignment (EGA), Super Distortion Matching (SDM), and Grid Compensation for Matching (GCM). These functions are capable to reduce all the components except local linear components caused by a wafer global deformation. In this paper we introduce a novel correction framework which includes new compensation function called Shot Correction by Grid Parameter; thereby enabling further enhancements to overlay. Using this novel framework, we show both simulation and experimental data demonstrating improved overlay accuracy.

The IBM 300 mm wafer manufacturing line provides a case study for the optimization of an automated macro defect inspection system to accurately flag global wafer color variation. The IBM inspection system was falsely flagging a large number of wafers primarily for global wafer color variation, leading to unacceptable amounts of production volume being placed on hold. A review of the macro inspection system identified several areas for improvement. An investigation into the installed hardware base found a panel behind the beam splitter was introducing noise through reflected light. This panel was replaced with a less reflective material. A review of the failed wafers found that maximum light levels were not achieved across all tools and an improved diffuser plate for the fiber optic output was designed to improve light transmittance. Global wafer color is determined by comparing the scanned wafer image to a "golden" data set, referred to as a "color baselist," which is composed of data from 30 wafers. A review of the recipe baselists revealed that some of the wafer samples did not accurately represent process conditions, and new wafer samples were collected. Finally, a tool-to-tool matching test revealed that the set of weightings given to each of the color parameters in the baselists was not optimized. After implementing the above changes, false global wafer color failures were virtually eliminated.

Critical dimension (CD) metrology is an essential part of the mask manufacturing process. We present a metrology solution based on broadband reflectometry, covering a wavelength range from 190 to 1000 nm, in one nanometer intervals. The analysis is performed using Forouhi-Bloomer dispersion equations, in conjunctions with Rigorous Coupled Wave Analysis (RCWA). The method provides accurate and repeatable results for critical dimensions, thickness, and optical properties (n and k spectra from 190 - 1000 nm) for all materials present in the structure. In terms of throughput (several seconds per point) and suitability for integration, the method has many advantages over conventional metrology techniques. Measurements were performed on two masks, at two different stages of the mask manufacturing process - After Etch Inspection (AEI) and After Strip Inspection (ASI). CD uniformity distribution maps at 121 points on the mask were obtained for 800 nm pitch grating arrays. The results were compared to conventional CD-SEM measurements collected at the same locations. A linearity study was conducted on 760 and 1120 nm pitch grating arrays with systematically increasing CD width. The results demonstrate excellent correlation with CD-SEM.

IC manufacture has to meet stringent requirements pushing the imaging tools beyond their limits. The key performance attribute of the imaging tool is the quality of the image projected on wafer plane. The image quality is controlled by the wavefront aberrations present in the projection lens pupil. Therefore the quality of the lenses can be represented by either various image quality metrics or by the data on the lens pupil aberration residua. Projection lens quality can be quantified by interferometers capturing the lens pupil residual aberration, leading to estimates of the image quality. These various techniques can be used off-line, testing projection lenses installed on a dedicated test bench, used during or after lens manufacture, or in-situ, testing the lenses installed in the projection tools, often at the IC manufacturing floor. These techniques have inherent tradeoffs in terms their accuracy, portability, ease-of-use and completeness of the aberration and imaging metrics. Such tradeoffs determine which technique is the most appropriate for various applications ranging from lens quality control during imaging tool manufacture, to tool qualification during its installation and setup, to tool monitoring and tuning during the IC manufacture. It is acknowledged within the scanner engineering community that qualification and maintenance of tools used for critical level pattering requires in-situ lens monitoring technique. Such method would also help to select and to fine tune the imaging tools to design-specific requirements of IC critical patterns. A preferred method of aberration monitoring should be highly compatible with routine scanner operation and should be independent of resist process conditions. This paper presents aerial image-based technique to monitor and to diagnose the quality of projection lenses used in scanners. The method involves aerial image sensor, AIS. We start with a discussion of the fundamental principles of operation and the key design issues impacting the accuracy of the technique. We follow with an examples of the AIS aberration test. These tests lead to a discussion of the method's capabilities to quantify the performance of the imaging tools.

Defects on the backside of a wafer during processing can come from many sources. Particles and scratches on the backsides of wafers can be caused by wafer handling equipment such as robots and chucks, as well as by CMP processes. In addition, cross-contamination of wafers and handling equipment can occur when wafers move from tool to tool, through the production line. When wafers are exposed, backside defects can cause localized areas of poor lithography pattern resolution on the frontsides of wafers, resulting in increased rework rates, decreased throughput, and yield loss. As minimum feature sizes continue to shrink with each new technology node, devices become denser and exposure tool depth of focus decreases - making the elimination of lithography hot spots an even more critical issue. At a major worldwide IDM, automated macro defect inspection tools for integrated front, edge, and backside inspection have been implemented to inspect wafers at several After Develop Inspection (ADI) and post-etch inspection steps. These tools have been used to detect foreign material and scratches on the backsides of several lots that were caused by another process tool, causing photolithography hot spots. This paper describes advanced macro inspection of wafer front and back surfaces and how the inspection data was used to correlate backside defects to photolithography hot spots, and take corrective action.

We describe the use of multifunctional perfluoropolyethers as enabling materials in imprint lithography and metrology. Perfluoropolyethers (PFPEs) are a unique class of fluoropolymers that are liquids at room temperature that can be functionalized and cured to form transparent "PTFE-like" elastomers. These materials posses many favorable attributes relative to imprint lithography and other soft lithographic techniques including: chemical resistance, flexibility, incredibly low surface energies, high gas permeability, and UV transparency. Molds made from PFPE materials exhibit the favorable properties of both rigid and soft materials in that they are rapidly made and disposable, yet maintain the chemical resistance and performance of rigid materials such as quartz. We have previously demonstrated the use of such materials in patterning 70nm features with a precision of +/-1 nm. Herein, we further demonstrate the capability of these materials in the rapid patterning of dual damascene structures and other patterns. The chemical resistance of PFPE-based materials allows for the patterning of a variety of organic resins including etch resists, low-k dielectrics, and conducting polymers. Additionally, we demonstrate the utility of functional PFPEs in a novel metrology method. In this simple technique, the liquid PFPE precursor is poured onto a wafer with a given pattern and cured. When released from the wafer, the cured film possesses an exact negative replica of the original pattern. A variety of metrology and inspection methods can then be performed on the patterned, transparent film including microscopy and through-film optics which can reveal defects in the original pattern. Furthermore, the method is shown to be completely non-destructive to the original patterned wafer. We describe the use of this method in the metrology and inspection of a dual damascene pattern containing features which are difficult to characterize by other techniques.

As reticle line widths shrink and RET complexity increases, even a single sub-micron defect can reject a photomask. High-end reticle manufacturers striving for increased yield and reduced cycle times are relying on low incoming rawstock defect levels and handling via SMIF mini environments for critical manufacturing steps. However, even in SMIF compatible reticle fabs, human handling is often required to load or unload a reticle to/from a SMIF environment. In an effort to provide a fully integrated solution to manufacturing 65 nm and below photomasks, Photronics has introduced a blank inspection/management system developed by Hitachi High Technologies and Fortrend Engineering. The clustered system is capable of robotic transfers in conjunction with blank storage, inspection, and material tracking capabilities. It consists of four major systems: a horizontal mask blank transfer system with state-of-the-art blank sorting capability, an integrated Hitachi GM3000 Mask Blank Surface Inspection System, a totally self-contained and sufficient Mask Blank Storage Station, and a material logistic control software system for material management and SPC. The Fortrend Lamina sorting system has a bright light inspection module for gross particle contamination detection, and a robotic transfer module for mask exchanges between SMIF and other shipping/transport boxes employed in the mask manufacturing facilities. The clustered Hitachi inspection system is an integral part of the solution allowing for additional inspections of stored and incoming blanks by optically detecting foreign particles and pinholes. The data is transferred and stored in the Foretrend handling system control module and may be used for rawstock management and screening based on a predefined criteria. The integrated system provides a total solution to mask manufacturing challenges at 65 nm and below.

The problem of enacting an effective Advanced Process Control (APC) system is herein discussed [1]. The schematic structure of the system is represented below: (please see manuscript). The creation of such a system with a communication link between the mask designer and lithography and process engineering of consequent operations can be broken down into two problems: 1. Organization of the interaction of services performed by APC. 2. Reliability of the measurement information obtained in SEM CD metrology. We will focus on the second problem. The effectiveness of the operation of the APC system depends on the reliability (precision and accuracy) of the measurement outcomes.

A small lot Automated Material Handling System (AMHS) is presented as a method to reduce the time between wafer exposure at a photolithography tool and collection of metrology / inspection data. A new AMHS system that is capable of the move rates required by small lot wafer transport is described, its implementation in a photolithography bay is explained, and the resulting reduction in metrology delay time is quantified. In addition, a phased implementation approach is described in which some, but not all, components of the new AMHS would be installed in existing fabs to enhance the move rate capability of traditional overhead transport (OHT) AMHS systems. This partial implementation would enable a partial lot size reduction and corresponding metrology delay time reduction of 60-70%. The full AMHS solution would be installed in new fabs and enable true small lot manufacturing in the litho area and would result in the maximum delay time reduction of 75-85%.

This paper describes some of the results collected during the study of improved purification materials, qualification of regenerability performances and newly developed ways to detect Acids, Bases and Siloxanes at the sub-ppt levels. Removal validation down to single ppt levels has been demonstrated for several impurities such as: NH₃, SO₂ and Hexamethyldisiloxane (HMDSO).

A high-throughput e-beam monitoring system, eProfile®, is designed to quickly measure gray level value (GLV) and critical dimension (CD) of the structures of interest on product wafers. Two wafers are used in this study, one wafer is at after etch inspection (AEI) with contact mask focus exposure matrix (FEM), and another is normal exposure contact AEI wafer. High-throughput CD measurement of AEI wafer at holes with different patterns, such as semi-dense and SRAM array were measured with results matched the FEM expectation very well. The system is also be used to measure GLV of the SEM images on contact holes of a normal production wafer to reflected the under etch (high GLV) problem in a semi-dense hole pattern.

Naturally occurring outbreaks of bacteria have the potential to contaminate process water used in semiconductor manufacturing. Bacteria are normally filtered out in the water treatment process, however contamination can still occur from biofilm growth, filter or media break-through, and air vectors. Because there is seldom a residual disinfectant and system sanitation is intermittent, the manufacturer must rely on point of use filters to prevent contamination at critical points in the process. Particle counters in the distribution system can tell when the number of particles is increasing but cannot discriminate bacteria from small silica particles and often are unable to detect smaller gram-negative particles. If an on-line multi-angle light scattering system is used in place of particle counters or in conjunction with them, then the discrimination between silica particles and bacteria can be made and the proper action taken in the distribution system to help identify the contamination source, improve preventative maintenance, and ultimately increase yields. This paper describes the multi-angle light scattering method of detecting bacteria with the BioSentry^TM system to provide an effective real-time on-line water monitoring sensor.

We developed the electron beam inspection system based on projection electron microscopy (EBI-PEM), and then applied this system to inspection of mask defects. Usually, inspection of mask defects (such as monitoring of growing defects) is carried out with resist pattern on Si wafer by using an optical inspection tool. In recent years, the shrinking of the design rule for LSI devices has fueled demand for mask inspection for small defects, which are hard to detect with the resolution of an optical inspection tool. Therefore, a high-resolution electron beam inspection tool is desired. However, conventional electron beam inspection systems based on scanning electron microscopy (EBI-SEM) require very long inspection time (10-100 times longer than in the case of optical inspection tool) and inspection costs are very high. In addition, it is difficult to inspect resist pattern by using an electron beam inspection tool, because of the charge- up problem. In order to solve the problem, we examined a new mask inspection method using an electron beam inspection system based on EBI-PEM. Although, EBI-PEM have an advantage in terms of inspection speed, it is more difficult to inspect resist pattern by EBI-PEM than by EBI-SEM, because EBI-PEM is very sensitive to charge-up of a sample surface. Therefore, we tried a method in which inspection is performed after transferring a pattern to SiO₂ thin film formed on Si wafer. By optimizing the thickness of SiO₂ thin film and the electron beam condition of EBI-PEM, we were able to minimize the influence of charge-up and obtained a higher contrast image. Using this method, EBI-PEM achieved inspection sensitivity of 35nm in the case of programmed defect wafer. We confirmed the probability of realizing high-speed and high-resolution mask inspection by using EBI-PEM.

First, we establish numerical calculation techniques for the three-dimensional arbitrary cross section measurement equipment production using oblique incident light waves. In the 3D analysis, the enormous calculation times are problematic to analyze arbitrary cross sections using the FDTD (Finite Difference Time Domain) methods. Then, the sub-grids are used for the time shortening analysis. The sub-grid methods are carried out by the adoption to change the cell dimensions in some specific regions. The multilayer thin film parts are necessary to use the small lattice because we had to deal with the small shape changes. Second, the Gaussian beam incidence analysis for non periodic and isolated grooves is examined. The spot beams are needed for the analysis of the 3D isolation grooves. The scattering characteristics are examined using the spot size of 0.2-1.0 microns. Third, the cell size in the FDTD method must be small enough (