Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of equipment for mask fabrication. This year's assessment is the third in the current series of annual reports and is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the mask industry. This report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results may be used to guide future investments on critical path issues. This year's survey builds upon the 2003 survey to provide an ongoing database using the same questions as a baseline with only a few minor changes or additions. Questions are grouped into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery times, returns and services. Within each category are a many questions that create a detailed profile of both the business and technical status of the mask industry. This assessment includes inputs from ten major global merchant and captive mask manufacturers whose revenue represents approximately 85% of the global mask market.

The introduction of extreme ultraviolet (EUV) lithography into high volume manufacturing requires the development of a new mask technology. In support of this, Intel Corporation has established a pilot line devoted to encountering and eliminating barriers to manufacturability of EUV masks. It concentrates on EUV-specific process modules and makes use of the captive standard photomask fabrication capability of Intel Corporation. The goal of the pilot line is to accelerate EUV mask development to intersect the 32nm technology node. This requires EUV mask technology to be comparable to standard photomask technology by the beginning of the silicon wafer process development phase for that technology node. The pilot line embodies Intel's strategy to lead EUV mask development in the areas of the mask patterning process, mask fabrication tools, the starting material (blanks) and the understanding of process interdependencies. The patterning process includes all steps from blank defect inspection through final pattern inspection and repair. We have specified and ordered the EUV-specific tools and most will be installed in 2004. We have worked with International Sematech and others to provide for the next generation of EUV-specific mask tools. Our process of record is run repeatedly to ensure its robustness. This primes the supply chain and collects information needed for blank improvement.

The increase of MEEF(Mask Error Enhancement Factor) as well as the life prolonging of the ArF lithography with low k1 makes the demand for the mask quality more and more severe . Alt-PSM (Alternating Phase-Shifting Mask) is one of the most effective approaches to the resolution improvements of the ArF lithography. In addition, the improvement of MEEF can be expected in Alt-PSM . In this study, firstly Alt-PSM was manufactured containing programmed phase defects. The programmed phase defects are variable type and multiple phase angles. The phase differences of these defects are 180,120 and 60degree. Two types of chrome line width were placed (280nm and 400nm) with four different pitches (1:1.1:1.5,1:2,1:5). Two programmed phase defects type (divot and bump) placed on isolated and on edge. The printability of the phase defect was evaluated by using Aerial Image Measurement System (AIMS-fab193 of Carl Zeiss Co.) In this study, the printable defect was defined to be a defect, which CD error size is within +/-5% and DOF was +/-100nm on wafer. And, the defect detection capability was confirmed by using TeraScan( KLA-Tencor Co.) Finally, the real existence situation of the natural phase defect in imitated 65nm node production mask was estimated by using TeraScan with optimized inspection condition. In addition, the detected phase defect verified the printability. As a result of this verification, it turned out that a practical inspection was possible of Alt-PSM for 65nm technology node.

The paper presents the results of a study to define a production-worthy inspection technique for subresolution solid and hollow scattering features used in 193-nm lithography. Masks are inspected using conventional high-NA and aerial-imaging-based mask inspection tools. Inspection results are compared regarding capture rate and nuisance defect rate.

This article presents the evolution of the first fully automated simulation based mask defect dispositioning and defect management system used since late 2002 in a production environment at Intel Mask Operation (IMO). Given that inspection tools flag defects which may or may not have any lithographic significance, it makes sense to repair only those defects that resolve on the wafer. The system described here is a fully automated defect dispositioning system, where the lithographic impact of a defect is determined through computer simulation of the mask level image. From the simulated aerial images, combined with image processing techniques, the system can automatically determine the actual critical dimension (CD) impact (in nanometers). Then, using the product specification as a criteria, can pass or fail the defect. Furthermore, this system allows engineers and technicians in the factory to track defects as they are repaired, compare defects at various inspection steps and annotate repair history. Trends such as yield and defect commonality can also be determined. The article concludes with performance results, indicating the speed and accuracy of the system, as well as the savings in the number of defects needing repair.

CPL^TM Technology is a promising resolution enhancement technique (RET) to increase the lithography process window at small feature line widths. Successful introduction of a reticle based RET needs to address several reticle manufacturing areas. One key area is reticle inspection. A CPL reticle inspection study has been completed and a best known methodology (BKM) devised. Use of currently available inspection tools and options provides a robust solution for die-to-die inspection. Die-to-database inspection challenges and solutions for optically completed CPL reticles are discussed. Core to the devised BKM is the concept of in-process inspections where the highest sensitivity inspection may not necessarily be performed after the last manufacturing step. The rationale for this BKM is explained in terms of actual manufacturing process flow and most likely defect sources. This rationale also has implications for programmed defect test mask designs in that the choice of defect types need to be linked to a plausible source in the manufacturing process. Often, the choice of a programmed defect type ignores the fact that a naturally occurring defect's origin is early in the manufacturing process and would be detected and either repaired or the reticle rejected before subsequent manufacturing steps. Therefore, certain programmed defect types may not be representative of what should be expected on a production mask. Examples such defects are discussed.

In this study, A new inspection system with Nd:YAG laser beam has been developed to detect defects on blank mask and particles from process and handling. The development of new reflective image and optic system increased inspection speed for advanced Cr, PSM and Quartz substrate. Through easy operation and defect classification, the productivity of inspection and particle control on mask process was increased. With this new inspection system, defects on blank mask was classified and evaluated after patterning process. As a process monitoring tool, defects from all mask process equipments have been evaluated and monitored with different microscopy and metrology tools to identify and characterize them on various steps. Our results demonstrate that this process monitoring is very effective to identify defects and their sources, and to prevent mask reject caused by defect of each process.

At the challenging ground rules required for 90 nm and 65 nm photomask production, new types of photomask defects are becoming increasingly prevalent. This paper discusses one particular new defect type found on critical 90 nm embedded attenuated phase-shift masks (EAPSMs). These defects had varying transmission characteristics depending on the wavelength used for analysis. Given that photomask inspection wavelength has historically lagged behind lithography wavelength, this type of defect can go undetected and poses a grave risk to wafer lithography yield. Detection and characterization methodologies will be presented along with aerial image analysis and wafer print evaluation results.

With ever shrinking k1 lithography, overall reticle quality is paramount to ensure high quality image transfer. State-of-the-art reticle inspection systems play two vital roles in reticle manufacturing: quality assurance and manufacturing process feedback. For quality assurance, the system must be capable of detecting all defects of interest to the end user - defects that repeatedly print on wafer, and also those that may reduce the lithography process window. For process monitoring and improvement, the system must be capable of detecting defects at or near the manufacturing limits of mask manufacturing. In order to meet both needs, an inspection system must detect all defect types including pattern errors and contaminates on all mask surfaces including chrome, quartz, and shifter materials. A new advanced inspection method compares both transmitted and reflected light images to the design database. This comprehensive inspection method detects numerous defects that would be missed in a transmitted or reflected only inspection tool. In this study we have tested a new method for detecting reticle defects. Inspection results will be shown from a programmed defect test vehicle as well as a production reticle.

DUV lithography has introduced a progressive mask defect growth problem widely known as crystal growth or haze. Even if the incoming mask quality is good, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught in advance during production in the fabs. The ideal reticle quality control goal should be to detect any nascent progressive defects before they become yield limiting. So a high- resolution mask inspection is absolutely needed, but then the big question is: "how often the fabs need to re-inspect their masks"? A previous work towards finding a cost effective mask re-qualification frequency was done by Vince Samek et al. of IBM and Dadi Gudmundsson et al. of KLA-Tencor in 1999 [1], but this work was prior to the above mentioned progressive defect problem that industry started to see at a much higher rate during just the last few years. In this present paper a realistic mask re-qualification frequency model has been developed based on the data from an advanced DRAM fab environment that is using low k1 lithography. Statistical methods are used to analyze mask inspection and product data, which are combined in a stochastic model.

Mask making yield is seriously affected by un-repairable mask defects. Up to now, there is only one size specification for critical defects, which has to be applied to any defect found. Since recently, some mask inspection tools offer the capability to inspect different features on one mask with different sensitivity. Boolean operations can be used to segregate mask features into more and less critical. In this paper we show the MEEF (Mask Error Enhancement Factor), which determines from the mask / wafer pattern transfer the actual effectiveness of mask errors, as an objective and relatively easily determinable parameter to assess the printability of mask defects. Performing OPC, a model-based OPC tool is aware of the MEEF, and can also provide the capability for the additional information handling, which is needed to supply the mask maker with a set of data layers of different defect printability for one mask layer.

The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. Design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect. Design for manufacturing (DFM) techniques verify and alleviate complex interactions between design and process. DFM can be applied at various stages in your design-to-silicon flow. We will discuss how these DFM methods are applied and implemented at Cypress. We will also show how design rules are defined and present several methods for injecting OPC/RET awareness into the designs prior to mask manufacture.

Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.

The ability to transfer designs with high fidelity onto photomasks and then to silicon is an increasingly complex task for advanced technology nodes. For example, the majority of the critical layers for even the 130nm node are patterned by sub-wavelength photolithography; therefore, the numerical aperture, illumination condition, and the resist process must be optimized to achieve the necessary resolution. The reticle, as a bridge between design and process, has become very complex due to the extensive application of resolution enhancement technologies (RETs). As the complexity of RETs increases, the final mask data can be vastly different from the original design due to a series of data manipulations. Optimizing the reticle layout plays the pivotal role in design-for-manufacturability (DFM) considerations. In this paper, we will discuss how design rules must accommodate the needs of Optical Proximity Correction (OPC) and Phase-shifting Masks (PSM). The final layout on a mask after extensive polygon manipulation must also meet the capability and manufacturability of mask writing, mask inspection, and silicon processing. We will also discuss how the wafer fab's perspective can affect the mask shop. Throughout the discussion, we will demonstrate that the integration at mask level and the collaboration of design, RET, mask shop, and wafer fab are key to DFM success.

A new chrome etch system was acquired and implemented to manufacture 65 nm node critical level masks. The etch performance of FEP 171, ZEP 7000, NEB 22, and REAP 200 resist systems in this new chrome etch system was evaluated. The critical dimension (CD) uniformity, etch bias, and etch linearity of this new etch system relative to the older generation etch system is presented. Implementation of the new etch system resulted in a 40-60 nm reduction in etch bias with no degrade in CD uniformity performance. In addition, it was found that the etch contribution to CD linearity was reduced by 50%. Detailed characterization of both macroloading and microloading etch effects was performed and showed substantial improvement relative to the previous generation etch system. The change in chrome etch rate as a function of etch area was reduced by 50%, improving mean to target CD performance on new designs. Implementation of the new etch system has enabled achievement of CD and defect density performance requirements for 65 nm node mask manufacturing. The results presented in this paper were collected during the process development phase and are not necessarily representative of the final optimized process.

A new chrome etch system was acquired and implemented to manufacture 65 nm node critical level masks. The etch performance of FEP 171, ZEP 7000, NEB 22, and REAP 200 resist systems in this new chrome etch system was evaluated. The critical dimension (CD) uniformity, etch bias, and etch linearity of this new etch system relative to the older generation etch system is presented. Implementation of the new etch system resulted in a 40-60 nm reduction in etch bias with no degrade in CD uniformity performance. In addition, it was found that the etch contribution to CD linearity was reduced by 50%. Detailed characterization of both macroloading and microloading etch effects was performed and showed substantial improvement relative to the previous generation etch system. The change in chrome etch rate as a function of etch area was reduced by 50%, improving mean to target CD performance on new designs. Implementation of the new etch system has enabled achievement of CD and defect density performance requirements for 65 nm node mask manufacturing. The results presented in this paper were collected during the process development phase and are not necessarily representative of the final optimized process.

Alternating Aperture Phase Shift masks (alt-APSM) are being increasingly used to meet present day lithography requirements by providing increased resolution. The quartz dry etch is a critical step in the manufacture of these photomasks. Etch depth linearity, phase uniformity and minimum etched surface roughness are critical factors. To achieve this, etched quartz structures need to have good selectivity to resist / chrome, vertical sidewalls and good etch depth uniformity over the mask area. Using the Mask Etcher IV at Unaxis USA, a series of experiments were performed to study and identify the trends in quartz etching for photomasks. Etch depth uniformity was measured using an n&k1700RT and etch depth linearity from feature sizes ~0.4 micron to ~1.4 micron was measured using an AFM. Cross sections of the ~0.6 micron structure were obtained using a SEM to check for profile and any evidence of micro trenching. After several set-up experiments, an optimized process to minimize etch depth linearity and improve etch depth uniformity was obtained and is presented here.

Dry etch in maskmaking is one of the major contributors to variation of critical dimensions (CD) which is caused primarily by the microloading and macroloading effects. CD variation during etch depends on the type of pattern involved. It would be highly desirable to run a pattern through the software to predict CD variation due to dry etch and decide if the variation is within the prescribed tolerance or if the pattern needs additional correction, and to what degree. In this paper, a dry etch simulation tool TRAVIT is introduced that is capable of simulating etch profile, CD, and CD errors. Using a set of desired process conditions, the software runs the simulation for the pattern of interest that helps to optimize sidewall, bias, and CD variation. Incorporating simulation into the maskmaking process can save cost and shorten the time to production.

A new photomask develop tool designed by Tokyo Electron Limited (TEL) with wafer puddle technology was evaluated at the Advanced Mask Technology Center (AMTC) in Dresden, Germany. Parameters selected for this evaluation were resist dark loss uniformity, critical dimension (CD) uniformity, loading, linearity, resist cross sectional images, and defects using chemically amplified resists (CARs) exposed with DUV (l=257nm) and 50KeV e-beam pattern generators. Implementing wafer puddle technology to photomask developing was not a simple, straightforward process. Standard CAR puddle recipes for wafer developing were inadequate to match CDU requirements for photomasks at the 130nm technology node using DUV exposure. While the results were disappointing, the TEL alpha develop tool cannot be held entirely responsible. Other, non-develop tool related factors such as resist, substrate, coating bake temperature and time, lithography tool, and post exposure bake temperature and time, all contributed to the final post develop results. Indeed, other CAR/substrate combinations exposed at 50keV e-beam and processed on the TEL alpha develop tool were markedly better in CD performance when compared to DUV results. The AMTC has recently taken delivery of a full scale, production worthy, TEL photomask develop tool for use at future technology nodes.

Recently developed positive tone CARs (pCAR) and negative tone CARs (nCAR) have been evaluated for mask making using a 50kV e-beam pattern generator. We determined a screening method considering the most important parameters for example resolution, profile, delay influences, line edge roughness (LER), which was identically applied for all investigated resist samples. The screening was accomplished on 6025 chrome blanks using a state-of-the-art mask line. Some of the investigated resists have shown promising progress in terms of straight profile, of reduced footing, of lower line edge roughness and of an almost insensitive influence of the post exposure delay. Unfortunately, all the improvements were not unified in one sample.

Dissolved resist effect on the global CD has been studied in detail in an effort to understand the CD reduction phenomenon due to develop loading. Spin spray process also showed the loading effect although it is less than that of puddle process. In rotating system like spin spray develop process, it is necessary to understand the fluids effect of developed resist to improve the local and global CD uniformity. In our study, CD reduction due to develop loading has a value of a few nm to ~10 nm as a function of flow direction of eroded resist and erosion time resulted from input dose in the photo mask designed to analyze the loading effect using 50keV exposure system. There are limit in reducing the loading effect using rpm or flow amount control in spin spray process. The range, direction and amount of loading effect according to flow direction, erosion time and process condition like rotating speed and chemical flow amount will be discussed, considering E-beam fogging effect. Develop loading effect at puddle process will be presented.

In previous study the high impact of development by-products on Critical Dimension (CD) through the microloading effect has been demonstrated for a Novolak resist. In this paper, through further tests involving Chemically Amplified Resist (CAR) and Novolak resist, the microloading effect of development is characterized and tentative mechanism is presented. Megasonic Immersion Development (MID), a high flow rate development technique similar to the Proximity Gap Suction Development (PGSD), was used and compared with spin spray development and puddle development. On TOK IP3600, a Novolak resist, we have explored a wide range of process conditions with MID. Developer temperature was varied from 5°C to 40°C with TMAH developer concentration of 1.9% and 2.38% resulting in an isofocal dose range of 90mJ to 190mJ. Exposure Focus Matrix (EFM) with a specific microloading pattern and resist cross sections were performed. The best conditions are quite far from the standard process advised by the resist supplier. Very nice standing wave profile was obtained at high temperature development. On CAR, JEOL 9000MVII, a 50kV e-beam vector scan tool, and ETEC ALTA 4300, a DUV raster scan tool, were used with different develop process techniques including MID. FujiFilm Arch FEP-171 positive CAR and Sumitomo NEB-22 negative CAR were used on 50kV writing tool. Sumitomo PEK-130 was used on DUV writing tool. FEP-171 and PEK-1300 show microloading effect on high density patterns but not NEB-22. MID shows also improved reproduction of develop features in the chrome and a 20% improvement of CD uniformity. The results of this study seem to indicate that a closer look in their development process is needed for 90nm and 65nm technologies.

Chrome and resist thickness are limiting factors for final resolution on mask. The trend in mask manufacturing is consequently moving towards thinner chrome and resist films. The Sigma7300 is a 248nm DUV laser pattern generator with optical resolution approaching 100nm. The earlier standard mask blank for the mask writer had 1030Å thick AR8 chrome together with 4000Å FEP-171 resist. To fully benefit from the resolution capability of the mask writer, this study aimed to investigate the 730Å thick NTAR7 chrome together with thinner FEP-171 resist. The dry etch characteristics of thin chrome and thin resist were also studied. As a first step, a set of plates with varying resist thickness was exposed to extract the swing curve. The resist thickness ranged from 3050Å - 3600Å in steps of 50Å. The fitted curve based on the dose required to break through the resist (dose-to-clear) for different thicknesses showed a maximum at approximately 3200Å. A resolution improvement of about 10nm was achieved in this resist thickness compared to the earlier 4000Å film. Design of Experiments (DoE) was used to perform a screening of the dry etch process on NTAR7 and the 3200Å resist. All plates were exposed using the Sigma7300. Etching was performed on a UNAXIS Gen III Mask Etcher with standard Cl2/O2/He gas mixture. The dry etch process developed from the DoE responses was used to characterize the lithographic performance on mask from the Sigma7300 together with the new optimized blanks. CD linearity <10nm (range) was demonstrated both for clear and dark isolated lines down to 180nm line width. Global CD uniformity <6nm (3s) was achieved and very well defined chrome profiles for 150nm isolated clear lines and 130 nm isolated dark lines were demonstrated.

Bimetallic thin films were previously shown to create laser direct write binary and analog gray scale photomasks. DC-sputtered Sn/In (5at.% Sn, 80 nm) oxidize under laser exposure, modifying the optical density at 365 nm from >3OD to <0.22OD. Bimetallic Sn/In thin film grayscale photomasks have been successfully used to create concave and convex 3D structures using mask aligners with Shipley photoresists. To produce precise 3D structures in the organic photoresists, every mask making step was studied. Compensations during the mask making process were necessary because that the relationship between the optical density of the exposed bimetallic films and the laser writing power is not accurately linear, and also that the response of the photoresists is not linear to the exposure. V-grooves with straight slope profile were produced with calibrations taken into account. X-ray diffraction analysis indicates that structure of laser exposed Sn/In bimetallic films is similar to that of ITO films, suggesting new directions for improvement of bimetallic film optical properties, and that the theoretical maximum transmission should approach pure ITO’s ~0.05OD in the visible wavelength.

We have developed a resist-shade mask (R-mask) technology applicable for small-volume production. The R-mask uses a novel resist as a shading material instead of chromium (Cr), and it exhibits sufficient durability against KrF exposure for ASIC and pilot line applications. Because the R-mask does not require a Cr etching process, it can reduce mask costs and improve critical dimension (CD) uniformity. A defect inspection technique for R-masks has also been investigated, and no defects were observed on a wafer for several R-masks used for device fabrication. The part of the R-mask making contact in exposure tools was carefully designed to not retain resist material so as to avoid particle contamination. We applied several R-masks to form wiring layers for 0.25-um and 0.18-um logic devices and confirmed that there were no differences in process margin and product yield between the R-masks and conventional Cr masks. We have also developed the partial R-mask, which consists of both conventional Cr mask and R-mask areas. The partial R-mask is very effective for customizing semiconductor chips. The R-mask area is applied only to customized circuit areas or certain wiring patterns to adjust circuit characteristics, whereas the common circuit area is delineated by the Cr pattern. The R-mask can be also used to customize attenuated phase-shifting masks, and to make unnecessary hole patterns opaque in prepared hole arrays. The R-mask is a very promising technology for reducing mask costs and improving the turn-around time (TAT) of masks, because of its simple manufacturing process and reworkable capability.

Chrome-based absorbers have been the mainstay of the photomask industry for three decades. While chrome is attractive because of its durability and opacity, it conversely poses challenges for etch and repair. Due to large capital investments, any new absorber must be designed to work with existing scanners, mask writers, and mask inspection tools. Furthermore changing absorber materials may not improve defect control in mask blank fabrication, which is a paramount concern in blank fabrication. Consequently, blank manufacturers are reluctant to change from chrome. In terms of return on investment (ROI), the only driver to switch technologies is achieving higher mask and wafer yields. This is a reasonable assumption as both etch and repair tool suppliers believe a non-chrome material like tantalum (Ta) compounds would significantly improve their capabilities with known technologies. A high level estimate shows that with even aggressive improvement assumptions, a 100% conversion from chrome does not save money. Based on the current International SEMATECH (ISMT) cost of ownership (COO) model and improved yields for critical dimension (CD) and defects, a case can be made for converting at and below 100 nm ground rules. An industry wide conversion from chrome to a non-chrome absorber is estimated to cost $100M. By contrast, blank suppliers are reportedly spending "multiple" millions of dollars to improve chrome per year. A widespread concern is whether binary optical masks have enough life left to provide sufficient ROI. Optical lithography will continue to be of use in the foreseeable future. Even as leading-edge production moves to new technology, the main manufacturing volumes will continue to create significant demand for masks for 100 nm to 45 nm for many years. With the industry currently pushing extreme ultraviolet lithography (EUVL), the best situation would be for EUVL and optical lithography to choose the same absorber material. This creates a winning situation for the industry independent of EUVL implementation timing. Today Ta-based films are a reasonable choice.

The capability of the DUV ALTAÒ 4300 system has been extended by the development of two new optical subsystems: a 0.9 NA, 42X reduction lens and a high-bandwidth acousto-optic deflector based beam position and intensity correction servo. The PSM overlay performance has been improved by modifications to the software algorithms. Characterization data show improved resolution performance in line end shortening, through pitch CD bias and feature corner acuity. The AOD subsystem reduces stripe beam placement errors and random and systematic beam intensity errors. This has enabled local CD uniformity to be reduced to 4.3 nm (3σ) and global CD uniformity to be reduced to 5.8 nm (range/2). Second layer overlay performance is now 20 nm (max error). A split lot wafer evaluation has demonstrated the equivalence of unmodified ALTAÒ 4300 reticles to those printed on a 50 KeV electron beam system for a 130/110 nm device. Wafer lithography results show equivalent CD uniformity, depth of focus and pattern registration results.

We show that a conformal mapping of the type, W = z π/α, describes how a shape of a 45° rotated cross transforms into a contact hole. We discuss its relevance to corner rounding seen on raster beam pattern generators.

The greatly increased complexity of modern masks has in turn led to increased write times and cost of the masks. Any opportunity to decrease write time while providing the required accuracy of the fabricated pattern is highly beneficial. A writing strategy using an arbitrarily shaped beam (ASB) results in a considerably smaller number of flashes to write a complex pattern compared to other strategies. The design of an ASB system is proposed. The ASB electron-beam column is similar to that of a variable-shaped beam system, except for a modified beam-shaping block. This suggests the relatively easy integration of an ASB column. The throughput of an ASB system is a few times greater than the throughput of other systems, except for patterns with low coverage or simple geometries. In addition to the throughput advantages, an ASB system enables higher accuracy, including the feasibility of writing features according to "ideal" optical proximity correction.

At the panel discussion of Photomask Japan 2004, we discussed about "Issues on mask technology for 65nm lithography with ArF". The summary of the PMJ2004 panel discussion is as follows: (1) 65nm node will be achieved with ArF immersion/dry lithography, (2) Attenuated PSM, Alternative PSM and Gate-Shrink will be used for 65nm device production., (3) there are no red brick walls for 65nm mask making, though there are many issues to be solved for 65nm mask fabrication; CD control, inspection, writer, repair, metrology and mask cost. The message from the panel discussion of PMJ2004 is "The mask technology will be ready for 65nm device development and production at 2007" For the business success, chip makers, mask manufacturers, EDA tool and equipment suppliers should work together in order to reduce the mask cost and cycle time.

Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to cost, yield, and manufacturability. In this paper, we present a simulated annealing based floorplanner to solve the shuttle mask floorplanning problem with multiple optimization objectives and constraints. We will consider area minimization, density optimization (for manufacturability enhancement with CMP), wafer utilization maximization, die-to-die inspection constraint, die orientation constraint and their combinations. A nice property of our floorplanner is that it can be easily adapted to different cost models of mask and wafer manufacturing. Experiments on industry data show promising results.

The cost of reticles for sub-100 nm technologies is growing twice as fast as the overall cost of new process development. This makes it necessary to pursue mask cost reduction options alternative to the standard approach of one mask for one layer of one product. The several viable scenarios such as the multi-layer or multi-product (shuttle) masks can be identified by a complex technical and economical analysis, to maximize mask return on investment (ROI) over the product lifetime. The key criteria include matching of layers or products on one plate, with respect to the CD and pattern density commonality and the expected time or fab volume to the conversion to solo mask set. This work discusses the business process and the methodology of such analysis. As an example, by taking into account the cost of the exposure and the mask, one can show that for a 100 nm technology, a positive ROI would be achieved for a product or test vehicle with volume below 50 lots utilizing a multi-layer mask set. A more complete study should include considerations of design rules for blading, stepper capacity, product scheduling, yield variation over the wafer, and probability of database updates. These added restrictions limit the benefits of shared mask methodology.

Mask manufacturing for the approaching 90nm and 65nm nodes increasingly deploys variable shaped beam (VSB) mask writing machines. This has led to high interest in the fracturing methods which are at the heart of layout data preparation for VSB mask writing. In this paper, we set out the main requirements for fracturing and suggest a new solution approach based on integer linear programming (ILP). The main advantage of the new method is that the ILP finds optimal solutions while being flexible enough to take into account all specified requirements. We also suggest several decomposition (polygon partitioning) heuristics which speed up the ILP approach. Experimental comparisons with leading industry tools show significant improvement in quality, as well as acceptable scalability, of the proposed methods. In particular, our fracturing solutions reduce shot count (which reflects write time and mask cost) and dramatically reduce sliver count (which reflects the risk of mask critical-dimension errors). Our results reveal significant headroom that can be exploited by future design-to-mask tools to reduce the manufacturing variability and cost of IC designs.

GDSII file size is not very well correlated with the computer runtime and memory required to perform RET processing. Occasionally, small files can take many hours to process, while large files can run very quickly. The ability to accurately predict resource requirements for RET processing is essential to optimizing RET automation. In this paper, we examine GDSII complexity metrics in an effort to find a method for predicting RET processing resource requirements.

Low k1 lithography process enables the production of 90nm and 65nm nodes by introducing advanced resolution enhancement technology (RET) mask with complex layout. To ensure the printed wafer outcome that meets the original IC design specifications, we need to consider the manufacturability and to verify it during design stage. This means that we need to characterize the process capabilities and use them as the input parameters to examine the upcoming design via simulation verification before mask making. For those of potentially weak or marginal layout design areas identified during the checking stage, we need to build a robust algorithm to improve the RET mask treatment process or to modify the design layout when necessary. This is the basic concept for Manufacturing Reliability Check & Correction (MRC2). In our implementation, MRC2 carries the wafer manufacturability information. By performing MRC2 during the design phase, we can better achieve the goal of Design for Manufacturing (DFM). In this paper, we present two example cases for a production worthy MRC2 - CPL (with two mask writing steps) and DDL (with two exposure masks). From our viewpoints, the first checking step needs to single out the "weak printing spots" or to map out the treated CPL/DDL features with unacceptable DOF and marginal exposure latitude. This allows using corrective actions to ensure a well-behaved printing of the entire chip during manufacturing. We recommend applying both MRC2 and electrical verification in the design verification loop iteratively until circuit performance prediction becomes satisfactory. The looping process generates useful feedback that adds to the RET knowledge database; hence, a more efficient DFM procedure.

The era of week-long turn around times (TAT) and half-terabyte databases is at hand as seen by the initial 90 nm production nodes. A quadrupling of TAT and database volumes for the subsequent nodes is considered to be a conservative estimate of the expected growth by most mask data preparation (MDP) groups, so how will fabs and mask manufacturers address this data explosion with a minimal impact to cost? The solution is a multi-tiered approach of hardware and software. By shifting from costly Unix servers to cheaper Linux clusters, MDP departments can add hundreds to thousands of CPU’s at a fraction of the cost. This hardware change will require the corresponding shift from multithreaded (MT) to distributed-processing tools or even a heterogeneous configuration of both. Can the EDA market develop the distributed-processing tools to support the era of data explosion? This paper will review the progression and performance (run time and scalability) of the distributed-processing MDP tools (DRC, OPC, fracture) along with the impact to the hierarchy preservation. It will consider the advantages of heterogeneous processing over homogenous. In addition, it will provide insight to potential non-scalable overhead components that could eventually exist in a distributed configuration. Lastly, it will demonstrate the cost of ownership aspect of the Unix and Linux platforms with respect to targeting TAT.

We propose a useful methodology, called phase-defocus (P-D) window, to express the mutual dependence of Alt-PSM mask structure and the wafer process window of the pattern-position shift caused by phase error and intensity imbalance. The P-D window was predicted and optimized with a 2-D mask with effective phase and transmission by simulations. We further used rigorous E-M field simulations to correlate the 3-D mask structure to those optimized conditions. Moreover, experiments were performed with four kinds of mask structures and the best Alt-PSM structure was obtained and used to suggest the mask fabrication performance based on P-D window analysis. In order to understand the influence of mask fabrication on patterns with various densities, the common P-D window is proposed. Using the P-D window, the optimized condition was achieved with a maximum process margin for the mask and wafer. In addition, the P-D window is used to quantify the scattering effect coming from the topographical mask and determine the effective 180° for the iso-focal condition.

Most lithography simulation software, such as OPC decoration engines, employ the thin-mask approximation for imaging calculations. While it is well known that a more rigorous approach is often needed for alternating phase-shift reticles, a solution to the full Maxwell equations is rarely used for binary masks. In the past, both the patterns and the thickness of the patterns for COG and attenuated PSM were relatively small compared with the illuminating wavelength. For the future technology nodes, this will not be true. For example, scattering bars are typically a quarter to a third of the size of the main feature. This means that a 65nm isolated line with typically have 65nm to 85nm assist features (mask scale). We have found a non-constant bias through pitch for low k1 imaging that is not found with the thin-mask approach. Results are presented for varying feature sizes, chrome thickness, and for both lines and spaces.

Source optimization techniques fall into two contrasting categories: The first and most common category includes methods to minimize OPC complexity and maximize process window for a specific pattern, without guaranteeing adequate image quality for the rest of the layout. The second category includes methods which optimize source and mask concurrently to deliver the largest process window and maximum resolution. This approach however, provides minimum control in the manufacturability of the mask. Our formulation is a hybrid combination of both categories. We apply a model-assisted double exposure decomposition using pre-optimized sources. By adding a second exposure we minimize possible negative impacts that the pattern specific source may have over the whole layout, while providing control over the area of interest and taking into account realistic mask constraints. We applied this technique to an SRAM design and the surrounding logic. Because of the general formulation of the model-assisted decomposition, we do not explicitly select memory or periphery logic, since by construction this method determines which feature segments correspond to each of the available exposures. We quantify the lithographic performance of this technique against other RET options via a statistical analysis of CD control and ILS behavior.

We describe a new resist model calibration procedure and its implementation in LithoCruiser^TM. In addition to the resist calibration, LithoCruiser is used to perform simultaneous optimization for numerical aperture (NA), mask OPC, and illumination profile with built-in manufacturing constraints for ASML illumination diffractive optical elements (DOE). This calibration procedure uses a global optimization algorithm for resist parameter tuning, matching the simulated and measured 2D resist contours at a user-defined multiple CD sampling across the selected developed 2D resist patterns. Using lumped parameter type resist models and vector high-NA simulation engine, this resist calibration procedure showed an excellent calibration capability of max CD error range < ±4nm for the CPL 70nm DRAM patterns. Calibration results for CPL 130nm contact hole patterns are also included in this manuscript. Dependency of the calibrated model parameters on lithography process (i.e., Quasar, C-Quad illumination and at different defocus) and further improvements to a more predictable resist model are discussed.

Aerial image measurements, SEM measurements from printed photoresist images, and simulations are used to characterize second-order effects due to mask topography, high-NA electric-field vector addition, and mask fabrication tolerances in projection printing of advanced process monitors on special phase-shifting test reticles. Challenging phase-shifting mask designs have been developed in collaboration with DuPont Photomask, Inc., Photronics Inc., ASMLithography, and Advanced MicroDevices for use as precision instruments to measure aberrations, system illumination, and the quality of the photomask itself. The results presented herein on pattern and probe-based aberration monitors show that, while the imaging of the probe portion of the target is dominated by errors in mask geometry and electromagnetic edge effects, high-NA effects play very little role in their image formation. The results also show that the full target suffers from mask edge electromagnetic effects and high-NA vector effects, implying that the ring patterns in the target emphasize those locations in the lens which are most susceptible to high-angle effects.

We have installed the industry's first commercial electron beam mask repair tool in Intel's mask shop. In this paper we describe our on-going efforts of developing e-beam repair processes for binary, phase-shifting and EUVL masks. We present a complete characterization of fundamental capabilities of e-beam repair and make general comparisons with other technologies, in terms of repair resolutions, substrate damage, edge placement, removal selectivity, and process margin. Among many applications, results from quartz etch with excellent resolution and vertical profile are described.

Focused Ion Beam (FIB) systems can be used to repair photomasks by accurately depositing and/or removing absorber material at the nanometer-scale. These repairs are enabled or enhanced by process gases delivered to the area of ion beam impact on the sample. To optimize gas delivery, three-dimensional computational fluid dynamics (CFD) models of selected gas delivery systems for FIB tools have been developed. The models were verified through an experiment in which water vapor was dispensed onto a cryogenically-cooled substrate. Water vapor hitting the sample surface immediately freezes. The height of the deposited ice on the sample surface is proportional to the product of the local gas flux and the exposure time. The gas flux predicted by the CFD model was found to be in good agreement with the experimental measurement. The CFD models were used to predict the mass flux of process gas and the pressure distribution at the sample surface for various gas delivery system designs. The mass flux and pressure relate directly to the amount of reactants that are available for the FIB repair processes. Parametric studies of key gas dispense system geometric parameters are presented and used to optimize the gas dispense system geometry.

Repair of etched quartz defects on AAPSM products negatively affect manufacturability in the mask shop. Currently there are few solutions to repair etched quartz defects, two of these include mechanical removal or a combination of topography mapping and FIB milling of the defect. Both of the above methods involve large capital investments specifically for etched quartz repair. The method presented in this study readily repairs etched quartz without the need to purchase additional tools for AAPSM repair. Photronics' Advanced Materials Program has developed a transparent etch stop layer (TESL) integrated into the binary blank for the purpose of building AAPSM products with a high yield component. This etch stop layer is located under a layer of sputtered SiO₂ deposited to 180° for a given lithography wavelength. These blanks can be used for a variety of etched quartz applications including cPSM and CPL. Photronics has developed software that reads in defect locations from automatic inspection tools and the jobdeck. A "repair" layer is created for the defect file and the plate is then re-exposed on the mask lithography tool. The defects are then etched away using the etch stop to control the phase of the surrounding trench. The repair method was tested using programmed defect masks from single etched 193nm AAPSM technologies. Inspection, SEM, AIMS and profilometry results will be shown.

Focused Ion beam (FIB) techniques have been extended to repair masks for the 65nm node using 193nm wavelength. As historically has been the case, opaque chrome defects provide the greatest challenge for FIB repair processes. These processes have been continually refined to support ever-shrinking geometries and tighter specifications. The most critical specification is deviation of printed line CD at the wafer through a specified focus range of the repaired defect region versus an identical defect-free region. Precise edge placement and quartz damage control are the most important factors in achieving this desired result. FEI Company has developed the Accura XT FIB mask repair system with extended capabilities to keep pace with the requirements brought forth by leading edge lithography masks. The new FIB processes incorporate several newly developed repair process strategies including new beam scanning sequences, improved dynamic registration to track positional error during a repair and a new method of repair by-product removal. Printability, CD and transmission performance will be shown via data collected from the Zeiss 193 AIMSfab tool on a binary test mask with feature sizes close to 65nm geometries. Quartz damage will be shown via FEI’s SNP tool. The data presented in this paper will show that FIB repair of chrome defects is a viable solution to support the most demanding specifications for the 65nm node.

The formation of photoinduced crystals and haze has become a challenge for 193nm photolithography high volume manufacturing (1-6). Extensive work has been performed to develop alternative to piranha chemistry for photomask cleaning processes in an attempt to eliminate the incidence of clean induced ammonium sulfate crystal formation (9-13). However, additional factors are impacting 193nm reticle optical quality. Sources of molecular contaminants such as environmental factors, outgasing from pellicle and reticle storage material can generate varieties of photoinduced crystals over the reticle useable lifetime (5-6). This paper will quantify and rank contributing factors for crystals generated under high energy UV exposure. A broad range of analytical and metrology techniques (FTIR, IC, TD-GC/MS, Inorganics impinger, AIMSTM, KLA Starlight, UV 172nm) and improvements in technique sensitivity were developed in order to identify crystal structure, quantify photogenerated contaminants levels and assess wafer printability impact. Engineering systems aimed at minimizing organic and inorganic molecular contaminants levels will be suggested.

Mask cleaning has been a significant challenge. Advanced PhotoMasks have proven to be even more difficult. The experimental work on 157nm systems uncovered an issue of particle growth under the pellicle. Since the mask blank had a different composition from existing production mask blanks, there was not a concern about current production impact. Investigations were started after a few incidents occurred on 193nm masks. The investigations demonstrated that the masks have a consistent family of contaminants that are on all chrome absorber masks. The initial work provided clues to the nature of the particle growth and some indication of the potential sources. The issues seemed to evolve from the total system and not a single contaminant source. Currently, hard defects due to particle growth under the pellicle occur industry wide. This paper will provide the methodology employed for a recent cleaning evaluation and identify some of the culprits that cause particle growth. The issue has grown to a major problem and needs to be quickly addressed.

An assessment of the mechanical performance of pellicles from different vendors was performed. Pellicle-induced distortions were experimentally measured and numerical simulations were run to predict what improvements were desirable. The experiments included mask registration measurements before and after pellicle mounting for three of the major pellicle suppliers, and adhesive gasket material properties characterization for previously untested samples. The finite element numerical simulations were verified via comparison to experimental data for pellicles with known frame bows, measured by the vendor. The models were extended to simulate the effect of the chucking of reticles in an exposure tool, as well as the various magnification correction schemes available in such tools. Results were compared to ITRS requirements to evaluate performances. This study enables the AMTC to give important feedback to pellicle suppliers and make proper recommendations to customers for future pellicle choices.

The critical source of haze contamination which mainly occurred on MoSiN surface and the interface of MoSiN and quartz is known as sulfuric ions remained after mask process. In this experiment, the UV treatment with oxygen gas was carried out before and after wet cleaning process for reducing residue ions from mask surface, and the effect with the sequence of UV treatment and wet cleaning was investigated. The composition of amorphous MoSiN layer was slightly modified by 172nm UV treatment with oxygen gas, and the amount of chemical residue ions after wet cleaning which use the piranha and SC-1 was reduced according to the transformation of surface composite. And also the relation of the surface transformation and the phase shift after SC-1 cleaning was evaluated.

An architecture for SLM-based mask writing and optical maskless lithography has been described in previous articles. This work reports on phase-shifting capabilities of different SLM's in light of rasterization and image stability. The tilting mirror SLM proven in the Micronic Sigma7300 mask writer has in other papers been presented as comparable to an attenuated phase-shift reticle. This article will feature the novel tilting phase-step mirror SLM. which has phase shifting capabilities enabling it to emulate hard phase-shift reticles. For a straight-forward rasterization architecture where individual pixels are determined by local pattern data it is required that the complex amplitude created by a mirror is confined to the real axis. This is the case for both the normal tilting mirror and the tilting phase-step mirror. For other micro-mirror designs this might not be true and in the case of the piston-mirror SLM this requirement leads to the demand that two or several mirrors work collectively, loosing degrees of freedom and resolution. The tilting phase-step mirror SLM provides a new rule-set for lithography: no penalty for phase shifting or aggressive OPC, seamless pattern decompositions, choice of optimal tones for each pattern, etc. This gives performance and flexibility not possible before.

The International Technology Roadmap for Semiconductors (ITRS) shows that 45 nm and lower feature sizes are required in lithographic production before the year 2007. Both immersion lithography and EUV lithography can play major roles in realizing this goal. However, a maskless lithography system capable of producing 45 nm features is an attractive option for small-volume semiconductor fabrication, such as with ASIC manufactures. Compared with a conventional lithography system, the maskless feature of the system allows the chip designer to be free of the very expensive process of mask fabrication and to shortcut development time. In this paper, we discuss a new maskless lithography concept employing an array of solid immersion lens (SIL) nano-probes. The nano-probes are efficient near-field transducers. Each transducer is the combination a SIL, a dielectric probe tip and an antenna structure. The nano-probes are fabricated in arrays that dramatically improve throughput. By combining these technologies, it should be possible to fabricate an efficient array of near-field transducers with optical spot dimensions of around 20 nm when illuminated by a 405 nm laser diode source. This paper plans to address, for the first time, the efficient generation of an array of light spots with dimensions of λ/20 or less that couple efficiently into dielectric films, like photoresist.

In high fidelity SLM-based mask making and maskless lithography, a high performance rasterizer with high capability is of utmost importance. The rasterizer must be capable, not only to convert the vector format input data to a bitmap suitable for the SLM in fractions of seconds, but also to perform image adjustments in terms of edge placement and edge acuity. This paper presents a new rasterizing algorithm with built-in capability to remove virtually all influence of the finite pixel size on lithographic performance, even for printed features down to the size less than 2 pixels. The rasterizer allows the SLM to mimic the performance of any phase-shifted reticle, including strong phase-shifting and chromeless lithography. In addition, with SLM-based mask making and maskless lithography, it is possible to switch between completely different printing modes (binary, weak and strong phase-shifting, or CPL) between consecutive exposures, without the need for reticle and wafer re-alignment. The result is improved image fidelity, smaller printed features relative to the pixel grid, and flexible powerful phase-shifting capabilities.

E-Beam Lithography is still the driving technology for semiconductor manufacturing of critical levels at the 45nm node. Mask costs, yields and representation of the mask on wafer are important factors to consider. Mask-less E-beam lithography is being considered, but major manufacturing is still done by scanner technology. Therefore the same emphasis on modeling applied in the 1990's on the wafer is now being applied to mask technologies to drive down costs, improve yields and to develop viable mask to wafer transfer patterns. Yield is ultimately connected to process latitude, which is limited by a variety of electron-material interaction issues. As in the optical world, the question is how to maximize the process window considering all the systematic and statistical error sources. Simulation can be used to find out the magnitude of yield limiting effects, and to evaluate the contributing error sources such as PEC file contributions. Film stacks are now becoming an important contributor to statistical error due to technologies such as tri-tone attenuated masks that place a thin layer of chrome over MoSi. In this paper we will compare the SELID E-beam simulation to cross-sections of line-space and contact patterns. Demonstrations of simulation to real data and the use of simulation to further evaluate process window to enhance the learning mode during development cycles will be presented.

Complementary Phase Shift Mask (c:PSM) has been a key photolithographic technique employed by chip makers, including Motorola, to fabricate 130nm-node devices. Advancing from the 130nm to 90nm technology generation, the c:PSM process needs fundamental improvements in order to meet new challenges such as tighter CD tolerance, smaller pitches, etc. In this paper we describe the challenges and our efforts to develop a c:PSM process for the 90nm technology, with a particular emphasis on the gate layer patterning. The significantly increased pattern density led to our strategy to phase shift not only gates but also some routing lines. As a result, more features are prone to phase conflicts. These phase conflicts have been avoided by enforcing more constrains on design rules, optimizing shifter/trim parameters, improving the coloring methods in the software, and even manually handling special cases. Model-based OPC has been applied to both masks with models rigorously calibrated to resist data. Small budget for CD variation imposes stringent requirements on both model accuracy and algorithm robustness. The double exposure process required by the c:PSM process aggravates the difficulties, by introducing issues such as different process conditions in the two exposures, intensity imbalance, connection between segment movements in the two masks, etc. The models and correction algorithm have been tuned to accommodate these issues. Both rule-based and simulation-based verification have been utilized to check mask manufacturability, susceptibility to defects, and pattern fidelity. In particular, a structural checking mechanism has been built for complexities created by the double exposure process. Significant effects from intensity imbalance have been observed on wafer at small pitches. Work is under way to alleviate the intensity imbalance by using different mask making techniques.

Alternating aperture phase-shift mask (AAPSM) technology in combination with conventional illumination enables the imaging needed in the 65nm node and beyond, thanks to its high image contrast and small mask error factor (MEF). It is a known point of attention that AAPSM topography induces an image intensity imbalance between the light propagating through the zero and pi-shifted space. There are several ways to compensate for such imbalance in the mask making process. The most common approaches are applying an undercut or a bias of the pi-shifted space. The guaranteed quartz etch depth of the pi-shifted space through pitch is another challenge in the mask making process of an AAPSM. This paper reports on the methodology to evaluate the mask making quality of AAPSM for both 193nm and 157nm lithography through printability. For this purpose rigorous electro-magnetic field simulations through the 3D mask topography using Solid-CM (software from Sigma-C) are performed. The parameter for the quantification of the image imbalance is the difference between the measured width of neighbouring zero and pi-shifted spaces on the wafer print. As a first step in the methodology the amount of undercut or bias applied on the mask is deduced from the correlation between the experimentally measured and simulated space difference. Once the amount of undercut or bias is known, the phase error for the evaluated structure is estimated by evaluating the through focus behaviour of the space difference. This gives an indication of the quality of the etch process through pitch during mask making. For the 193nm lithography the wafers are exposed on an ASML PAS5500/1100 ArF scanner working with a 0.75NA projection lens. The 157nm AAPSM masks are printed with an ASML Micrascan VII equipped with a 0.75NA projection lens. The wafers and masks are evaluated on a top-down mask-compatible CD-SEM (KLA-Tencor 8250XR).

This paper presents the use of specially designed electrically testable structures to measure characteristics of alternating aperture phase-shifting masks (altPSM). The linewidths of chrome features on the mask are measured using modified cross-bridge structures, the technique behind this is explained together with the specific designs used to characterise both dense and isolated features. A practical, manufacturable solution to overcoming the problem of the non-conductive anti-reflective chromium oxy-nitride is given and results shown to prove its success. Correlation to more conventional CD measurements reinforce this result. A new technique, to measure the overlay of the second laye, used in the mask manufacture as the mask for the quartz etch establishing the phase shifted areas, is discussed. This entails using capacitive test structures in a progressional offset array to establish the minimum capacitance, indicating the overlay achieved. This technique has the added advantage of removing the errors created by mask sag in overlay metrology tools where the mask is held only at the edge. Results are presented indicating the success of this technique.

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable the low k₁ optical lithography. To meet the challenges imposed by the previously unthinkable low k₁ for manufacturing with most stringent dimension control requirements, a capable OPC model to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new OPC model must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, usch as customer designed illuminator and experimental measured illuminator profile from the scanners. The physical and mathematical foundation of the model must be well thought of to meet the requirements for the above-mentioned applications. We have extended our Eigen Decomposition Model (EDM) for model OPC treatment into the high NA regime, in which the vector characteristics of light and thin film stack are taken into account. For CPL calibration, it has been found that 3D mask topography effect cannot be ignored in order to achieve satisfactory model accuracy.

A methodology has been developed to measure OPC model robustness as a function of systematic and statistical process variations. The analysis includes comparison of imaging solutions with several different OPC models generated for different writing tools and lithography process conditions. This approach allows for definition of OPC model tolerance in the continually changing R&D and production environment. The question of when it is absolutely necessary to regenerate OPC models and when application of "the old" OPC model is acceptable is answered This method has been applied at LSI Logic for qualifying a single OPC model for e-beam and laser reticle writing tools in back-end processes for the 0.13um technology node. The OPC model tolerance qualification takes additional time and engineering effort, but it provides pay back through comparable or better product performance and lower costs.

Traditionally, there has been a clear separation between TCAD and full chip simulation tools. While TCAD is normally used during process development, it remains outside the realm of full chip corrections due to its long runtime requirements. One of the key components of a model-based OPC tool is fast and reliable CD prediction of all features present in the design layout, usually at the best point in the process window. Such models exist today, and are routinely used in production. However, there is also a growing need to make more informed decisions about the tradeoffs between accuracy, correction and turn around time. For this reason we need to develop techniques that enable full chip simulations across a variety of process conditions. It was previously shown that a combination of optical vector and variable threshold models can be calibrated to predict well across multiple focus conditions, however dose predictions have not yet been studied. In principle, the possibility of having models that predict process window behavior exists today by calibrating empirical models separately at every one of the process conditions under investigation. However, this method has two clear disadvantages. On the one hand, it cannot guarantee that such models can be extrapolated to conditions other than those used for their calibration, thus not making it possible to provide models "on demand" for arbitrary focus and dose values. And on the other hand, a substantial additional effort is required for creating models at more than one process condition. This work concentrates in listing the requirements to evaluate the robustness of any process window model as well as showing how a well-calibrated compact model can be used to predict -within metrology uncertainty- dose and defocus induced changes for a wide variety of features. While such capability has a number of applications, we will describe a methodology for IC-product verification.

Optical proximity correction (OPC) procedure for modifying designs requires an OPC setting effectively accounting for manufacturing and imaging constraints. Reticle-writing and imaging tool capabilities drive the choice for the minimum feature of an OPC model. Aggressiveness of an optical proximity correction is determined by a discretization setting for an OPC algorithm. Some OPC scheme parameters are there to restrict the minimum spacing and width to avoid circuit failures. The OPC minimum spacing parameter controls bridging lines. The OPC minimum width parameter limits the correction of trenches responsible for circuit breakdown. An aggressive choice of minimum spacing and width for an OPC setting can results in circuit failure: shortage or breakdown. The conservative approach results in poor circuit performance. The methodology was deployed at LSI Logic Corporation for empirical optimization of the OPC minimum spacing/width settings for a no failure imaging solution of OPCed masks. The proposed procedure is particularly beneficial for dark field metal interconnect masks. The approach was successfully validated for 130nm and 90nm backend technology metal layers.

Schott's already commercially available two layer Ta/SiO2 phase shift system can be tuned from 6% up to 30% transmission for 157, 193 and 248 nm lithography wavelengths. Thus one film patterning process provides a wide product range. Dry etch process development is done at IMS chips in Stuttgart, Germany, to provide our customers the service of a good start process for patterning. Our newest development enhances our phase shift layer system. An inspection layer provides an improved contrast for inspection at 257 nm and 365 nm by adjusting reflection to the optimum range from 7% to 20%. Chemical durability against standard mask cleanings was already shown to be good but can be further enhanced by an protection layer. Furthermore a new two layer phase shift system was designed achieving ultra-high transmission above 90% at 193 nm lithography wavelength as an alternative to hard shifter masks.

Different types of phase-shift masks (PSM) in combination with the proper illumination condition are widely used to allow 193nm lithography to print ever-decreasing pitches with a sufficient process window. A viable option for the 65nm node is Chromeless Phase Lithography (CPL), which combines a chromeless phase shift mask and 193nm off-axis illumination. It has been demonstrated that CPL has a high flexibility for through pitch imaging. Also concerning mask making CPL masks showed advantages over alternating and attenuated PSM [1]. This paper discusses how the mask quality and its topography influence the imaging performance of CPL. It is shown that mask topography is an important factor for CPL, as the imaging relies also on the quartz depth differences in the mask. The wafer image is sensitive to phase variations induced by the quartz etch depth and the sidewall profile. Their impact is separately studied using rigorous 3D mask electro-magnetic field simulations (Sigma-C Solid-CM). Correlation of experimental results to simulation explains that the observed pitch-dependent tilt in the Bossung curves is mainly related to the 3D character of the mask. In search for a global compensation valid through pitch, the simulation study also evaluates the effect of other contributors such as lens aberrations in the optical system, assist features and half-toning Cr zebra lines in the design. However, as the tilt is inherent to the CPL mask fabrication, a compensation of the Bossung tilt effect can only be obtained for specific combinations of all sources, as will be shown. We concentrate on the imaging of 70nm lines and 100nm contact holes in pitches ranging from dense up to isolated. The wafers are exposed on an ASML PAS5500/1100 ArF scanner working with a 0.75NA projection lens and various types of off-axis illumination. The wafers are evaluated on a top-down CD SEM (KLA-Tencor 8250XR).

For advance semiconductor manufacturing, imaging contact and via layers continues to be a major challenge for 65nm node lithography and beyond. As a result, much effort is being placed on reducing the k₁ for hole patterning to the range of 0.35 - 0.40. However, the consequences of operating at such low k₁ values are a small DOF, reduced exposure latitude, and high MEF. To achieve this level of k₁, it is necessary to employ resolution enhancement techniques that require phase shifting reticles and/or strong off axis illumination. Recent results show that by using strong off axis illumination to achieve resolution for the dense pitch contacts and by adding subresolution scattering bars for the semi dense to isolated, it is possible to achieve contact hole imaging through the entire pitch range.[1] To generate such reticle designs, the current technique commonly used is to apply a set of rules to define the assist features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) through pitch, whether for binary or attenuated phase shifting reticles. But this approach is not capable of deriving correct assist feature placement for the entire range of pitches and for the randomly placed contact holes that occur in actual device patterns. The objective of this work is to define the necessary methodology for creating binary, attPSM, ternary HTPSM, and CPL^TM reticle designs containing assist features for contact patterns that are representative of actual device patterns that will be used in production at the 65nm node and contain effectively randomly placed contacts over a wide range of pitches from dense to isolated. To overcome the problem of deriving assist features for randomly placed contacts at pitches from semi-dense to isolated, IML^TM Technology was used which is a modeling algorithm based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern.[2,3] This technique provides a model-based approach for placing all types of assist features for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. Using reticle designs created from implementing automated algorithms based on IML, wafer printing results are measured and we examine the critical issues related to contact layer RET's including through pitch process windows, overlapping process window, controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, printing of the assist features, MEF, and reticle manufacturing constraints.

Scattered light in optical lithography, also known as flare, has been shown to cause potentially significant linewidth variation at low-k1 values. The interaction radius of this effect can extend essentially from zero to the full range of a product die and beyond. Because of this large interaction radius the correction of the effect can be very computation-intensive. In this paper, we will present the results of our work to characterize the flare effect for 65nm and 90nm poly processes, model that flare effect as a summation of gaussian convolution kernels, and correct it within a hierarchical model based OPC engine. Novel methods for model based correction of the flare effect, which preserve much of the design hierarchy, is discussed. The same technique has demonstrated the ability to correct for long-range loading effects encountered during the manufacture of reticles.

Double Dipole Lithography (DDLä) has been demonstrated to be capable of patterning complex 2D devices patterns. [1,2,3] Due to inherently high aerial image contrast from dipole illumination, we have found that it can meet lithography manufacturing requirements, such as line edge roughness (LER), and critical dimension uniformity (CDU), for the upcoming 65nm node using ArF binary chrome masks. For patterning at k1 below 0.35, DDL is one of the promising resolution enhancement techniques (RET), which can offer process latitudes that are comparable to more costly alternatives such as two-exposure alternating PSM. To use DDL for printing actual IC devices, the original design data must be converted into a "vertical (V)" mask and a "horizontal (H)" mask for the respective X-dipole and Y-dipole exposures. We demonstrated that our model-based DDL mask data processing methodology is capable of converting complex 2D logic and memory designs into dipole-compatible mask layouts. [2,3] Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One intuitive solution to minimize stray light is to apply large patches of chrome in the open field areas in order to reduce the background (non-pattern area) exposure level. Unfortunately, this is not viable for a clear-field poly gate mask as it incorporates a positive photoresist process. We developed an innovative and practical background-shielding scheme called sub-resolution grating block (SGB), which is part of the DDL layout conversion method for full-chip application. This technique can effectively minimize the impact of long-range stray light on critical features during the two exposures. Reticles inspection is another important issue for the implementation of DDL technology. In this work, we reported a methodology on how to characterize defects and optimize inspection sensitivity for DDL RET reticles.

Vortex phase-shift mask had been shown to have excellent image quality by Marc Levenson et al. [1, 2]. However, its application has been restricted to uniform contact-hole arrays and non-uniform contact holes on uniform grid requiring double exposure technique. In this paper, we show that random contact holes in a real layout can be imaged using vortex phase shift mask, with a single exposure. We use a DRAM contact-hole layout as an example. At minimum half-pitch size of 80nm (k1=0.28) and pitch of 160nm, using 193nm stepper with 0.68 numerical aperture and 0.3 degrees of partial coherence, we are able to achieve 0.4um DOF with 10% exposure latitude. The possibility of using a single exposure and low NA stepper should far outweigh the increased cost of vortex mask for high volume products. In comparison, the corresponding alternating phase-shift mask, however, can only achieve 0.2um DOF at 10% exposure latitude, even with the aid of higher numerical aperture of 0.90 and high degrees of partial coherence of 0.15. For non-uniform contact holes, image asymmetry is an issue. We show OPC-corrected images that are substantially symmetrical. Phase error is always a concern for any phase-shift mask. We show that substantial process windows remain even in the presence of phase errors. Furthermore, we demonstrate that random contact-hole layout can be successfully phase-shifted using vortex phase-shift method. Finally, we shall that the same phase-shift mask design technology for vortex mask can be applied to double line-space phase-shift mask method [3].

As semiconductor lithography geometries scale deeper into submicron regimes, the importance of abundant and accurate metrology becomes more apparent. For example, processes such as OPC generation, RET selection and structure validation require detailed image information such as CD, area, slope and line edge roughness (LER) in order to be considered robust. Large numbers of SEM images of different structure types are often required in order to gain physical insight into pattern transfer behavior (proximity, resolution limits, etc.). In this paper, a set of techniques is described to systematically analyze and report on objects found in SEM images. In particular, a reference template file (either aerial or GDSII) is used to compare design coordinate polygons to those extracted from a SEM image. An algorithm is explored that analyzes the target image and extracts objects based on heuristics that correspond to the SEM image type (or class). The algorithm contains various stages in which the image is filtered, conditioned and finally partitioned in order to extract objects. These objects are then, in turn, compared with the original template file. Information such as CD and threshold population distributions are collected and used as output. An example of OPC model validation using this technique is demonstrated and results from this analysis are presented. A prototypical template structure is simulated using an aerial imaging technique and is then compared to its corresponding SEM image. Finally, this same template image is compared with output of two GDSII-based simulations and discussed.

A proof of concept methodology has been demonstrated for greatly speeding up the simulation of buried defects inside of EUVL multilayer mask blanks through exploiting the problem specific nature of EUV multilayer materials. The optical homogeneity and optical smoothness of EUV buried defects, along with the low numerical aperture of the EUV system, allow the development of fast and accurate simulations. The buried defect problem is broken into three separate components: a push inward to deliver the electromagnetic energy, a reflection calculation, and a push outward to propagate the reflections outside of the multilayer. This new method has been shown to give results as accurate as FDTD simulations, while maintaining the speed of the SSA method when used to simulate buried defects coated with the smoothing process developed at LLNL. The newly proposed method can be viewed as a generalization of the SSA method to incorporate the entire multilayer stack by using a dual mirror structure to approximate the resonance conditions. The new method has been shown to be about 400X faster and use about 20X less memory than FDTD simulations.

The interface roughness of EUV mask multilayers was taken into account for the numerical calculation of blank reflectance, and models for the growth of oxide on Si capping layers were proposed and evaluated. The simulations were then checked and validated with reflectometry measurements at different steps of the mask blank processing as well as for various angles of incidence, and ellipsometry data on layer thickness. The benchmarked models made it possible to characterize EUV mask blank Mo/Si multilayers (period, thickness ratio, number of bilayers), as well as Si capping layers and native oxide layers from reflectivity measurements. This enabled the study, via a combination of experiments and simulations, of the growth of SiO2 layers, bringing deeper understanding into this phenomenon. Finally, the simulations were used to more properly optimize multilayers and quantify the influence of the exposure tool illumination numerical aperture. Having successfully matched reflectivity data around the actinic wavelength, it was also possible to extend the models to inspection wavelengths in order to predict inspection contrast values.

Three different architectures were compared as candidates for EUV lithography masks. Binary masks were fabricated using two different stacks of absorber materials and using a selective etching process to directly pattern the multilayer of the mask blank. To compare the effects of mask architecture on resist patterning, all three masks were used to print features into photoresist on the EUV micro-exposure tool (MET) at Lawrence Berkeley National Laboratory. Process windows, depth of focus, mask contrast at EUV, and horizontal and vertical line width bias were use as metrics to compare mask architecture. From printing experiments, a mask architecture using a tantalum nitride absorber stack exhibited the greatest depth of focus and process window of the three masks. Experimental results obtained using prototype masks are discussed in relation to simulations. After accounting for CD biasing on the masks, similar performance was found for all three mask architectures.

Extreme Ultraviolet Lithography (EUVL) reflective mask blank development includes low thermal expansion material fabrication, mask substrate finishing, reflective multi-layer (ML) and capping layer deposition, buffer (optional)/absorber stack deposition, EUV specific metrology, and ML defect inspection. In the past, we have obtained blanks deposited with various layer stacks from several vendors. Some of them are not commercial suppliers. As a result, the blank and patterned mask qualities are difficult to maintain and improve. In this paper we will present the evaluation results of the EUVL mask pattering processes with the complete EUVL mask blanks supplied by the commercial blank supplier. The EUVL mask blanks used in this study consist of either quartz or ULE substrates which is a type of low thermal expansion material (LTEM), 40 pairs of molybdenum/silicon (Mo/Si) ML layer, thin ruthenium (Ru) capping layer, tantalum boron nitride (TaBN) absorber, and chrome (Cr) backside coating. No buffer layer is used. Our study includes the EUVL mask blank characterization, patterned EUVL mask characterization, and the final patterned EUVL mask flatness evaluation.

EUV Lithography requires high end quality defect free layers from the backside coating to the absorber stack. Low thermal expansion materials (LTEM) substrates with super flat surfaces are already available with low defect backside coating for E-Chuck technology. The multilayer stack is well developed from a physical point of view and major effort relies nowadays on the layer defectivity. On the other hand, absorber stack becomes one of the main challenges in terms of stress, optical behavior for ultraviolet wavelengths and dry etching behavior. Schott Lithotec is currently developing absorber stack solutions that will fulfill the requirements of next generation lithographies. There are several options for achieving the mechanical, optical and chemical specs for buffer layers and absorber coatings. Some of them are already integrated in our production processes. Buffer layers were evaluated and reach almost the physical and chemical level necessary to fit with the mask processing. TaN based absorber coatings were designed and deposited by an ion beam sputter tool optimized for low defect deposition (LDD-IBS). The chemical composition of our layer and its manufacturing process is already optimized to achieve high quality etching behavior. The current results of defect density for the absorber stack will be presented.

Actinic (at-wavelength) inspection of EUV mask blanks using a dark-field imaging proved a high sensitivity for detecting multilayer defects through detecting programmed phase defects accurate to 70nm in width and 2nm in height without any detection of false defects. Characterization of the experimental actinic inspection tool is ongoing to find the ultimate sensitivity of this tool to define the detailed specification of a proto-type tool. In this paper, we present a detailed analysis of the defect signal intensity compared with AFM measurements taken from more than 20 programmed phase defects. This analysis proved that the signal intensity is mainly correlated with the volume of bumps whose sizes range from 2.8nm to 6.0nm in height and from 59nm to 86nm in width. The correlation suggests that the intensity variation within the group of the same design size reflects the actual variation of the defect size. Some natural defects other than programmed defects are also detected. The comparison of the defect signal and AFM analysis suggests that one of the detected defects is not a pure phase defect but more like an amplitude defect. The smallest natural defect had a surface height as low as 1.5nm, which can only be detected by lowering the detection threshold to the level with some statistically expected false defect counts. Current efforts to improve its detection capability while minimizing false defect detection are also discussed.

Mask blanks for extreme ultraviolet lithography (EUVL) are fabricated by depositing Mo/Si multilayer films on 6” square super polished substrates. These mask blanks must be almost defect-free and development of a suitable multiplayer deposition tool and process is crucial for the commercialization of EUVL. We will show that using current, real-world quartz substrates and our state-of-the-art defect inspection tool, that substrate defect decoration is an obstacle; this means that there appear to be many non-detectable substrate defects that become detectable once a reflective coating is deposited. This makes it very challenging to conduct accurate defect root cause analysis experiments. We have overcome this obstacle: it entails characterizing an already coated substrate for defects, which provides a suitable reference from which to measure the defects in the multilayer coating that is subsequently applied. We will demonstrate that this is a viable technique and that it enables a suitable defect baseline to be obtained; this is crucial to performing accurate root cause analysis experiments for potential defect sources/mechanisms.

For the last five years KLA-Tencor and our joint venture partners have pursued a research program studying the ability of optical inspection tools to meet the inspection needs of possible NGL lithographies. The NGL technologies that we have studied include SCALPEL, PREVAIL, EUV lithography, and Step and Flash Imprint Lithography. We will discuss the sensitivity of the inspection tools and mask design factors that affect tool sensitivity. Most of the work has been directed towards EUV mask inspection and how to optimize the mask to facilitate inspection. Our partners have succeeded in making high contrast EUV masks ranging in contrast from 70% to 98%. Die to die and die to database inspection of EUV masks have been achieved with a sensitivity that is comparable to what can be achieved with conventional photomasks, approximately 80nm defect sensitivity. We have inspected SCALPEL masks successfully. We have found a limitation of optical inspection when applied to PREVAIL stencil masks. We have run inspections on SFIL masks in die to die, reflected light, in an effort to provide feedback to improve the masks. We have used a UV inspection system to inspect both unpatterned EUV substrates (no coatings) and blanks (with EUV multilayer coatings). These inspection results have proven useful in driving down the substrate and blank defect levels.

Defect detection sensitivity of a multi-beam confocal inspection system operating at a wavelength of 488 nm is characterized using experiments and image modeling. Experimental data on defect sensitivity are reported for programmed defects on mask substrates and blanks that are being developed for extreme ultraviolet lithography. The effects of sample surface roughness on the detection sensitivity and signal-to-noise levels are quantified. Theoretical analysis of confocal imaging of defects is in excellent agreement with measured defect images. Modeling is used to predict inspection sensitivity for defects commonly found on mask blanks.

In immersion lithography, the air gap that currently exists between the last lens element of the exposure system and the wafer is filled with a liquid that more closely matches the refractive index of the lens. There is a possibility that air bubbles, which represent a refractive index discontinuity, may be present in the liquid within the active exposure region and cause errors in imaging. One potential source of bubble generation is related to the flow of liquid over previously patterned features, or topography, during scanning or filling. This microscale entrainment mechanism is investigated experimentally and analyzed using computational fluid dynamics (CFD) modeling. The contact angle is a critical parameter that governs the behavior of the contact line and therefore the entrainment of air due to topography; the same topography on a hydrophobic surface is more likely to trap air than on a hydrophilic one. The contact angle can be a strong function of the flow velocity; a hydrophilic surface can exhibit hydrophobic behavior when the velocity of the free surface becomes large. Therefore, the contact angle was experimentally measured under static and dynamic conditions for a number of different surfaces, including resist-coated wafers. Finally, the flow of liquid across 500-nm deep, straight-sidewall spaces of varying width was examined using both experimental visualization and CFD modeling. No air entrainment was observed or predicted over the velocity and contact angle conditions that are relevant to immersion lithography. The sharp-edged features studies here represent an extreme topography relative to the smoother features that are expected on a planarized wafer; therefore, it is not likely that the microscale entrainment of bubbles due to flow over wafer-level topography will be a serious problem in immersion lithography systems.

Nanoimprint lithography (NIL) was placed on the 2004 ITRS Roadmap, thus signifying its growing potential as a viable next-generation lithography technique. A particularly promising NIL technology is Step-and-Flash Imprint Lithography in which the pattern from a quartz template is transferred into a UV-curable silicon-rich monomer. The process of squeezing the monomer film during the imprint process produces significant flow-related pressures on the template which result in out-of-plane distortions (OPD). These OPD inherently produce in-plane distortions which compromise the quality of the resulting features. A single droplet imprint process, wherein a single puddle of monomer is used to cover the entire active area, suffers from throughput limitations due to the low imprint velocities that are required to control the flow-related pressures exerted on the template. In response to these limitations, recent research has focused on a multiple droplet imprint process wherein many droplets are dispensed and coalesce during the imprint process, resulting in lower flow-related pressures. In this paper, a numerical model is described that is capable of predicting both the pressures and the template distortions during a multiple droplet imprint process. The model consists of a finite element structural model of the template interfaced to a fluid-dynamic model of the flow through the gap; the distortion of the template affects the pressure applied on the template and vice versa, therefore a coupled, fluid-structure model is required. The pressure distribution during the imprint process is described by an analytical solution to the Reynolds equation that is modified to account for the coalescing process as well as the affects of absorption and surface tension. The modified solution is developed and verified through the use of computational fluid dynamic simulations. Results are described for a nominal set of conditions and a parametric study of the effect of droplet density is presented.

Step and Flash Imprint Lithography (S-FIL) 1X templates must eventually achieve and maintain the very low defect counts commensurate to current production masks. This requires typically fewer than ten or even no defects over the entire field and to minimize template fabrication costs and techniques must be identified to repair defects on templates when they do occur. We describe inspection and repair methodologies and how it can be applied to the imprint template. For inspection, test patterns etched onto the template enable both a die-to-die comparison, to find nuisance defects, and also calibration of sensitivity to different types of preprogrammed defects. A state of the art deep UV photomask inspection system (KLA-Tencor model 526) can detect these events with about 70 nm threshold for imprint masks using reflection mode contrast. Initial scans are made at various stages of the imprint process: the processed mask, after dicing, and after several imprints. The scans show mostly isolated point defects at a density of ~ 10 to 100 per mm². To repair defects, studies were undertaken using RAVE’s nm650 tool which is essentially an AFM platform that relies upon a nano-machining technique for opaque defect removal. On S-FIL templates, the standard deviation for depth repairs in quartz from the target depth was found to be 3.1 nm (1σ). The spread in edge placement data for opaque line protrusions was 21.5 nm (1σ). Trench cuts through lines were successfully created with a minimum size of about 55nm. The repairs on the template were verified by imprinting the features on wafers. The range of depth offsets studied (-15 to +15) had no bearing on the imprinting process and the edge placement on wafers replicated the edge placement of the repaired templates. Trench cuts on the template were successfully filled with the imprint monomer and measured slightly larger than the minimum gap size. Finally, the imprinted wafers were used to pattern transfer features into 100nm of oxide.

Thirty years ago it was the common believe of most of the lithographer that the limit end for the optical lithography will be at about 1 μm ground rule. So NGL tools were developed to go in the 500nm and 250nm regions. 15 years later the different optical lithography techniques were still alive exposing feature sizes down to 200nm and the NGL tool developer had to move to 100nm and below. Today 100nm features made by optical lithography is world wide a common technique in most of the modern chip manufacturing plants, and feature sizes beyond the used wavelength are state of art. So do we really need NGL or will the optical lithography lives forever? Well, there are already optical system available or will be soon delivered to the manufacturing lines which are able to expose feature sizes down to 70nm and even to 50nm if they use 193nm immersion lithography. But for what price? The optical lithography became extremely expensive. Reticles for the 70nm technology full with OPC structures may cost up to $ 500 K and an optical reticle set up to $ 2 Million. So in my understanding the introduction of any NGL technique will only happen if such a technique can demonstrate at least the same performance as the optical lithography but at a lower cost level. The best understood NGLs are the electron beam lithography techniques used in e-beam direct writing tools for the exposure of masks and reticles or e-beam techniques which expose the wafers using masks like E-beam Projection Lithography (EPL) or Low Energy E-beam Proximity Lithography (LEEPL) respectively. Both EPL and LEEPL require a similar mask technique so called stencil masks. The first 1x stencil masks (a silicon wafer with a thin membrane area containing the pattern as physical holes) were developed by IBM Germany more than 25 years ago and perfected in the Advanced Mask Facility (AMF) at IBM Vermont. Today, these 1x stencil masks used for LEEPL are mainly produced by Hoya, DNP, Toppan and NTT-AT in Japan. This paper will explain the different fabrication processes for the stencil masks, their different shapes and their performance used for LEEPL.

For next generation photomask lithography, improved resolution and precision are required to monitor lithography tools and photomask processes. The newly developed LWM9000 SEM Critical Dimension Scanning Electron Microscope (CD-SEM) for photomask applications will be presented. Its proprietary electron optics technology combined with an improved detection system leads to sub-nanometer CD measurement repeatability by almost completely eliminating the effect of charging and contamination. In an effort to minimize integration into production environments and to facilitate the ease of use the new CD-SEM utilizes a graphical user interface and data evaluation software based on Leica Microsystems’ LMS IPRO / LMS IPRO2. Presented in this paper is data showing leading edge CD measurement repeatability performance on chrome on glass substrates (COG), different types of phase shift masks (PSM), and resist plates. The virtual lack of charging in conjunction with a laser controlled stage, dramatically reduces the need for local feature alignment prior to CD measurement in most cases. The lack of need for local pattern alignment leads to increased throughput and high reliability during the measurement process. The standard system can be configured for manual loading or SMIF handling.

The capability of a high NA, large working distance, microscope objective was demonstrated by investigating different mask features. The microscope objective is based on a hybrid concept combining diffractive and refractive optical elements. Resolution down to 125 nm lines and spaces (L/S) is demonstrated by investigating periodic chrome on glass structures. A significant additional improvement of the resolution is achieved by inducing a solid immersion lens (SIL).

The recent introduction of chromeless-phase lithography (CPL) has provided lithographers with a powerful wavefront engineering tool for patterning at k₁ values below 0.3. Reliable image formation at such extreme k₁ requires a well-characterized CPL photomask. However, the limitations of available optical inspection tools have made the test and measurement of CPL photomasks a difficult task. In this paper, we describe preliminary imaging and phase metrology results on a leading-edge CPL reticle using an high-resolution 193-nm microscope. This microscope features a solid-state 5-kHz repetition rate, 193.4 nm actinic light source in conjunction with high-numerical-aperture (0.75 NA) optics to provide 200X magnification, 150-nm Rayleigh resolution and 35-nm pixel size over a 30-micron image field. A recently-developed phase metrology architecture facilitates optical path difference (OPD) measurements of isolated or dense features on a sub-200-nm spatial scale. We discuss the phase measurement process and present images and corresponding OPD measurements of line and contact structures on an ArF CPL reticle that is designed mainly for the 65 nm technology node. We compare these OPD measurements with predictions based on surface nano-profilometer (SNP) step-height measurements of the same feature regions.

In order to meet stringent mask CD uniformity requirements, mask makers require a high precision CD metrology tool. According to the 2003 revision of the International Technology Roadmap for Semiconductors, there are no known solutions for sub-nanometer CD precision requirements. Furthermore, ITRS lists non-destructive, production worthy mask level microscopy for CD measurement for 3D structures as one of the five difficult challenges for 2009 and beyond. This paper focuses on the recent development successes of a scanning force based microscopy platform (Stylus NanoProfilometry, SNP). Innovative scanning strategies are discussed that enable high throughput, sub nanometer CD precision on advanced mask structures. Advancements in tip technology are also highlighted with metrology data presented on re-entrant alternating aperture phase shift mask features.

As the technology roadmap continuously goes along, pattern density increases beyond more than 250 G shots per a mask until 2010. However the total usable beam current is limited by Coulomb interaction to maximum several hundred nanoampere and by the settling time of positioning amplifier the shot rate is restricted to around 10 MHz. To overcome those restrictions we propose MCC (Multi-Column cell with Lotus Root lens) system to use for mask making. In this system plural numbers (4 or 16) of square variable shaped beams and some kinds of Cell Projection beams including triangles and fundamental DRAM or SRAM patterns are independently controlled to expose simultaneously different parts of a glass substrate. Coulomb interaction between beams of different CCs no more exists and parallel writing is carried out. With this system a mask can be exposed from four to sixteen times faster than present single column system. We evaluated the beam performance of the electron optics Proof of Concept (PoC) system of Multi-Column Cell (MCC) method. As for the two beams at the near center of 4 x 4 layout with 25 mm pitch they show the good uniformity and low interference.

As the mask cost and cycle time have increased dramatically with the shrinkage in the design technology, it becomes crucial to produce photomask with lower cost and reasonable cycle time. It is also important to achieve good process window and mask quality at the same time. In this paper, we study the feasibility of DUV laser mask writing tool for sub-wavelength technology on backend layers. Comparison between DUV laser mask writing tool and 50keV electron beam writing tools was done, based on reticle critical dimension (CD) uniformity, CD through pitch and linearity performance. Besides, wafer results on CD through pitch, linearity, line end shortening, pattern fidelity are also presented. 3 sigma of reticles CD uniformity performance are around 11 to 20nm for DUV laser writer and 5 to 15nm for 50keV. CD through pitch range for reticles written using DUV laser writer are around 8 to 11nm and 3 to 5 nm for 50keV. CD linearity performance is around 10 to 20nm for DUV laser writer and 4 to 8nm for 50keV. From the results, we conclude that DUV laser writer demonstrates reasonable good mask and wafer performance, and it is adequate for sub-wavelength backend mask technology on some of the critical layers.

With the rapid progress in the minimization in the device fabrication, it comes to be indispensable to reduce Critical Dimensional (CD) error in the mask production. The electron beam mask lithography system HL-7000M series has been developed, to meet the needs for mass production line below 90 nm node. A novel high-accuracy Proximity Effect Correction (PEC) method of exposure correction for pattern density variation is applied in this system. By using this high accuracy PEC method, CD error caused by proximity effects has been reduced to 4 nm, from 14 nm with the conventional PEC method.

Two types of strut-supported low energy electron-beam proximity projection lithography (LEEPL) masks which are grid-type mask and COSMOS-type mask, were investigated for Global image placement (IP). First, we evaluated the dynamic repeatability measurement performance for global IP, measuring a same mask 10 times on a 46 x 46 mm pattern area by using LEEPL electrostatic chuck (ESC). The measurement repeatability for grid type and COSMOS type were 5.1/7.8 nm and 4.4/5.8 nm in x/y directions respectively. And then global in-plane distortion (IPD) of COSMOS type masks with various stress and flatness were measured. The global IPD of a COSMOS-type mask with a low stress of 10 MPa and a flatness of 3.1 μm was 6.5/6.4 nm in x/y directions, which is negligible assuming the measurement repeatability. Finally the global IPs of the two-type masks were measured. The global IPs for the grid-type and COSMOS-type were 24.5/15.7 nm and 23.2/16.4 nm in x/y directions respectively. Thus we confirmed that the global IP obtained meet the required value of less than 30 nm.

At IBM’s Mask House, we deigned, installed, and evaluated a fully automated pellicle mounting tool. Features include very low particulate levels, ability to mount a wide variety of pellicles, ease of operation, and pellicle and mask inspection capability. During an evaluation period, pellicles were mounted both with this fully automated tool and with a semiautomatic tool. The fully automated tool showed good reliability (>95% availability) and a 2X lower incidence of foreign material contemination as compared with the semiautomatic tool.

Increase of cost and long turn-around-time (TAT) are becoming hot topics for advanced photomasks. Especially, in the small volume production such as SoC and pilot production, the mask cost and TAT are becoming an important issue for the semiconductor industry. To get rid of these issues, we propose the R-mask (resist shade mask) concept, and in this paper, we will focus on the fabrication techniques of the R-mask. The essential of the R-mask is the simplification of mask fabrication and inspection process. A newly developed e-beam resist, which is able to shield the KrF light, is used as the mask pattern material instead of the chrome. Pellicle is mounted immediately after the mature development process, so that defect density could be reduced. Furthermore, the R-mask concept omits mask cleaning and repair process. We evaluated the newly developed e-beam resist from the standpoint of applicability to mask manufacturing, and we successfully made an R-mask for 180nm metal layer pattern with the new resist. In this paper the process performance of resist is reported.

ULVAC Coating Corporation proposes a new ArF high transmittance attenuated mask which consists of a thin MoSiON film and a quartz trench. We made an appropriate thickness MoSiON film and found a proper dry etching condition to dig a quartz trench by a NLD dry etcher. The etched quartz trench had very smooth bottom and correct depth. It is very difficult to make ArF high transmittance attenuated mask with perfectly satisfy the transmittance and phase shift angle because of characteristics of MoSiON film. PSM with MoSiON film has been used commercially under 248nm and 193nm wavelength. If it is possible to use the current MoSiON film also for ArF high transmittance attenuated mask making, it would be very convenient for mask makers. This report will show our investigation results in regards to the possibility of making ArF high transmittance attenuated mask by using current MoSiON film with setting the transmittance of 15% at 193nm wavelength and setting the phase shift angle of 180 degree by MoSiON film and quartz trench etching. NLD (Magnetic Neutral Loop Discharge) mask etcher was used for this investigation. At conventional conditions, a large side etch was observed on the MoSiON film as a result of the etching process. We checked correlation between gas pressure and side etch, and found lower pressure resulted in smaller side etch. As the further low pressure, appearance of sub-trench were observed. By adding a CxFy gas with CF4-base etching gas for the dry etching process, we are able to improve the side etching and also sub-trench.

Preserving the accuracy of pattern reproduction on silicon with the decreasing linewidth usually requires paying increasingly higher prices for the masks. However, the advances in optical, device and circuit simulation tools are offering interesting alternatives to the tightening of reticle specifications. The performance of the next generation circuits can be verified by integrated simulation at the mask, device, and cell level. The tradeoff between mask quality, process options, product characteristics, and manufacturing cost can be thereby analyzed. Such integrated simulation impacts also mask shop and process deliverables. As an example, it was shown the potential to reduce reticle rejection rate by several times. In this work, integrated simulation helped choose the most economical option for the poly mask process, to control channel CD variation related to the discontinuity of gate pattern in multi-transistor memory cells. We evaluated the tradeoff between cell performance and the cost of the phase shift mask set to reduce poly CD variation. Based on the cell stability dependence on photo process parameters, we proved that the low cost approach can still yield economically satisfactory results.

In 65nm node and some more technology node probably may go with current optical lithography and industry has predicted many challenges. In patterning point of view, quality and cost of mask became more and more important than ever. Particularly, mask defect engineering technology is key area not only inspect the defects but also mask process monitoring and improvements. In mask inspection technology there were a lot of new progresses to enhance the defect inspection sensitivity and stability. The key solution to achieve better sensitivity may be short inspection wavelength and adequate detection algorithm. In this paper, we will propose defect size specifications of 65nm and beyond optical mask with various OPC and RET environments. In addition, we will present initial data of newly developed 198.5nm inspection wavelength system. Through this study, we found future optical mask faces new challenges in defect inspection and to solve these problems, we need advanced mask inspection system and collaborations among patterning related fields.

Tebaldi is a software tool developed at Intel Mask Operation (IMO) for quantitatively analyzing patterns in 2D. Its initial scope was to analyze aerial images taken with a microscope. However the software has recently been enhanced to support aerial images obtained through simulation, bitmap, jpeg and tiff files saved from the mask inspection systems and the scanning electron microscope (SEM). This article primarily focuses on the SEM module of the software. Tebaldi supports simulated aerial images generated through IMO’s simulation based defect disposition system. This allows engineers to directly correlate 2D structures in an experimental aerial image, with those in a simulated image. To analyze SEM images, the software features scaling, alignment and calibration functions. Several linear and non-linear filtration techniques to reduce noise and charging exist. Custom convolution kernels can be user defined. Ability to segment features and extract contours also exist. Further, these contours can be overlayed and shortest distances between corresponding points can be computed in a user friendly manner with a high degree of confidence. Tebaldi is currently used in production to disposition defects in repaired sites on masks shipped from IMO as well as to compare SEM images to determine the pattern fidelity across mask writers and processes within IMO.

A novel high-resolution mask inspection platform using DUV wavelength has been developed. This platform is designed to enable the defect inspection of high quality masks for 65nm node used in 193nm lithography. In this paper, newly developed optical system and its performance are reported. The system is operated at wavelength of 198.5nm, which wavelength is nearly equal to 193nm-ArF laser exposure tool. Some defect image data and defect inspection sensitivity due to simulation-base die-to-die (D/D) inspection are shown on standard programmed defect test mask. As an initial state D/D inspection performance, 20-60 nm defects are certified. System capabilities for 65nm node inspection and beyond are also discussed.

Mask manufacturing becomes more complicated with each technology generation. The number of tools and processing steps is increasing while the feature geometries and substrate materials are becoming more difficult to process. At the same time, the market demands new product introductions at a faster rate than ever before. The only way to meet all of these challenges is through faster yield (critical dimensions, defects, registration) learning. However, the rate of technology development for manufacturing has far outpaced the development of yield learning solutions. Spreadsheet-based learning tools are severely limited in their ability to handle the complex hierarchical data, and often there is not enough data available for a meaningful statistical analysis. We have deployed a novel application that greatly enhances our ability to perform commonality studies, which are a key element of yield learning. This application is based on treemapping technology, which takes advantage of the human eye's ability to detect subtle changes. Here, data is represented graphically on a two-dimensional screen. However, additional dimensions are included on the same plot through the use of size, color, and hierarchical nesting. This has enabled us to be more sophisticated in our approaches to yield learning through visualizing multidimensional correlations. In addition to improving our ability to perform commonality studies, the tool has also been used for process stability analysis, hold and excursion analysis, and several other manufacturing and engineering applications.

The frequent occurrence of crystal growth defects on the patterned surface and back glass of critical layer reticles in 193nm lithography has been seen at most advanced fabs around the world. While frequent contamination inspections using regimented sample plans help monitor the growth of crystals and protect yield, no clear solutions have been found to eliminate this progressive defect growth. The recently proposed “Advanced Reticle Defect Disposition Process” (ARDD) was applied successfully for the first time. This process employs a high-throughput inspection system based on the STARlight architecture and - after defect reduction through algorithms - a high-resolution AIMS review system, utilizing the newest networked data connectivity to directly exchange inspection report data and review results. The printability of crystal growth defects is highly variable depending on which surface the defects occur, the size of the defects, and the proximity of the defect to a printing pattern. Crystal growth defects can have different transmittance and phase depending on the lithography wavelength and we found in our investigations a significant change in transmission loss depending on lithography settings like NA and sigma. Such effects may result in severe reduction of the process window, and affect yield. Progressive reticle defects have been characterized on a production reticle applying the ARDD process. It is shown that emulating any given stepper/ scanner settings is necessary to measure the effect of these types of defects on transmittance and that through-focus AIMS evaluation is required to accurately assess the printability of crystal growth defects in terms of process window on wafer. Both features are important components of an overall effective and economical reticle monitor strategy, e.g. in order to optimize the reticle cleaning cycles and thus the reticle lifetime.

As new technologies are developed for smaller linewidths, the specifications for mask cleanliness become much stricter. Not only must the particle removal efficiency increase, but the largest allowable particle size decreases. Specifications for film thickness and surface roughness are becoming tighter and consequently the integrity of these films must be maintained in order to preserve the functionality of the masks. Residual contamination remaining on the surface of the mask after cleaning processes can lead to subpellicle defect growth once the mask is exposed in a stepper environment. Only during the last several years, has an increased focus been put on improving mask cleaning. Over the years, considerably more effort has been put into developing advanced wafer cleaning technologies. However, because of the small market involved with mask cleaning, wafer cleaning equipment vendors have been reluctant to invest time and effort into developing cleaning processes and adapting their toolset to accommodate masks. With the advent of 300 mm processing, wafer cleaning tools are now more easily adapted to processing masks. These wafer cleaning technologies may offer a solution to the difficulties of mask cleaning and need to be investigated to determine whether or not they warrant continued investigation. This paper focuses on benchmarking advanced wafer cleaning technologies applied to mask cleaning. Ozonated water, hydrogenated water, super critical fluids, and cryogenic cleaning have been investigated with regards to stripping resist and cleaning particles from masks. Results that include film thickness changes, surface contamination, and particle removal efficiency will be discussed.

Tighter lithography requirements are increasing the challenges for mask registration metrology. Demands on calibration will increase as tool specific calibration need to significantly improve to enable accurate plate quality assessment and adequate matching between multiple writer and metrology system. We present results of calibration study conducted on Leica LMS IPRO 2 and LMS IPRO1. Two different calibration techniques were used to match the tool grid to absolute Cartesian coordinate system. The impact of the two calibration techniques on tool matching is summarized. The results are used to make recommendations on improving calibration methodology.

Different mask manufacturing methods can lead to specific signatures (fingerprints) in registration and CD distribution across the mask blanks. A mix-and-match strategy can thereby cause systematic contributions to the total overlay and CD error on the wafer. As a result, mixing masks between different mask vendors or different mask writing tools is often regarded as detrimental to wafer yields. Especially overlay and CD sensitive structuring layers, like gate and capacitor layer, it is often preferred to use only one mask vendor and mask making process to cancel out systematic errors. However in reality, due to delivery constraints or other logistics boundary conditions, it would sometimes be preferable to be able to mix-and-match for different masks. That could be the case if one manufacturing site is not able to supply a specific type or spec class. On top of that, it might even be required that different copies of one layer are supplied by different vendors. That could be caused by commercial reasons or by switching the mask vendor. In this paper we investigate systematically the influence of mix-and-match masks on frontend wafer yields. Three main issues can be identified as potential pitfalls: registration fingerprints, CD characteristics (linearity, line-end-shortening, proximity), and metrology matching. Main contributors for differences are the writer technology (tool-type, correction settings), developer and etch process, as well as different calibration and metrology methods. The CD characteristic can be compensated by generating appropriate OPC models, and the metrology- and correction methods can be matched. Consequently, we would like to focus on the registration fingerprint of different writer tools from different maskshops as the one systematic contribution which cannot be eliminated. We will investigate the impact of registration fingerprints by analyzing the electrical performance of memory chips.

This paper details a study undertaken to revisit defect specifications and maskshop metrology calibration for a mature lithographic process. A programmed array was created containing darkfield and brightfield feature types at various pitches with appropriate OPC sizing. Defects were systematically added to the layout with differing sizes and spacing from the main feature. After exposure with production illumination settings, resist image data was collected and used to determine critical defect sizes. These results are correlated with typical maskshop metrology methods such as AIMS, AVI Photomask Defect Metrology Software (PDMS), and CDSEM. In some cases, it is shown that AIMS data correlates poorly with both defect size and spacing from the feature edge when using illumination settings nominally matched to the exposure tool. Finally, for the particular processes reviewed in this study, the results indicate that the initial reticle defect specifications are often too aggressive for the finalized production lithographic process.

Reticle inspection and qualification is getting very important due to the overall shrinking feature sizes on chips and CD values less than the exposure wavelength. Mask defects will matter increasingly and successful defect disposition and image qualification is becoming essential to improve yield. Currently ongoing studies demonstrate the beneficial use of AIMS^TM* (Aerial Image Measuring System) -besides its application in mask shops like repair verification- for various wafer fab applications like Incoming Qualitiy Check (IQC), Automated Reticle Defect Disposition (ARDD)1, OPC verification or litho process evaluation in engineering without the use of stepper time and image qualification through wafer SEM evaluation. Among the important questions for the use of an aerial image measuring system is the level on which different tools compare to each other in terms of critical system performance parameters in order to judge the results of the data analysis in a global way. In this work we conducted a tool to tool comparison study of AIMS^TM fab 193 systems investigating parameters like: Normalized illumination uniformity, CD (critical dimension) uniformity over field, and static CD repeatability over time in x- and y-directions. The study is based on the evaluation of a data base collected with typical feature sizes of 1μm on the mask, ensuring with such feature sizes that tool results are independent of mask features being close to the resolution limit or the printability capability. Typical settings are NA = 0.7 and circular sigma = 0.6 on a set of tools in the field as well as in-house. In addition the performance of the tools will be discussed in terms of a specific application, global CD mapping, for use in process control. It can be applied for different use in wafer fab and mask shop environment.

We investigated the defect printability of KrF attenuated PSM. To analyze the printability of PSM defects, the programmed defect mask was designed and fabricated. The programmed defect mask contains background pattern layer of 800nm contact holes. Various types and sizes of MoSi defects such as extensions, dots and holes were programmed on the background patterns. We used a KrF excimer step-and-scan exposure system for wafer printing test. Based on the experimental results, we defined the maximum non-printable defects size of MoSi defects and tested repair performance of current tools by comparing the printability of defect pattern between pre-repair and post-repair. In addition, we calculated CD of defected patterns by simulation and compared it with the print CD.

Attaining acceptable yields in the manufacture of advanced photomasks will require higher performance optical metrology tools. Key to improving these tools is the development of new ultraviolet light illumination sources that operate at the actinic wafer exposure wavelength, which is now projected to be 193 nm for the 65 and 45 nm device nodes. The use of an actinic light source for metrology facilitates imaging of photomask phase structures, and ensures that optical path difference measurements and printing simulations are performed in-band and are not subject to off-wavelength accuracy errors. We review the solid-state laser technologies that have been employed to generate 193 nm, and describe the development of a new solid-state 193 nm laser platform tailored specifically for high resolution photomask phase metrology. This source operates at a repetition rate of five-kilohertz, produces 2.5 mW average power with a spectral bandwidth of 10 pm and has excellent mode quality. Additionally, we present high-resolution, 200X-magnification photomask images obtained using this new illumination source.

EB lithography has a potential to successfully form hole patterns as small as 80 nm with a stencil mask. In a previous paper we proposed a technique using a HOLON dual-mode critical dimension (CD) SEM ESPA-75S in the transmission mode for CD measurement of line-and-space patterns on a stencil mask. In this paper we extend our effort of developing a CD measurement technique to contact hole features and determine it in comparison of measured values between features on mask and those printed on wafer. We have evaluated the width method and the area methods using designed 80-500 nm wide contact hole patterns on a large area membrane mask and their resist images on wafer printed by a LEEPL3000. We find that 1) the width method and the area methods show an excellent mask-wafer correlation for holes over 110 nm, and 2) the area methods show a better mask-wafer correlation than the width method does for holes below 110 nm. We conclude that the area calculated from the transmission SEM image is more suitable in defining the hole dimensions than the width for contact holes on a stencil mask.

The 65nm photomasks have to meet tight specifications and improve the production yield due to high production cost. The 65nm optical lithography has two candidates, 157nm and 193nm, and we are developing two types of experimental photomask repair systems, FIB and EB, for the 65nm generation. We designed and developed experimental EB and FIB system that are beta systems. The construction of these systems was the same design except the each column. The platforms of beta systems consist of anti-vibration design to reduce outer disturbance for repair accuracy. Furthermore, we developed a new CPU control system, especially the new beam-scanning control system that makes it possible to control the beam position below nanometer order. These developments will suppress transmission loss and improve repair accuracy of the systems. We also adopt the 6-inch mask SMIF pod system and the CAD data linkage system that matches the EB mask data image with the SED image to search defects in photomasks with sophisticated patterns such as OPC patterns. We evaluated the EB and FIB beta systems with AIMS, LWM and AFM. EB and FIB beta systems were able to deposit carbon film and etch chrome, quartz, and MoSi. Furthermore, We confirmed that repair accuracy is 3σ below 10nm and transmission is over 97%. We also confirmed that CAD linkage was able to repair sophisticated pattern completely. In this paper, we report the photomask defect repair experimental systems for the 65nm generation.

Selete is developing a series of defect inspection and repair systems for electron projection lithography (EPL) stencil mask infrastructure, that includes tools and software development, and also verification by EPL exposure systems. The work is carried out in collaboration with Dai Nippon Printing, Toppan Printing and HOYA. A system for defect inspection of EPL stencil mask is developed with TOKYO SEIMITSU and HOLON. Another system for defect repairs is developed with SII NanoTechnology. The performances of these systems need to be verified for their further improvement and optimization. In this paper, we verified a series of defect inspection and repair systems through a sequential process. We can say that EPL mask infrastructure is established and our work has made significant contribution to it.

It is an important task in 65nm generation to reduce process CD loss to get better pattern resolution and CD performance. As we know the main process CD loss is the etch process. This study is mainly in Cr etching process. Process CD loss reduction is one of critical issues in 65nm generation photomask fabrication to improve pattern resolution and total CD performance. The CD loss is mainly determined by etching process. Cr etching process is particularly important because the process decide the CD performance for not only binary mask but also phase shift mask. So, we focused on Cr etching process in this study. For Cr etch, the masking material is a soft-etchable photo-resist. The resist behavior in the etch process strongly affects the Cr etching performance. In our study, the resist we used is Chemical Amplified Resist. We devoted to reduce the CD loss during etching process by optimizing the etching parameter through a designed experiment (DoE). And we studied about the relation of etching bias with the parameter and the relation of etching bias with other etching property. Then we discussed about the over-etching time with the bias loss. The etching uniformity is strongly affected in the plasma etch optimization, including proximity CD bias, CD radial, and Cr loading effect. So these factors will be checked throughout our optimization study.

Mask fabrication rules can interfere with the ability of OPC and RET shape generation to achieve the best lithographic quality on silicon. With low k1 lithography, ideal correction shapes dictated by lithography-based simulation frequently violate mask geometry constraints. Because the scaled spatial bandwidth of the wafer lithography process is lower than that of the mask process there are some degrees of freedom in OPC shape generation to optimize for lithographic accuracy and mask compliance together. In this paper we discuss strategies to embed mask rule compliance in correct-by-construction model-based OPC.

Resolution enhancement techniques and OPC(Optical Proximity Correction) have been developed with empirical data points from general test patterns and some actual patterns extracted from full-chip design. Lithography simulation tools have been used for intensive process simulation to optimize RET solutions using sample patterns to cover whole full-chip patterns. However, as design complexity increases and mask manufacturing rules restrict process proximity correction coverage, post-RET/OPC data can generate fatal patterning failures at locations where the process window is marginal. Therefore, it is necessary to identify those patterns from full-chip layout to choose proper RET/OPC solutions. Previously, it was proven that model based full-chip verification tool is useful to capture potential fatal patterning failures before mask tape-out sign-off for sub-wavelength lithography processes. [1] In this paper, we extended the full-chip verification methodology to quantitative RET/OPC development using database error analysis. First, using GDS data containing design intent only and a single 90nm lithography process calibrated model, we performed full-chip verification for linearly scaled designs through 130nm, 90nm and 65nm node to take OPC directions. Second, a standard OPC recipe was applied for each design node followed by verification. And then, potential pattern failures at 65nm node were analyzed through lithography process window. Finally, RET/OPC solution was discussed for 65nm design.

In this paper we present new development of intellectual properties(IP) protection software using OASIS format. By taking advantage of repetition presentation of OASIS, it becomes possible to express arrayed patterns without any generation of new cells, which also brings less overhead and further compaction of the result file. As a result, we could rebuild the hierarchy without cell generation and reduce the output file size. The experimental results show that there are no redundant cells generated and the file size has become 5 to 8 times smaller than conventional methods.

We have developed a unified mask data format named “OASIS.NEO¹” for Variable-Shaped-Beam (VSB) EB writers as enhancement of unified mask data format named “NEO²”. OASIS.NEO is a pattern data format based on OASIS^TM3 released as GDSII replacement by SEMI. We have developed OASIS.NEO for practical use of unified mask data formats in mask data preparation (MDP) flow. For practical use, it is necessary to input OASIS.NEO data directly to VSB EB writers just like the native EB data. So we have defined restrictions on OASIS for VSB EB writers referring the restrictions in NEO based on GDSII named “GDSII.NEO⁴”. In this paper we proposed the specification of OASIS.NEO.

The challenges, mask manufacturing is faced with, are more and more dominating the semiconductor industry as the pattern sizes shrink. Today's mask patterns have reached sizes that are common in wafer manufacturing. Looking into the industry, we can see that some of the quality parameters - such as CD uniformity and defect control - are managed better in wafer than in mask manufacturing. Consequently, mask manufacturers have started to apply more wafer processing techniques to mask processes. Among others, develop process has a great impact on the quality of the mask manufacturing. This contribution describes how Tokyo Electron Limited (TEL) scanning (linear drive nozzle) developer processing (widely used in advanced wafer manufacturing) was adapted for mask development. Out of this technology transfer, a new alpha-type mask develop tool was launched at TEL and an evaluation of this tool was carried out at the Advanced Mask Technology Center (AMTC), Dresden, Germany. Target of this collaboration was to successfully transfer wafer processing technology to mask making. By this, valuable information was generated, that has been implemented into the production platform, which is commercialized since first half of 2004.

Producing smaller feature sizes by extending current and near-term lithographic printing tools is a cost-effective strategy for high-volume production of integrated circuits. The hardbake process, as an annealing step to strengthen resist structures, includes a desirable thermal reflow that can facilitate this objective. Thermal reflow of polymer-based resists is a phase-dependent phenomenon in which a polymeric material with recyclable/reversible thermal characteristics experiences dimensional changes through relaxation during thermal cycling at hardbake. Unlike polymer melts, resist reflow is accompanied by a continuous change in the physical state of the resist over a specific temperature range, so it can be described on the basis of the relaxation modulus-temperature relation. Resist behavior during thermal transitions (e.g., glassy, leathery, rubbery plateau, etc.) can effectively be classified into either solid or viscous, depending on whether the resist material is below or above the characteristic glass transition temperature. In general, resist contact hole size can be significantly reduced by optimizing the principal factors driving resist reflow, i.e., temperature-dependent material properties, bake cycle parameters, contact-hole dimensions, and the type of contact array. Recognizable size reduction of the contact hole appears as the resist passes through the leathery state, and its maximum permanent deformation after thermal cycling completely depends on the resist material used. This research focuses on a bake profile of the resist described by the parameters in typical three-stage proximity contact wafer processing. Simulation programs were developed to characterize the primary thermal properties and process parameters affecting the bake profile, and to identify their relative effects on the resist contact-hole response.

In photomask manufacturing, the corner and the edge of the photomask are stained by photo-resist after coating. Since such resist remains cause the particles when substrates are transferred inside the photomask manufacturing equipment, it is important to remove the stained areas. The scanning type photomask edge resist remover developed this time enables a rapid and accurate resist removal compared with similar type tool. Besides, the edge remover reduces the process time of edge resist removal to set slightly narrowing the removal width. The removal speed varies according to removal conditions; it decreases when the resist film density is high such as after the pre-bake. When determining removal conditions, defect and linearity of resist removal line should be well considered as well as the removal speed. It is important to define a balance among the thinner dispense rate, N2 flow and exhaust pressure to prevent defects and optimize the arm velocity to obtain good linearity of resist removal line. With this new edge resist remover, it is also possible to make a complex removal line that is difficult by conventional technology.

We investigated the film property and the lithographic performance of five commercialized NCARs. This report focused on Cr effect and PCD stability which are critical issues on advanced mask making. Results confirmed to solve the Cr effect by controlled dissolution rate of resist film. Furthermore, PCD was occurred by PAG moving and unsuitable reaction in the resist film standing delay time. This report suggests the strategy that was design of chemical structure for the next generation NCARs.

The push for smaller linewidths and tighter critical dimension (CD) budgets forced manufacturers of optical pattern generators to move from traditional i-line to deep ultraviolet (DUV) resist processing. Entering the DUV area was not without pain. The process conditions, especially exposure times of a few hours, put very tough demands on the resist material itself. However, today 248nm laser writers are fully operating using a resist process that exhibits the requested resolution, CD uniformity and environmental stability. The continuous demands of CD performance made Micronic to investigate suitable resist candidate materials for the next generation optical writer using 193nm excimer laser exposure. This paper reports on resist benchmarking of one commercial as well as several newly developed resists. The resists were investigated using a wafer scanner. The data obtained illustrate the current performance of 193nm photoresists, and further demonstrate that despite good progress in resist formulation optimization, the status is still a bit from the required lithographic performance.

We manufactured LEEPL masks for 65-nm node and evaluated the masks for the critical dimension (CD), image placement (IP) and defects. Although the CD uniformity was 8.0 nm (3σ), an improvement is promising by resist upgrading. The CD linearity was within 5 nm (3σ) through the range of 80- to 300-nm width and the 65-nm hole patterns were successfully resolved. The local and global IP errors obtained were 23.2/16.4 nm and 8.76/6.66 nm (in the x/y directions), respectively. A defect inspection was conducted and detected defects were classified. Most of the defects were miss-placement and miss-size, which seemed to be non-killer defects. On the other hands, foreign materials that must be killer defects were analyzed using energy dispersion X-ray (EDX) and found that they consist of Si. Si fragments mainly came from strut walls and by employing new backside-etching conditions, we improved roughness of strut walls. As a result, no closed defects were detected.

The International Technology Roadmap for Semiconductors requires improvements in resolution for each lithographic node. In order to meet the resolution requirements for the sub-65-nm nodes, image placement (IP) errors induced by chucking the mask during e-beam patterning, metrology, and exposure must be characterized and minimized. This study focused on a 200-mm electron projection lithography (EPL) stencil mask designed for high throughput. Finite element models were developed to simulate the response of the mask throughout a typical fabrication process flow, including the electrostatic chucking during e-beam patterning and EPL exposure. The results of this predictive study were used to identify the primary sources of IP error as a function of the system parameters.

A new idea of writing a PXL (Proximity X-ray Lithography) mask is presented, in which a EUVL (extreme ultraviolet lithography) exposure tool is used as a mask repeater. EUV power of less than 1W is enough to write a PXL mask within 5 minutes, and an expensive EUV mask blank can be recycled because the mother mask is not necessary once a PXL mask is written. A EUV mask repeater especially consisting of a high-NA Micro Exposure Tool (MET) makes it possible to write a PXL mask for the 32 nm nodes and after. The new system can also be applied to other lithography tools using a 1X: such as LEEPL (Low Energy E-Beam Proximity Lithography) and imprint lithography.

Optical Proximity Correction (OPC) can be formulated as a constrained optimization problem. The constraints are mask constraint rules for space and width. These are sometimes called Mask Rule Checks (MRC), or Design Rule Checks (DRC). At 90nm and below, intelligent constraint handling is required for good OPC. In this paper, we show a technique for OPC constraint checking which is built in to the OPC feedback algorithm. The system is flexible enough to allow relaxed rules for corner-to-corner checking versus edge-to-edge checking. Also, the system can categorize checks by the length of the edges being compared. Lastly, the system can create special checks from line-ends to other features, or any user-defined edge type to any other user-defined edge type. In addition, we present a method for multiple layer enclosure rules which can be used for multiple exposure OPC. These enclosure constraints are useful for assurance of overlay tolerance.

Current model based OPC software operates under a set of simple guiding principles. First, a design is fragmented into finitely sized segments, the sizes and numbers of which are limited by run-time and mask constraints. Within each fragment the intensity (aerial image) and edge-placement error (EPE) are calculated at a single location. Finally, the length of the entire fragment is moved to correct for the EPE at that location. Although the computation of intensity and EPE are “model based”, the fragmentation and simulation site placement are typically “rules based”. Problems with this methodology can arise whenever the location of the fragments and simulation points are non-optimal. This can be of particular concern with very low-k1 lithography employing hard off-axis illumination, where aerial image “ripples” are a known issue. The authors will propose several solutions to these issues involving model based optimization and placement of fragments and simulation sites.

A 65 nm node mask is required to have total alignment accuracy of 20 nm (3σ) or less for 1st and 2nd layers, including the positional accuracy of each layer. We have developed a new electron beam mask lithography process using “alignment-and-height” marks to minimize the displacement between two layers resulting from additional bowing and contraction on the blank surface after the 1st layer exposure. The new process consists of the following steps: 1. Write “alignment-and-height” marks on the edge of a mask simultaneously with the pattern of the 1st layer. 2. Measure the position and height of “alignment-and-height” marks before writing the 2nd layer. 3. Create a position/height correction map to write the 2nd layer. 4. Write the 2nd layer with reference to the correction map. Basic system attributes, such as beam origin and positional drift of mask blank, are monitored and adjusted throughout the process. We tested the process and achieved an alignment accuracy of 20 nm (3σ) between 1st and 2nd layers regardless of the density of the pattern area ratio, confirming that the process is effective for 65 nm node phase shift mask exposure.

This paper presents Line Edge Roughness (LER) characterization for Tower Semiconductor 0.13um Standard Logic technology with advanced OPC modeling. First the applicability of top-view CD-SEM and AFM for LER measurement of poly-Si transistor gate characterization is studied. Then the influence of aerial image contrast and the gradient of the photoactive component on LER is reviewed and the possibility of minimizing LER by optimizing process conditions is considered. Finally the impact of LER on OPC model accuracy is reviewed. Model predictability with and without LER taken into account is compared.

Sub-resolution assist features (SRAFs) are non-printing features arranged on a mask layout to “assist” the lithographic performance of the lines intended to be printed on the wafer [1]. SRAFs typically are narrow lines located adjacent to the target figure edges. Current practice is to synthesize SRAFs with a rule-based methodology where the assist feature placement is dictated by combinations of feature width and spacing parameters. Optical behavior with off-axis illumination is complex and requires an elaborate set of SRAF synthesis rules. Creating and maintaining a robust set of placement rules guaranteed to work properly for arbitrary configurations is very difficult. Socha, et al, have demonstrated that the optimum configurations for SRAFs can be derived from the aerial image of the target layout configuration [2]. In this paper we show how SRAF synthesis can be optimally implemented in an OPC tool environment, leveraging lithography simulation.

Chrome-less Phase Lithography (CPL) technology is introduced as one of the key Resolution Enhancement Technologies for the application of 90 and 65nm node logic gate layer. From the view point of mask manufacturing, one of the strong points is that it doesn’t require complicated data division process into two complementary patterns, such as for double exposure AAPSM technology, and is possible to prepare the data by extension of EAPSM design technology. Another is the point of having a good wafer printing performance which is not inferior to AAPSM by giving the optimum exposure condition for a pattern. Although the optimization of OPC tuning is required, if a perfect mask manufacturing process is developed, it will be considered very feasible RET technology. While a mask process is important, establishment of inspection and repair technology is also very important. We have designed and fabricated a CPL defect test mask which has 90nm and 65nm technology nodes Line patterns for ArF lithography. By using this defect test mask, we will report defect detectability which was evaluated by several inspection systems. And also we will show the defect printability results by Zeiss MSM193 simulation microscope to confirm how the defect will affect to printing results. We also show repair performance of RAVE Nano-machining technology with the confirmation of printability by AIMS tool. Finally, we will discuss about when and how many inspections will be required in the CPL mask process.

As IC design rules shrink dramatically while the wavelength reduction in exposure systems can not keep up, extensive usage of Litho RET, Etch trimming and OPC techniques has become common practice in the integrated patterning flow. We examined a large number of CD measurement datasets of 90nm Contact layer ADI and AEI CD. As the etch bias is not a constant through pitch, AEI contribution has to be incorporated in the OPC model. Based on these datasets, we tried to develop a non-constant AEI model. In this paper, we investigated various strategies to streamline OPC modeling. Multiple regression method is used to fit CTR and CTE models. It was revealed that an extra long range Loading Kernel, additional to a well-fitted ADI model, may not successfully meet the fitting criteria we want. Mainly due to the fact that models with too many eigenvectors would have a tendency to over-fit-and-correct CD curves. We introduced an alternative approach by limiting the number of parameters in our model OPC algorithm. We achieved a 90nm Contact Model with OPC empirical data fitting error within +-2nm. Lastly, the wafer verification datasets showed only 3σ = 7.82 nm of through-pitch OPC residual error by using this Constant Threshold Etch Model, compared to simulation residue error 3σ of 8 nm.

For 90nm node generation, 65nm, and beyond, dark field mask types such as contact-hole, via, and trench patterns that all are very challenging to print with satisfactory process windows for day-to-day lithography manufacturing. Resolution enhancement technology (RET) masks together with ArF high numerical aperture (NA) scanners have been recognized as the inevitable choice of method for 65nm node manufacturing. Among RET mask types, the alternating phase shifting mask (AltPSM) is one of the well-known strong enhancement techniques. However, AltPSM can have a very strong optical proximity effect that comes with the use of small on-axis illumination sigma setting. For very dense contact features, it may be possible for AltPSM to overcome the phase conflict by limiting the mask design rules. But it is not feasible to resolve the inherent phase conflict for the semi-dense, semi-isolated and isolated contact areas. Hence the adoption of this strong enhancement technique for dark filed mask types in today’s IC manufacturing has been very limited. In this paper, we report a novel yet a very powerful design method to achieve contact and via masks printing for 90nm, 65nm, and beyond. We name our new mask design as: Novel Improved Contact-hole pattern Exposure PSM (NICE PSM) with off-axis illumination, such as QUASAR. This RET masks design can enhance the process window of isolated, semi-isolated contact hole and via hole patterns. The main concepts of NICE PSM with QUASAR off-axis illumination are analogous to the Super-FLEX pupil filter technology.

A methodology and a Monte Carlo simulation flow with integrated LSI Logic's OPC package, Molotof, was applied to the 65nm poly line sensitivity analysis. Strong phase shift mask (sPSM) manufacturing specifications were optimized to obtain image critical dimensions (CD) and image placement errors (IPE) complying with technology design rules. Reticle manufacturing statistical errors of phase depth, phase width, and phase intensity imbalance were used to generate a virtual sPSM for imaging poly lines. A criterion for qualifying reticle specification is to obtain all latent image CDs and IPEs within a design rule allowed range for a given mask specification. The approach allows for computing reticle and litho budgets into CD imaging performance. We present simulation and empirical results of statistical analysis of the 65nm poly line (clear field) printability, and a method for optimizing a strong phase shift reticle specification. Sensitivity to a single parameter variation and full statistical analysis of the 65nm poly line imaging performance affected by manufacturing errors is presented. The optimum reticle specification, yielded 100% of critical dimensions and image placement errors, was found in simulation and confirmed by empirical data.

In this article, we analyzed in-field uniformity (IFU) on wafer considering exposure margin [linewidth variation (nm) per % exposure dose variation (%)] and the MEEF (mask error enhancement factor). As gate linewidth becomes smaller, the controllability of in-field uniformity (IFU) plays a key role in wafer manufacturing yield. IFU depends on various lithography parameters including mask CD (critical dimension) uniformity, MEEF, exposure margin, focus margin, transmittance, flare and illumination uniformity. In real world, the combination of wafer exposure machine and mask characteristics should be carefully considered to achieve better IFU on wafer. This presentation discusses the various experimental works including CD uniformity on mask, IFU on wafer, MEEF, exposure margin and wafer exposure machine. CD uniformity data on mask and IFU data on wafer is obtained from optical measurement tool to reduce measurement error disregarding local CD variation. Even though one handles a unit pattern, various MEEF exists in a unit pattern in case of complex pattern. In addition, the MEEF varying with the area across one mask degrades IFU on a wafer. IFU on a wafer is predictable using mask CD uniformity and exposure margin mean. Variation of exposure margin is the measure of stability of photo process. In manufacturing devices, mask and Litho. Tool should be well harmonized to achieve better IFU and a higher manufacturing yield. The photo process including resist process should be well controlled to get stability, as well as mask CD uniformity.

To obtain a high throughput and good CD uniformity, the EUV reflectivity of EUVL masks must be high and very uniform. In this study, EUVL masks were fabricated, and the degradation in EUV reflectivity due to the fabrication process was evaluated. The damage to the multiplayer due to plasma etching appeared as a drop in peak reflectivity of about 2.0%. Etching the Cr buffer layer by a wet process reduced the value to within the measurement error. On the other hand, thermal damage appeared as both a drop in peak reflectivity and a shift in centroid wavelength. The drop in peak reflectivity was about 0.5-1.0% in the temperature range 140-240° C, and about 1.5% in the temperature range 260-280°C. The shift in centroid wavelength increased monotonically as the temperature rose from 180degrees C to 280°C. To ensure good CD uniformity, both the shift and the variation in centroid wavelength should be kept within ∓0.02 nm. If a drop in peak reflectivity of 1-2% is acceptable, annealing could be an effective way to adjust the centroid wavelength by as much as 0.10 nm with an accuracy of ∓0.01 nm.

CLEARCERAM®-Z HS is a low thermal expansion glass-ceramics and has been used in semiconductor industry field as well as for various precision applications. Extreme Ultra Violet Lithography (EUVL) is one of the applications, in which future utilization of CLEARCERAM®-Z HS can be expected. Previous reports revealed that CLEARCERAM®-Z HS met the material requirements in the SEMI spec. This paper refers to the latest investigation results on the CTE & surface finish performance of CLEARCERAM®-Z HS relative to the SEMI spec. Also the data obtained from the development of new CLEARCERAM®-Z, which is designed for more fit with EUVL applications, will be presented and its advantageous potential for EUVL Photomask substrate application is to be discussed.

The development of a low-distortion mask is of prime importance to Extreme Ultraviolet (EUV) Lithography. The mask consists of a standard ultra low expansion (ULE®) substrate measuring 152.4 mm x 152.4 mm x 6.35 mm, with a 280 nm thick reflective multilayer deposited on the top surface. Nonflatness of the mask patterned surface will manifest itself as image placement errors on the device wafer. Bottom surface nonflatness can interfere with securely holding the mask in the patterning and exposure tools as well as exacerbating patterned surface nonflatness. Of great concern is the effect of the mounting technique employed in the patterning and exposure tools on mask flatness. One such design, the electrostatic pin chuck, consists of a 'bed of pins' on the top surface of the chuck that will support the EUV mask during patterning and exposure. The pin design has been proposed to minimize the likelihood of particulates becoming lodged between the mask and chuck that would adversely distort the mask. To ensure that a chuck of this design will minimize image placement errors while still securely holding the mask, three-dimensional finite element (FE) models have been created to predict the influence of the electrostatic pin chuck on mask flatness. Legendre polynomials were used as input to the models to represent experimentally-measured substrate bottom surface shapes. The FE results illustrate that mechanical modeling provides an invaluable tool for quantifying the influence of mounting techniques on mask flatness, and, ultimately optimizing system parameters to successfully meet the stringent requirements at the 45-nm node (and below).

Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. The SiO₂ buffer dry etching is a crucial step in the manufacture of the EUV mask due to stringent CD and reflectance requirements. In contrast to conventional chromium absorber layers new absorber materials e.g. TaN require an adjustment of the SiO₂ buffer etch chemistry and process parameters to avoid a strong influence on the initial absorber profile and thickness. We have developed a SiO₂ buffer dry etch process that uses the structured TaN absorber as masking layer. A laser reflectometer was used during the SiO₂ dry etch process for process control and endpoint detection. Different dry etch processes with SF₆/He, CF₄ and CHF₃/O₂ etch chemistry have been evaluated and compared with regard to TaN- and SiO_2- etch rate, TaN- and SiO₂ etch profile and Si capping layer selectivity. We focused our work on minimum feature sizes and simultaneous etching of different line (e.g. dense- and isolated lines) and hole patterns. Line and contact hole structures with feature sizes down to 100nm have been realized and characterized in a SEM LEO 1560. The whole mask patterning process was executed on an advanced tool set comprising of a Leica SB 350 variable shaped e-beam writer, a blank coater Steag HamaTech ASR5000, a developer Steag HamaTech ASP5000 and a two chamber UNAXIS mask etcher III.

Extreme Ultraviolet (EUV) masks are composed of EUV-reflective regions (multilayer) and of EUV-absorbing regions (patterned areas). The choice of materials for the absorbing stack (i.e. the buffer layer and the absorber layer) is crucial for providing good optical performances. This choice has to take into account three major issues: optical aspects (EUV and DUV performances, aerial image); repair feasibility and technological feasibility (deposition, etching, stripping...); ageing and utilization aspects: stability of the stack, cleaning capability. In this paper, a new absorbing stack A/B is proposed: this stack completely fulfils optical specifications and its total thickness is much lower than those found in the literature, with absorbing materials like TiN, Cr or TaN for instance. This thin thickness enables to reduce shadowing effects, which is particularly interesting for very advanced nodes. Experimental studies were then carried out on this new stack. We focused on two major topics: low temperature deposition and wet etching feasibility of B-material.

Defect printability and inspection studies were conducted on a programmed EUV defect mask. The mask was fabricated using Ta-based absorber stack on a Mo/Si multilayer coated 6025 plate. The defect pattern contains a variety of types of defects. The defect printing was performed on the Engineering Test Stand (ETS), which is the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The result showed that the printability of defects depended on the defect type and that either notches in or protrusions from absorber lines were the first to print. The minimum printable defect size was approximately 15 nm (1X). Defect inspection was performed on a 257-nm wavelength mask inspection system in die-to-die mode. Seventy-eight out of 120 programmed defects were detected when using 50% detection sensitivity. Maximum detection sensitivity was also tried. However, the number of defects is overwhelmed by the nuisance defects. The minimum defect detected was 52 nm in width. Simulations with a 2-D scalar model are used to verify the results.

EUVL mask process of absorber layer, buffer layer dry etching and defect repair were evaluated. TaGeN and Cr were selected for absorber layer and buffer layer, respectively. These absorber layer and buffer layer were coated on 6025 Qz substrate. Two dry etching processes were evaluated for absorber layer etching. One is CF4 plasma process and the other is Cl2 plasma process. Etch bias uniformity, selectivity, cross section profile and resist damage were evaluated for each process. Disadvantage of CF4 plasma process is low resist selectivity and Cl2 plasma process is low Cr selectivity. CF4 plasma process caused small absorber layer damage on isolate line and Cl2 plasma process caused Cr buffer layer damage. To minimize these damages overetch time was evaluated. Buffer layer process was also evaluated. Buffer layer process causes capping layer damage. Therefore, etching time was optimized. FIB-GAE and AFM machining were applied for absorber layer repair test. XeF2 gas was used for FIB-GAE. Good selectivity between absorber layer and buffer layer was obtained using XeF2 gas. However, XeF2 gas causes side etching of TaGeN layer. AFM machining repair technique was demonstrated for TaGeN layer repair.