This PDF file contains the front matter associated with SPIE Proceedings Volume 9781, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um² can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

As optical lithography and conventional transistor structure are approaching their physical limits, 3D vertical gate-all-around (GAA) nanowire MOSFETs and double-surrounding-gate (DSG) MOSFETs are two promising device candidates for post-FinFET logic scaling owing to their superior gate control and scaling potential. However, source, drain and gate of a vertical nanowire MOSFET and DSG MOSFETs are located in different physical layers. Consequently, structural design of IC devices/circuits, layout arrangement for high-density vertical nanowires/interconnects, and routing strategy are non-trivial challenges. In this paper, we shall discuss these critical issues for constructing standard cells using 3D vertical GAA nanowire MOSFETs and DSG MOSFETs. We redesigned the standard cells in Nangate Open Cell Library for 5nm node using vertical GAA nanowire MOSFETs and DSG MOSFETs. Experimental results verify the functionality of the proposed standard cell layout design approach.

Directed self-assembly (DSA), the epitaxial alignment of block copolymers to minimize the system free energy, is prone to defects that are random and difficult to eliminate. When creating fins for FinFET devices, the defect density is known to be a strong function of guide pattern CD. We propose the use of a restricted design rule (RDR) that limits the guide pattern CD to achieve low defectivity, and also report its impact on overall chip area and design-ability of logic, analog IO, and SRAM. The restricted design rule in defining guide pattern CD is extracted from empirical data. Design rule check (DRC) is applied to GLOBALFOUNDRIES' technology chip design to estimate the penalty of DSA RDR on fin layer.

Self-aligned double patterning (SADP) has been proposed as an alternative patterning solution for sub-10nm technology because of delay of advanced lithography beyond 193nm ArF. In conventional SADP, line and space style of dummy metal fills are inserted once main design is complete. A large buffer distance is required around the main design because no further verification of main design (in presence of fills) is performed. This causes irregular pattern density, which becomes a source of process variations. We propose integrated-fill, in which main design and dummy fill insertion are performed together. This requires a change in overall design flow, which we discuss. Integrated-fill is demonstrated in M2 layer of SADP process; M2 density increases by 15.7% with 2.3% reduction in standard deviation of density distribution; metal thickness variation is also reduced by 24%. More dummy fills cause increased coupling capacitance, which however is shown to be insignificant.

Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

As the IC industry moves forward to 7nm or 5nm node, the minimum pitch of back-end-of-line (BEOL) layers could be near 30nm. Extreme ultraviolet (EUV) could be the most cost effective solution for patterning critical metal and via layers. Patterning of the critical layers would need greater than 4x exposures using ArFi lithography, leading to severe cost and yield issues. There are two potential design options, one-dimension (1D) and two-dimension (2D), for metal 1 layer. EUV’s single exposure option offers superior image quality especially for the 2D design style, but scalability of a 2D design is limited by EUV with a fixed numerical aperture (NA). The single exposure of EUV is an appropriate patterning solution for printing a 1D design directly, but maintaining critical dimension uniformity (CDU) of lines and line-ends is a challenge. Scalability of the 1D design is also limited by the single exposure option. The 1D design can be patterned through a spacer film deposition to gain superior line CD control, followed by printing a cut or block pattern to create the line-ends. Since the minimum pitch of cut/block patterns is generally larger than the metal pitch, EUV’s single exposure option has a potential to print the cut/block pattern at smaller pitch and resolution and offers an opportunity to further design shrink. An elongated via design helps design scalability due to an insensitive overlay error contribution to via-to-metal contact area and encroachment.

In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quantify and measure design changes and the degree of layout regularization. This new approach allows engineers to perform a full profiling across all patterns that exist in design and without needing to explicitly specify what patterns to analyze.

At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.

During a new technology node process setup phase, foundries do not initially have enough product chip designs to conduct exhaustive process development. Different operational teams use manually designed simple test keys to set up their process flows and recipes. When the very first version of the design rule manual (DRM) is ready, foundries enter the process development phase where new experiment design data is manually created based on these design rules. However, these IP/test keys contain very uniform or simple design structures. This kind of design normally does not contain critical design structures or process unfriendly design patterns that pass design rule checks but are found to be less manufacturable. It is desired to have a method to generate exhaustive test patterns allowed by design rules at development stage to verify the gap of design rule and process.

This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.

A pattern-based methodology for optimizing Self-Aligned Double Patterning (SADP)-compliant layout designs is developed based on detecting cut-induced hotspot patterns and replacing them with pre-characterized fixing solutions. A pattern library with predetermined fixing solutions is built. A pattern-based engine searches for matching patterns in the layout designs. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution, preserving only the design rule check-clean replacements. The methodology is demonstrated on a 10nm routed block. A small library of fourteen patterns reduced the number of cut-induced design rule check violations by 100% and lithography hotspots by 23%.

As minimum feature sizes shrink, unexpected hotspots appear on wafers. Therefore, it is important to detect and fix these hotspots at design stage to reduce development time and manufacturing cost. Currently, as the most accurate approach, lithography simulation is widely used to detect such hotspots. However, it is known to be time-consuming. This paper proposes a novel aerial image synthesizing method using regression and minimum lithography simulation for only hotspot detection. Experimental results show hotspot detection on the proposed method is equivalent compared with the results on the conventional hotspot detection method which uses only lithography simulation with much less computational cost.

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose a variability-aware compact model characterization methodology based on stepwise parameter selection. Transistor I-V measurements are obtained from bit transistor accessible SRAM test array fabricated using a collaborating foundry’s 28nm FDSOI technology. Our in-house customized Monte Carlo simulation bench can incorporate these statistical compact models; and simulation results on SRAM writability performance are very close to measurements in distribution estimation. Our proposed statistical compact model parameter extraction methodology also has the potential of predicting non-Gaussian behavior in statistical circuit performances through mixtures of Gaussian distributions.

In this paper, we propose a novel modular patterning technology to reduce the edge-placement errors (EPE) significantly by combining alternating-material self-aligned multiple patterning (altSAMP) and selective etching processes. It is assumed that gates and fins are fabricated by the same type of altSAMP process as mixing two different processing techniques will drive up the manufacturing costs. Process variability induced circuit performance degradation is shown to be a serious issue as FinFET devices are scaled down to sub-10nm. We analyze the dependence of FinFET-based SRAM circuit performance on supply voltage, fin-width and gate-length variations. Improved device control with narrower fins helps to increase the static noise margin (SNM) in all SRAM cell designs. Higher supply voltage is also beneficial to the SNM performance. Our simulation results show that 6-T SRAM circuit design does not meet the six-sigma yield requirement when the half pitch is scaled down to sub-7 nm. To reduce the SRAM circuit variability, we study an 8-T SRAM cell and show that it significantly improves the SRAM performance.

Publisher’s Note: This paper, originally published on March 16th, was replaced with a corrected/revised version on March 28th. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

Interconnect corners should accurately reflect the effect of misalingment in LELE double patterning process. Misalignment is usually considered separately from interconnect structure variations; this incurs too much pessimism and fails to reflect a large increase in total capacitance for asymmetric interconnect structure. We model interconnect corners by taking account of misalignment in conjunction with interconnect structure variations; we also characterize misalignment effect more accurately by handling metal pitch at both sides of a target metal independently. Identifying metal space at both sides of a target metal.

Traditional RC extraction flows mostly consider interconnect thickness variations caused by etch and CMP processes in a way of rule-based approach where a form of tables or polynomials is used. While such rulebased approaches are easily incorporated into design flows, they are not inevitably accurate since tablelook- ups in rules are inherently taking simple (mostly one dimensional) typed patterns. Moreover, rules fail to account for the length scale and cumulative effects in both etch and CMP, thereby making them less accurate compared to physics-based models. In this paper, we introduce a model-based CMP aware RC extraction flow that uses the results of thickness simulations from Cadence CMP modeling tools. We apply the proposed model-based CMP aware RC extraction flow to several blocks in a 16 nm design, and compare the results of the proposed model-based flow with those of a traditional rule-based RC extraction flow. This paper also notes that running the model-based flow in conjunction with the traditional rule-based flow should cover the full range of RC variation along critical nets, and ensure faster timing closure.

Lithography hotspot detection in the physical verification phase is one of the most important techniques in today's optical lithography based manufacturing process. Although lithography simulation based hotspot detection is widely used, it is also known to be time-consuming. To detect hotspots in a short runtime, several machine learning based methods have been proposed. However, it is difficult to realize highly accurate detection without an increase in false alarms because an appropriate layout feature is undefined. This paper proposes a new method to automatically extract a proper layout feature from a given layout for improvement in detection performance of machine learning based methods. Experimental results show that using a deep neural network can achieve better performance than other frameworks using manually selected layout features and detection algorithms, such as conventional logistic regression or artificial neural network.

In this paper, we introduce a fast and reasonably accurate methodology to determine patterning difficulty based on the fundamentals of optical image processing techniques to analyze the frequency content of design shapes which determines patterning difficulties via a computational patterning transfer function. In addition, with the help of Monte- Carlo random pattern generator, we use this flow to identify a set of difficult patterns that can be used to evaluate the design ease-of-manufacturability via a scoring methodology as well as to help with the optimization phases of post-tape out flows. This flow offers the combined merits of scoring-based criteria and model-based approach for early designs. The value of this approach is that it provides designers with early prediction of potential problems even before the rigorous model-based DFM kits are developed. Moreover, the flow establishes a bi-directional platform for interaction between the design and the manufacturing communities based on geometrical patterns.

Multiple-Patterning Technology (MPT) is still the preferred choice over EUV for the advanced technology nodes, starting the 20nm node. Down the way to 7nm and 5nm nodes, Self-Aligned Multiple Patterning (SAMP) appears to be one of the effective multiple patterning techniques in terms of achieving small pitch of printed lines on wafer, yet its yield is in question. Predicting and enhancing the yield in the early stages of technology development are some of the main objectives for creating test macros on test masks. While conventional yield ramp techniques for a new technology node have relied on using designs from previous technology nodes as a starting point to identify patterns for Design of Experiment (DoE) creation, these techniques are challenging to apply in the case of introducing an MPT technique like SAMP that did not exist in previous nodes.

This paper presents a new strategy for generating test structures based on random placement of unit patterns that can construct more meaningful bigger patterns. Specifications governing the relationships between those unit patterns can be adjusted to generate layout clips that look like realistic SAMP designs. A via chain can be constructed to connect the random DoE of SAMP structures through a routing layer to external pads for electrical measurement. These clips are decomposed according to the decomposition rules of the technology into the appropriate mandrel and cut masks. The decomposed clips can be tested through simulations, or electrically on silicon to discover hotspots.

The hotspots can be used in optimizing the fabrication process and models to fix them. They can also be used as learning patterns for DFM deck development. By expanding the size of the randomly generated test structures, more hotspots can be detected. This should provide a faster way to enhance the yield of a new technology node.

As we move to advanced technology nodes, the requirements on within chip and across wafer planarity are becoming more demanding [1]. Also, the number of Chemical Mechanical Polishing (CMP) processes and steps used in microelectronic chip manufacturing is increasing rapidly, in an effort to meet the stringent planarity requirements [1]. However, the complex pattern dependencies inherent in CMP processes, and the cumulative nature of the topography generated by these processes make it challenging to meet the aforementioned stringent uniformity requirements for the variety of designs produced. Consequently, we expect to see an increased CMP and related hotspots on advanced node designs. Accurately detecting CMP and related hotspots (such as pooling, DOF hotspots, topography variation hotspots etc.) and providing guidelines to fix or prevent them is therefore critical for CMP process development, yield ramp up and shorter design and manufacturing cycles.

In this paper we present a hotspot detection and removal/prevention flow. The flow uses Cadence Design System’s manufacturing modeling methodology that predicts feature scale, within chip, and wafer level topography. The modeling methodology takes into account etch depth, deposition, and CMP variations across multiple levels in the design, and across multiple process steps within a given design level.

As technology moves towards more advanced nodes, the complexity of VLSI designs continues to grow and unexpected designs in physical layout push the process limits. In the beginning of a new technology node development there are not enough real design chips with complex structures and it is hard for foundries to comprehensively verify their process capabilities. It is necessary for foundries to generate a comprehensive set of test patterns to co-optimize the design rule manual (DRM) and manufacturing process. Furthermore, as the technology goes into an accelerated yield ramp phase, we need to find the potential process weak-points and identify the gaps between the design rules and the process.

This paper will present a novel methodology to enumerate initial test patterns based on other technology node products. With this novel methodology, DRM development and process capability verification can be sped up rapidly in comparison to a more traditional way. At the same time, the process weak-point signatures can be migrated from the older technology nodes to the new technology node for verification. This methodology will help foundries catch process detractor patterns at new technology early development stage.

As feature size of the semiconductor technology scales down to 10nm and beyond, multiple patterning lithography (MPL) has become one of the most practical candidates for lithography, along with other emerging technologies such as extreme ultraviolet lithography (EUVL), e-beam lithography (EBL) and directed self assembly (DSA). Due to the delay of EUVL and EBL, triple and even quadruple patterning are considered to be used for lower metal and contact layers with tight pitches. In the process of MPL, layout decomposition is the key design stage, where a layout is split into various parts and each part is manufactured through a separate mask. For metal layers, stitching may be allowed to resolve conflicts, while it is forbidden for contact and via layers.

In this paper, we focus on the application of layout decomposition where stitching is not allowed such as for contact and via layers. We propose a linear programming and iterative rounding (LPIR) solving technique to reduce the number of non-integers in the LP relaxation problem. Experimental results show that the proposed algorithms can provide high quality decomposition solutions efficiently while introducing as few conflicts as possible.

In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of litho masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where hole patterns are readily accessible through templated confinement of cylindrical phase BCP materials.

Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced.

For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.

For technologies beyond 10 nm, 1D gridded designs are commonly used. This practice is common particularly in the case of Self-Aligned Double Patterning (SADP) metal processes where Vertical Interconnect Access (VIA) connecting metal line layers are placed along a discrete grid thus limiting the number of VIA pitches. In order to create a Vertical Interconnect Access (VIA) layer, graphoepitaxy Directed Self-Assembly (DSA) is the prevailing candidate. The technique relies on the creation of a confinement guide using optical microlithography methods, in which the BCP is allowed to separate into distinct regions. The resulting patterns are etched to obtain an ordered VIA layer.

Guiding pattern variations impact directly on the placement of the target and one must ensure that it does not interfere with circuit performance. To prevent flaws, design rules are set. In this study, for the first time, an original framework is presented to find a consistent set of design rules for enabling the use of DSA in a production flow using Self Aligned Double Patterning (SADP) for metal line layer printing.

In order to meet electrical requirements, the intersecting area between VIA and metal lines must be sufficient to ensure correct electrical connection. The intersecting area is driven by both VIA placement variability and metal line printing variability. Based on multiple process assumptions for a 10 nm node, the Monte Carlo method is used to set a maximum threshold for VIA placement error.

In addition, to determine a consistent set of design rules, representative test structures have been created and tested with our in-house placement estimator: the topological skeleton of the guiding pattern [1]. Using this technique, structures with deviation above the maximum tolerated threshold are considered as infeasible and the appropriate set of design rules is extracted. In a final step, the design rules are verified with further test structures that are randomly generated using percolation in order to emulate a Placed and Routed (P&R) standard cell block.

To overcome the prohibitive barriers of edge-placement errors (EPE) in the cut/block/via step of complementary lithography, we propose a modular patterning approach by combining layout stitching, selective etching, and alternating-material self-aligned multiple patterning (altSAMP) processes. In this patterning approach, altSAMP is used to create line arrays with two materials alternatively which allow a highly selective etching process to remove one material without attacking the other, therefore more significant EPE effect can be tolerated in line-cutting step. With no need of connecting vias, the stitching process can form 2-D features by directly stitching two components of patterns together to create 2-D design freedom as well as multiple-CD/pitch capability. By adopting this novel approach, we can potentially achieve higher processing yield and more 2-D design freedom for continuous IC scaling down to 5 nm. We developed layout decomposition and synthesis algorithms for critical layers, and the fin/gate/metal layer from NSCU open cell library is used to test the proposed algorithms.

One of the key challenges while scaling logic down to N7 and N5 is the requirement of self-aligned multiple patterning for the metal stack. This comes with a large cost of the backend cost and therefore a careful stack optimization is required. Various layers in the stack have different purposes and therefore their choice of pitch and number of layers is critical. Furthermore, when in ultra scaled dimensions of N7 or N5, the number of patterning options are also much larger ranging from multiple LE, EUV to SADP/SAQP. The right choice of these are also needed patterning techniques that use a full grating of wires like SADP/SAQP techniques introduce high level of metal dummies into the design. This implies a large capacitance penalty to the design therefore having large performance and power penalties. This is often mitigated with extra masking strategies. This paper discusses a holistic view of metal stack optimization from standard cell level all the way to routing and the corresponding trade-off that exist for this space.

In a sub 2Xnm node process, the feedback of pattern weak points is more and more significant. Therefore, it is very important to extract the systemic defect in Double Patterning Technology(DPT), however, it is impossible to predict exact systemic defect at the recent photo simulation tool.[1] Therefore, the method of Process Window Qualification (PWQ) is very serious and essential these days.

Conventional PWQ methods are die to die image comparison by using an e-beam or bright field machine. Results are evaluated by the person, who reviews the images, in some cases. However, conventional die to die comparison method has critical problem. If reference die and comparison die have same problem, such as both of dies have pattern problems, the issue patterns are not detected by current defect detecting approach. Aside from the inspection accuracy, reviewing the wafer requires much effort and time to justify the genuine issue patterns. Therefore, our company adopts die to data based matching PWQ method that is using NGR machine. The main features of the NGR are as follows. First, die to data based matching, second High speed, finally massive data were used for evaluation of pattern inspection.[2] Even though our die to data based matching PWQ method measures the mass data, our margin decision process is based on image shape. Therefore, it has some significant problems.

First, because of the long analysis time, the developing period of new device is increased. Moreover, because of the limitation of resources, it may not examine the full chip area. Consequently, the result of PWQ weak points cannot represent the all the possible defects. Finally, since the PWQ margin is not decided by the mathematical value, to make the solid definition of killing defect is impossible.

To overcome these problems, we introduce a statistical values base process window qualification method that increases the accuracy of process margin and reduces the review time. Therefore, it is possible to see the genuine margin of the critical pattern issue which we cannot see on our conventional PWQ inspection; hence we can enhance the accuracy of PWQ margin.

The concept of the multi-source focus correlation method was presented in 2015 [1, 2]. A more accurate understanding of real on-product focus can be obtained by gathering information from different sectors: design, scanner short loop monitoring, scanner leveling, on-product focus and topography.

This work will show that chip topography can be predicted from reticle density and perimeter density data, including experimental proof. Different pixel sizes are used to perform the correlation in-line with the minimum resolution, correlation length of CMP effects and the spot size of the scanner level sensor. Potential applications of the topography determination will be evaluated, including optimizing scanner leveling by ignoring non-critical parts of the field, and without the need for time-consuming offline topography measurements.

In this paper, we examine two types of 2-D layout design methodology (via connecting and direct stitching) for future IC scaling. The yield model for via landing process is first developed based on the probability-of-success (POS) function, which incorporates the overlay errors and via CD variations. A layout library is constructed using the 2-D patterns in 45-nm and 15-nm open cell libraries, and the basic stitching structures are identified. Six commonly seen stitching structures in our layout library are analyzed. The optimization methods for via landing and direct stitching are discussed. We compare the yield performance of via landing and direct stitching (with and without optimization). It is found that direct-stitching yield is better than the via-landing yield for all types of vias in the 2-D layouts we examined, regardless of whether the optimization procedure is performed.

Looking for the highest density and best performance, the 14nm technological node saw the development of aggressive designs, with design rules as close as possible to the limit of the process. Edge placement error (EPE) budget is now tighter and Reticle Enhancement Techniques (RET) must take into account the highest number of parameters to be able to get the best printability and guaranty yield requirements. Overlay is a parameter that must be taken into account earlier during the design library development to avoid design structures presenting a high risk of performance failure.

This paper presents a method taking into account the overlay variation and the Resist Image simulation across the process window variation to estimate the design sensitivity to overlay. Areas in the design are classified with specific metrics, from the highest to the lowest overlay sensitivity. This classification can be used to evaluate the robustness of a full chip product to process variability or to work with designers during the design library development. The ultimate goal is to evaluate critical structures in different contexts and report the most critical ones.

In this paper, we study layers interacting together, such as Contact/Poly area overlap or Contact/Active distance. ASML-Brion tooling allowed simulating the different resist contours and applying the overlay value to one of the layers. Lithography Manufacturability Check (LMC) detectors are then set to extract the desired values for analysis.

Two different approaches have been investigated. The first one is a systematic overlay where we apply the same overlay everywhere on the design. The second one is using a real overlay map which has been measured and applied to the LMC tools. The data are then post-processed and compared to the design target to create a classification and show the error distribution. Figure:

Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. To verify the interlayer design, we have developed the interlayer design verification methodology using contour image. Our methodology makes it possible to verify interlayer design visually by extracting the contour image from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a statistical analysis of massive measured data. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design.

In order to resolve the causality dilemma of which comes first, accurate design rules or real designs, this paper presents a flow for exploration of the layout design space to early identify problematic patterns that will negatively affect the yield.

A new random layout generating method called Layout Schema Generator (LSG) is reported in this paper, this method generates realistic design-like layouts without any design rule violation. Lithography simulation is then used on the generated layout to discover the potentially problematic patterns (hotspots). These hotspot patterns are further explored by randomly inducing feature and context variations to these identified hotspots through a flow called Hotspot variation Flow (HSV). Simulation is then performed on these expanded set of layout clips to further identify more problematic patterns.

These patterns are then classified into design forbidden patterns that should be included in the design rule checker and legal patterns that need better handling in the RET recipes and processes.

Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.

Self-Aligned-Double-Patterning (SADP) is a potential technology for metal layers in N10 and beyond nodes. SADP manufacturing process comes with lots of challenges. Several approaches were introduced to manufacture SADP. The most major SADP manufacturing approach is the Spacer-Is-Dielectric (SID). One of the main advantages of SADP over Litho-Etch-Litho-Etch (LELE) Double Patterning (DP) is better Mask Overlay Control. In addition, SADP results in better process tolerance and lower Line-Width Roughness. In this paper, we propose a model-based manufacturing flow for SID-SADP approach. The flow includes: (1) SADP Patterns Decomposition, (2) Etch Retargeting, (3) Sub Resolution Assist Features (SRAF) Insertion, (4) Optical Proximity Correction (OPC) process, and finally (5) Verification. The motivation beyond developing this flow is to find the least number of needed masks to achieve satisfactory imaging quality, and to characterize possible challenges in each step of the flow. Consequently, we highlight the challenges and the proposed techniques we examined to meet this objective.

At the advanced technology node, logic design has become extremely complex and is getting more challenging as the pattern geometry size decreases. The small sizes of layout patterns are becoming very sensitive to process variations. Meanwhile, the high pressure of yield ramp is always there due to time-to-market competition. The company that achieves patterning maturity earlier than others will have a great advantage and a better chance to realize maximum profit margins.

For debugging silicon failures, DFT diagnostics can identify which nets or cells caused the yield loss. But normally, a long time period is needed with many resources to identify which failures are due to one common layout pattern or structure. This paper will present a new yield diagnostic flow, based on preliminary EFA results, to show how pattern analysis can more efficiently detect pattern related systematic defects. Increased visibility on design pattern related failures also allows more precise yield loss estimation.

Among various electron-beam lithography (EBL) techniques, variable-shaped beam (VSB) and character projection (CP) methods have attracted many EBL users for their high-throughput feature, but they are considered to be more suited to small-featured VLSI fabrication with regularly-arranged layouts like standard-cell logics and memory arrays. On the other hand, non-VLSI applications like photonics, MEMS, MOEMS, and so on, have not been fully utilized the benefit of CP method due to their wide variety of layout patterns. In addition, the stepwise edge shapes by VSB method often causes intolerable edge roughness to degrade device characteristics from its intended performance with smooth edges.

We proposed an overall EBL methodology applicable to wade-variety of EBL applications utilizing VSB and CP methods. Its key idea is in our layout data conversion algorithm that decomposes curved or oblique edges of arbitrary layout patterns into CP shots. We expect significant reduction in EB shot count with a CP-bordered exposure data compared to the corresponding VSB-alone conversion result. Several CP conversion parameters are used to optimize EB exposure throughput, edge quality, and resultant device characteristics.

We demonstrated out methodology using the leading-edge VSB/CP EBL tool, ADVANTEST F7000S-VD02, with high resolution Hydrogen Silsesquioxane (HSQ) resist. Through our experiments of curved and oblique edge lithography under various data conversion conditions, we learned correspondence of the conversion parameters to the resultant edge roughness and other conditions. They will be utilized as the fundamental data for further enhancement of our EBL strategy for optimized EB exposure.

A fast and inexpensive scheme for etch rate prediction using flexible continuum models and Bayesian statistics is demonstrated. Bulk etch rates of MgO are predicted using a steady-state model with volume-averaged plasma parameters and classical Langmuir surface kinetics. Plasma particle and surface kinetics are modeled within a global plasma framework using single component Metropolis Hastings methods and limited data. The accuracy of these predictions is evaluated with synthetic and experimental etch rate data for magnesium oxide in an ICP-RIE system. This approach is compared and superior to factorial models generated from JMP, a software package frequently employed for recipe creation and optimization.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer.

This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Chemical mechanical polishing (CMP) has been a critical enabling technology in shallow trench isolation (STI), which is used in current integrated circuit fabrication process to accomplish device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This paper proposes characterization and modeling techniques to address a variety of concerns in STI CMP. In the past, majority of CMP publications have been addressed on interconnect layers in backend- of-line (BEOL) process. However, the number of CMP steps in front-end-of-line (FEOL) has been increasing in more advanced process techniques like 3D-FinFET and replacement metal gate, as a results incoming topography induced by FEOL CMP steps can no longer be ignored as the topography accumulates and stacks up across multiple CMP steps and eventually propagating to BEOL layers. In this paper, we first discuss how to characterize and model STI CMP process. Once STI CMP model is developed, it can be used for screening design and detect possible manufacturing weak spots. We also work with process engineering team to establish hotspot criteria in terms of oxide dishing and nitride loss.

As process technologies move from planar transistor to 3D transistor like FinFet and multi-gate, it is important to accurately predict topography in FEOL CMP processes. These incoming topographies when stacked up can have huge impact in BEOL copper processes, where copper pooling becomes catastrophic yield loss. A calibration methodology to characterize STI CMP step is developed as shown in Figure 1; moreover, this STI CMP model is validated from silicon data collected from product chips not used in calibration stage. Additionally, wafer experimental setup and metrology plan are instrumental to an accurate model with high predictive power.

After a model is generated, spec limits and threshold to establish hotspots criteria can be defined. Such definition requires working closely with foundry process engineering and integration team and reviewing past failure analysis (FA) to come up a reasonable metrics. Conventionally, a potential STI weak point can be found when nitride residues remains in the active region after nitride strip. Another source of STI hotspots occurs when nitride erosion is too much, and active region can suffer severe damage.

This paper presents an automated DFM solution to generate Bit Line Pattern Dummy (BLPD) for memory devices. Dummy shapes are aligned with memory functional bits to ensure uniform and reliable memory device. This paper will present a smarter approach that uses an analysis based technique for adding the dummy shapes that have different types according to the space available. Experimental results based on layout of Mobile dynamic random access memory (DRAM).

As technology development advances into deep-sub-wavelength nodes, multiple patterning is becoming more essential to achieve the technology shrink requirements. Recently, Optical Proximity Correction (OPC) technology has proposed simultaneous correction of multiple mask-patterns to enable multiple patterning awareness during OPC correction. This is essential to prevent inter-layer hot-spots during the final pattern transfer. In state-of-art literature, multi-layer awareness is achieved using simultaneous resist-contour simulations to predict and correct for hot-spots during mask generation. However, this approach assumes a uniform etch shrink response for all patterns independent of their proximity, which isn’t sufficient for the full prevention of inter-exposure hot-spot, for example different color space violations post etch or via coverage/enclosure post etch.

In this paper, we explain the need to include the etch component during multiple patterning OPC. We also introduce a novel approach for Etch-aware simultaneous Multiple-patterning OPC, where we calibrate and verify a lumped model that includes the combined resist and etch responses. Adding this extra simulation condition during OPC is suitable for full chip processing from a computation intensity point of view. Also, using this model during OPC to predict and correct inter-exposures hot-spots is similar to previously proposed multiple-patterning OPC, yet our proposed approach more accurately corrects post-etch defects too.

Traditional model-based Optical Proximity Correction (OPC) and rule-based Resolution Enhancement Technology (RET) methods have been the workhorse mask synthesis methods in volume production for logic and memory devices for more than 15 years. Rule-based OPC methods have been in standard use for over 20 years now. With continuous technical enhancements, these methods have proven themselves robust, flexible and fast enough to meet many of the technical needs of even the most advanced nodes. Inverse Lithography Technology (ILT) methods are well known to have strong benefits in finding flexible mask pattern solutions to improve process window for the most advanced design locations where traditional methods are not sufficient.

However, OPC/RET requirements at each node have changed radically in the last 20 years beyond just technical requirements. The volume of engineering work to be done has also skyrocketed. The number of device layers which need OPC/RET can be 10X higher than in earlier nodes. Additionally, the number of mask layers per device layer is often 2X or more times higher with multiple patterning. Finally, the number of features to correct per mask increases ~2X with each node. These factors led to a large increase in the number of OPC engineers needed to develop the complex new OPC/RET recipes for advanced nodes.

In this paper, we describe new developments which significantly improve the productivity of OPC engineers to deploy Rule Based OPC (RBOPC), Model Based OPC (MBOPC), AF, and ILT recipes in modern manufacturing flows. In addition to technical improvements such as novel multiple segment hotspot fixing solvers and ILT hot-spot fixing necessary to support correction needs, we have re-architected the entire flow based on how OPC engineers now develop and maintain OPC/RET recipes. The re-architecture of the flow takes advantages of more recent developments in modular and structured programming methods which are known to benefit ease engineering software development applications. Therefore, this improved OPC/RET development methodology includes specifically targeted advanced new technical functions; new types of modular structures for much faster reuse of customizations; and new interfaces to flexible programming capabilities to enable easier development and integration of deep customizations for the most challenging technical needs.

A hybrid multi-step method for Sub-Resolution Assist Feature (SRAF) placement is presented. The process window, characterized by process variation bands (PV-bands), is subjected to optimization. By applying a state-of-the-art advanced pattern matching based approach, the SRAF placement is optimized to maximize the process window. Due to the complexity of building a complete Rule-Based SRAF (RBSRAF) solution and the performance limitation of the Model-Based SRAF solution (MBSRAF), the hybrid pattern based SRAF reduces the complexity and improves performance. In this paper, the hybrid pattern-based SRAF algorithm and its implementation, as well as testing results, are discussed with respect to process window and performance.

As device design rule has been made pattern size shrink, LELE (Litho-Etch- Litho-Etch) process is used in advance pattern process more and more. The CD control is one of the most critical factors for semiconductor manufacturing. However, the numbers of current in-line measurement points are not sufficient for the whole wafer CD monitoring. It’s the goal to increase inline monitor capacity without suffering process cycle time. To generate an innovation pattern to reach the goal is the purpose for the advance pattern process.

This paper is going to introduce the detection of CD variation by using overlay metrology in LELE process. The target mark was designed from AIM (Advanced Imaging Metrology) overlay mark. By placing Layer 1 and Layer 2 AIM pattern side by side, CD variation will cause related position changed. And it is able to be detected by overlay tool. On the other hand, overlay shift will not influence this model. It has an advantage over the conventional CD measurement tool. First, the overlay tool throughput is 5~10 times faster than traditional CDSEM and the measurement time is saved. Second, we are able to measure CD and overlay at the same time. Both CD/AA performances are considered and the throughput is also gained.