This PDF file contains the front matter associated with SPIE Proceedings Volume 9428, including the Title Page, Copyright information, Table of Contents, Authors, Introduction (if any), and Conference Committee listing.

Recent trend in CMOS technology showed migration towards new device structures. In order to reduce leakage at very small dimension, FINFET has been incorporated into the roadmap. This introduces new challenges on etch patterning due to topography. FINFET gate etch and spacer etch are two of the most challenging steps. For gate last flow, the dummy gate etch is very similar to planar polysilicon gate etch. Selectivity > 1:100 can be easily achieved between polysilicon and silicon dioxide. However, for gate first flow, the gate stack consists of a-Si/TiN/HfO₂ on FINFET topography, which makes gate etch very challenging. Significant over etch is needed to clear the gate materials from FIN side wall, so very high selectivity is needed between multiple etch materials. Nanowire represents the next evolution from FINFET where the gate now surrounds the channel. To overcome the etch challenges, one structure has been demonstrated utilizing a non conventional gate etch process to remove the gate material from under the nanowire [3]. New materials are also being proposed to replace silicon such as SiGe [5] and III-V [6]. For both materials, high selectivity and low damage gate etch and spacer etch are required. For III-V InGaAs MOSFET, the material is even more prone to damage than SiGe. EarlyMOSFET work has always relied on low damage gate definition such as wet etch or lift-off. We have demonstrated that similar performance can be achieved with anisotropic low damage RIE gate etch.

In the HARC etching to form capacitor in DRAM fabrication, many essential requirements such as CD uniformity, vertical profile, process margin and etc. should be satisfied. The CD uniformity not only of the contact hole but also of the space between adjacent contact holes determines the distribution of the cell capacitance and leakage characteristics. The CD uniformity is mainly determined by the mask etching. Recently, it was found that the CD uniformity of the space between contact holes becomes worse along with the design rule shrinkage. And the worse CD uniformity comes from the tilted profile of the hard mask. Obtaining vertical contact profile is a traditional problem in HARC etching. To achieve large enough bottom CD fundamentally erodes side surface of the upper part of the contact and thus forms so called bowed profile. Serious bowed profile decreases the minimum space between adjacent contact holes and induces electrical leakage. In this paper, these issues and related challenges will be presented. And various approaches to understand the mechanism of the issues and to resolve them will be touched.

Line pattern collapse attracts attention as a new problem of the L&S formation in sub-20nm H.P feature. Line pattern collapse that occurs in a slight non-uniformity of adjacent CD (Critical dimension) space using double patterning process has been studied with focus on micro-loading effect in Si etching. Bias RF pulsing plasma etching process using low duty cycle helped increase of selectivity Si to SiO₂. In addition to the effect of Bias RF pulsing process, the thin mask obtained from improvement of selectivity has greatly suppressed micro-loading in Si etching. However it was found that micro-loading effect worsen again in sub-20nm space width. It has been confirmed that by using cycle etch process to remove deposition with CFx based etching micro-loading effect could be suppressed. Finally, Si etching process condition using combination of results above could provide finer line and space without "line pattern collapse" in sub-20nm.

Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.

As feature critical dimension (CD) shrinks towards and beyond the 7nm node, patterning techniques for optical lithography with double and triple exposure will be replaced by EUV patterning. EUV enables process and overlay improvement, as well as a potential cost reduction due to fewer wafer passes and masks required for patterning. However, the EUV lithography technique introduces newer types of resists that are thinner and softer compared to conventional 193nm resists currently being used. The main challenge is to find the key etch process parameters to improve the EUV resist selectivity, reduce LER and LWR, minimize line end shrink, improve tip-to-tip degradation, and avoid line wiggling while still enabling previous schemes such as trench-first-metal-hard-mask (TFMHM), self-aligned via (SAV) and self-aligned contact (SAC).

In this paper, we will discuss some of the approaches that we have investigated to define the best etch process adjustments to enable EUV patterning. RF pulsing is one of the key parameters utilized to overcome most of the previously described challenges, and has also been coupled with stack optimization. This study will focus on RF pulsing (high vs. low frequency results) and bias control (RF frequency dependence). In particular, pulsing effects on resist morphology, selectivity and profile management will be reported, as well as the role of aspect ratio and etch chemistry on organic mask wiggling and collapse.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

We report a 20 nm half-pitch self-aligned double patterning (SADPP) process based on a resist-core approach. Line/space 20/20 nm features in silicon are successfully obtained with CD_variation, LWR and LER of 0.7 nm, 2.4 nm and 2.3 nm respectively. The LWR and LER are characterized at each technological step of the process using a power spectral density fitting method, which allows a spectral analysis of the roughness and the determination of unbiased roughness values. Although the SADP concept generates two asymmetric populations of lines, the final LLWR and LER are similar. We show that this SADP process allows to decrease significantly the LWR and the LER of about 62% and 48% compared to the initial photoresist patterns. This study also demonstrates that SADP is a very powerful concept to decrease CD uniformity and LWR especially in its low-frequency components to reach sub-20 nm node requirements. However, LER low-frequency components are still high and remain a key issue tot address for an optimized integration.

Optical lithography has given the semiconductor industry the chance to follow Moore’s law in scaling the transistor dimensions and consequently stacking them in a more dense way. However, for present sub 20 nm nanoscale patterns, which are reaching molecular dimensions; controlling the line edge and width roughness (LER/LWR) has become a key challenge. One way of reducing the roughness at photoresist level is the exposure of the organic substrate to a hydrogen plasma process in a post lithography step. Unfortunately, to this day, no clear understanding of the interaction of various plasma parameters with EUV resist substrates has been reported. In this work, two EUV resist platforms were exposed to an H₂ plasma environment and H₂ energetic neutrals only, by using a customized plasma reactor. The surface and bulk modifications of the photoresists have been evaluated by spectroscopic ellipsometry, Fourier transformed infrared spectroscopy and atomic force microscopy.

Directed Self-Assembly (DSA) of Block Copolymers (BCP) is one of the most promising solutions for sub-10 nm nodes. However, some challenges need to be addressed for a complete adoption of DSA in manufacturing such as achieving DSA-friendly design, low defectivity and accurate pattern placement. In this paper, we propose to discuss the DSA integration flows using graphoepitaxy for contact-hole patterning application. DSA process dependence on guiding pattern density has been studied and solved thanks to a new approach called “DSA planarization”. The capabilities of this new approach have been evaluated in terms of defectivity, Critical Dimension (CD) control and uniformity before and after DSA etching transfer.

Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.

In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming / reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER) / Line Width Roughness (LWR); critical dimension uniformity (CDU); and profile in 3-dimensions for the resist trim / reformation etch is extremely aggressive.

In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.

One of most promising technique for the extension of 193nm immersion lithography must be Self-Aligned Multiple Patterning (SAMP) at the present. We have studied this SAMP in several aspects, which are scaling capability, mitigation of process complexity, pattern fidelity, affordability and so on. On the other hand, Gridded Design Rule (GDR) concept with Single directional layout (1D layout) extended the down-scaling with 193-immersion furthermore and relieve the process variation and process complexity, represented in Optical proximity effect (OPE), by simplification of layout design. In 1D layout fabrication, Key process steps might be edge placement control on grating line and controllability of hole-shrink technique for line-cutting. This paper introduces current demonstration results on pattern transfer fidelity control and hole-shrink technique as combined with unique pattern shape repair approach.

For more than five decades, the semiconductor industry has overcome technology challenges with innovative ideas that have continued to enable Moore’s Law. It is clear that multi-patterning lithography is vital for 20nm half pitch using 193i. Multi-patterning exposure sequences and pattern multiplication processes can create complicated tolerance accounting due to the variability associated with the component processes. It is essential to ensure good predictive accuracy of compact etch models used in multipatterning simulation. New modelforms have been developed to account for etch bias behavior at 20 nm and below. The new modeling components show good results in terms of global fitness and some improved predication capability for specific features. We’ve also investigated a new methodology to make the etch model aware of 3D resist profiles.

The performance of novel molecular glass resists is demonstrated in this work for the purposes of performing nano-pattern transfer. In order to improve the etch durability, post apply bake (PAB) and mixing two resists platforms were investigated. These resists showed a promising etch durability for efficient pattern transfer with films as thin as 5 nm. Etch rate, surface roughness, evolution of the refractive index of these materials are presented to establish a good baseline and select appropriate candidate materials for patterning beyond-CMOS.

A neutral beam etching process has been developed that achieves damage- free (chemically and physically) etching. Recently, it was found that transition metals could be etched using neutral beam etching through metallic complex reactions. In this process, a neutral beam is extracted from a plasma generation region into a reaction chamber. Complex reactant gases are injected into a reaction chamber which is screened from the plasma during neutral beam etching. In this paper, etching of Pt and CoFeB, candidate materials for MRAM structures by a neutral beam system is described. It was found that etch rate enhancement of Pt/CoFeB surfaces resulted from their exposure to a neutral beam from Ar/O₂ plasma with simultaneous injection of EtOH /acetic acid into the reaction chamber. Etching damage was also evaluated and no magnetic hysteresis degradation has been observed. Neutral beam etching technology has the capability to make breakthrough for fabricating MRAM device.

With shrinking critical dimensions, minimizing each of aspect ratio dependent etching (ARDE), bowing, undercut, selectivity, and within die uniformly across a wafer is met by trading off one requirement against another. The problem of trade-offs is especially critical. At the root of the problem is that roles radical flux, ion flux and ion energy play may be both good and bad. Increasing one parameter helps meeting one requirement but hinders meeting the other. Managing process by managing flux ratios and ion energy alone with conventional sources is not adequate because surface chemistry is uncontrollable. At the root of lack of control is that the electron energy distribution function (eedf) has not been controlled. Fortunately the high density surface wave sources control the eedf by fiat. High density surface wave sources are characterized by distinct plasma regions: an active plasma generation region with high electron temperature (T_e) and an ionization free but chemistry rich diffusive region (low T_e region). Pressure aids is segregating the regions by proving a means for momentum relaxation between the source and downstream region. “Spatial pulsing” allows access to plasma chemistry with reasonably high ion flux, from the active plasma generation region, just above the wafer. Low plasma potential enables precise passivation of surfaces which is critical for atomic layer etch (ALE) or high precision etch where the roles of plasma species can be limited to their purposed roles. High precision etch need not be at the cost of speed and manufacturability. Large ion flux at precisely controlled ion energy with RLSATM realizes fast desorption steps for ALE without compromising process throughput and precision.

Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the “coordinated line epitaxy (COOL) process,” using grapho- and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.

We report a facile route to form densely packed graphene nanoribbon (GNR) arrays via graphoepitaxial assembly of symmetric P(S-b-MMA). Since guiding channels for graphoepitaxy are the source and drain electrodes in field effect transistor (FET) geometry, we avoid laborious nanopatterning and FET device fabrication processes. By grafting a random copolymer brush on the graphene FET device, perpendicular lamellar domains are aligned normal to the electrode direction, resulting in line arrays connecting the two electrodes. Through optimization of the reactive ion etching conditions, the vertically oriented lamellar domains were transferred to the underlying graphene, leading to GNR arrays that act as conducting channels. This is a simple and efficient fabrication process using the fundamental concepts developed for the graphoepitaxial assembly of symmetric BCPs to create densely packed sub- 20 nm GNR arrays, compared to conventional fabrication process.

Electron beam writing remains one of the reference pattern generation techniques, and plasma etching continues to underpin pattern transfer. We report a systematic study of the plasma etch resistance of several e-beam resists, both negative and positive as well as classical and Chemically Amplified Resists: HSQ^[1,2] (Dow Corning), PMMA^[3] (Allresist GmbH), AR-P6200 (Allresist GmbH), ZEP520 (Zeon Corporation), CAN028 (TOK), CAP164 (TOK), and an additional pCAR (non-disclosed provider). Their behaviour under plasma exposure to various nano-scale plasma etch chemistries was examined (SF₆/C₄F₈ ICP silicon etch, CHF₃/Ar RIE SiO₂ etch, Cl₂/O₂ RIE and ICP chrome etch, and HBr ICP silicon etch). Samples of each resist type were etched simultaneously to provide a direct comparison of their etch resistance. Resist thicknesses (and hence resist erosion rates) were measured by spectroscopic ellipsometer in order to provide the highest accuracy for the resist comparison. Etch selectivities (substrate:mask etch rate ratio) are given, with recommendations for the optimum resist choice for each type of etch chemistry. Silicon etch profiles are also presented, along with the exposure and etch conditions to obtain the most vertical nano-scale pattern transfer. We identify one resist that gave an unusually high selectivity for chlorinated and brominated etches which could enable pattern transfer below 10nm without an additional hard mask. In this case the resist itself acts as a hard mask. We also highlight the differing effects of fluorine and bromine-based Silicon etch chemistries on resist profile evolution and hence etch fidelity.

It is clear today that further scaling towards smaller dimensions and pitches requires a multitude of additional process steps. Within this work we look for solutions to achieve a middle of line 193i based patterning scheme for N7 logic at a contacted poly pitch of 40-45 nm. At these pitches, trenches can still be printed by means of double patterning. However, they need to be blocked at certain positions because of a limited line end control below 90 nm pitch single print. Based on the 193i patterning abilities, the proposed SRAM (Static Random Access Memory) cell requires 5 blocking layers. Integrating 5 blocking layers is a new challenge since down to N10 one blocking layer was usually sufficient. The difficulty with multiple blocking layers is the removal of the masked parts, especially in cases of overlap. As a solution a novel patterning approach is proposed and tried out on relaxed dimensions (patent pending). The proposed solution is expected not to be sensitive to the number of blocking layers used, and tolerates their overlap. The stack is constructed to be compatible with N7 substrates such as SiGe or P:Si. Experimental results of the stack blocking performance on relaxed pitch will be presented and discussed.

When CMOS technology reaches 28/20nm node and beyond, several new schemes are implemented such as High K metal gate (HKMG) which can enhance the device performance and has better control of device current leakage. Dummy poly gate removal (DPGR) process is introduced for HKMG, and works as a key process to control the work function of metal gate and threshold voltage (Vt) shift. In dry etch technology, conventional continuous wave (CW) plasma process has been widely used, however, it may not be capable for some challenging process in 28nm node and beyond. In DPGR process for HKMG scheme, CW scheme may result in plasma damage of gate oxide/capping layer for its inherent high electron temperature (Te) and ion energy while synchronous pulsing scheme is capable to simultaneously pulse both source and bias power, which could achieve lower Te, independent control of ion and radical flux, well control the loading of polymer deposition on dense/ isolate features. It’s the first attempt to utilize synchronous pulsing plasma in DPGR process. Experiment results indicate that synchronous pulsing could provide less silicon recess under thin gate oxide which is induced by the plasma oxidation. Furthermore, the loading of HK capping layer loss between long channel and short channel can be well controlled which plays a key role on transistor performance, such as leakage and threshold voltage shift. Additionally, it has been found that synchronous pulsing could distinctly improve ILD loss when compared with CW, which is helpful to broaden the whole process window.

Based on semiconductor process conditions such as power, gas, temperature and pressure, proper elastomer seal material selection is vital to maximizing the performance and productivity of wafer process production systems. Numerous metrology and test methods are used to measure the combined performance of elastomer seals. It is extremely important to take into consideration several performance parameters because minute shifts or modifications to process conditions can have detrimental effects on the production process. Weight loss, FTIR, SEM, Laser Confocal Microscope, and ICP/MS are some of the test methods used by Greene, Tweed to predict, with high confidence, the performance of elastomer seals for specific process conditions. This methodology is used to support the semiconductor research and process development community.