This volume is undergoing review. This PDF file contains the front matter associated with SPIE Proceedings Volume 9782, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

Si FinFET scaling is getting more difficult due to extremely narrow fin width control and power dissipation. Nanowire FETs and high mobility channel are attractive options for CMOS scaling. Nanowire FETs can maintain good electrostatics with relaxed nanowire diameter. High mobility channel can provide good performance at low power operation. However their fin patterning is challenging due to fins consisted of different materials or fragile high mobility material. Controlled etch and strip are necessary for good fin cd and profile control. Fin height increase is a general trend of scaled FinFETs and nanowire FETs, which makes patterning difficult not only in fin, but also in gate, spacer and replacement metal gate. It is important that gate and spacer etch have high selectivity to fins and good cd and profile control even with high aspect ratio of fin and gate. Work function metal gate patterning in scaled replacement metal gate module needs controlled isotropic etch without damaging gate dielectric. SF6 based etch provides sharp N-P boundary and improved gate reliability.

EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.

Ar/Cl₂/CH₄ gas mixture has been investigated for the development of plasma etching process dedicated to the patterning of 3μm-deep InP structures integrated on 200mm SiO₂ carrier wafer. The plasma process requirements are: high InP etch rates (>500nm.min^-1), high InP/SiO₂ selectivity (<40), anisotropic profiles and smooth bottom and sidewalls surfaces. The process development mainly focuses on the impact of the gas ratio and gas flow on the etch rates, selectivity, pattern profile and surface roughness. It is demonstrated that the CH4 flow drives the process performance and that by adjusting it properly, a narrow process window provides acceptable selectivity of 25, anisotropic profiles and smooth surface. The difficulty of the process development using Ar/Cl₂/CH₄ gas mixture is to combine high InP/SiO₂ selectivity and anisotropic profiles since to passivate efficiently the InP sidewalls and prevent from lateral etching, it seems that a SiOC like deposition is needed, which is only possible if the SiO₂ wafer is etched.

Optical metrology is the workhorse metrology in manufacturing and key enabler to patterning process control. Recent advances in device architecture are gradually shifting the need for process control from the lithography module to other patterning processes (etch, trim, clean, LER/LWR treatments, etc..). Complex multi-patterning integration solutions, where the final pattern is the result of multiple process steps require a step-by-step holistic process control and a uniformly accurate holistic metrology solution for pattern transfer for the entire module. For effective process control, more process “knobs” are needed, and a tighter integration of metrology with process architecture.

Multiple patterning integrations for sub 193nm lithographic resolution are becoming increasingly creative in pursuit of cost reduction and achieving desired critical dimension. Implementing these schemes into production can be a challenge. Aimed at reducing cost associated with multiple patterning for the 10nm node and beyond, we will present a self-aligned quadruple patterning strategy which uses 193nm immersion lithography resist pattern as a first mandrel and a spacer on spacer integration to enable a final pitch of 30nm. This option could be implemented for front end or back end critical layers such as Fin and Mx. Investigation of combinations of low temperature ALD films such as TiO, Al2O3 and SiO2 will be reviewed to determine the best candidates to meet the required selectivities, LER/LWR and CDs.

For sub-10nm technologies, the semiconductor industry is facing the limits of conventional lithography to achieve narrow dimensions. DSA (Directed Self-Assembly) of Block Copolymers (BCP) is one of the most promising solutions to reach sub-10nm patterns with a high density. One challenge for DSA integration is the removal of PMMA selectively to PS. In this paper, we propose to study PMMA removal selectively to PS by screening different plasma etch chemistries. These chemistries developed on blanket wafers have been tested on cylindrical and lamellar patterned wafers.

The need for continued device scaling along with the increasing demand for high precision have lead to the development of atomic layer etch processes in semiconductor manufacturing. We have tested this new methodology with regard to patterning applications. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. While PE-ALE approaches seem to have limited success for trilayer patterning applications, significant improvements were obtained when applying them to small pitch. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

Self-Aligned Quadruple Patterning (SAQP) is targeted to support the sub 10nm technology nodes. It is consisted of several process steps starting with lithography and Etch to define the pattern backbone. Followed by additional set of processes based on thin-films deposition and etch that quadruple the number of patterns, shrinking pattern and pitch sizes.

Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield.

In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.

Sub-nm precision is increasingly being required of many critical plasma etching processes in the semiconductor industry. Accurate control over ion energy and ion/radical composition is needed during plasma processing to meet these stringent requirements. Described in this work is a new plasma etch system which has been designed with the requirements of atomic precision plasma processing in mind. In this system, an electron sheet beam parallel to the substrate surface produces a plasma with an order of magnitude lower electron temperature T_e (~ 0.3 eV) and ion energy E_i (< 3 eV without applied bias) compared to conventional radio-frequency (RF) plasma technologies. Electron beam plasmas are characterized by higher ion-to-radical fraction compared to RF plasmas, so a separate radical source is used to provide accurate control over relative ion and radical concentrations. Another important element in this plasma system is low frequency RF bias capability which allows control of ion energy in the 2-50 eV range. Presented in this work are the results of etching of a variety of materials and structures performed in this system. In addition to high selectivity and low controllable etch rate, an important requirement of atomic precision etch processes is no (or minimal) damage to the remaining material surface. It has traditionally not been possible to avoid damage in RF plasma processing systems, even during atomic layer etch. The experiments for Si etch in Cl₂ based plasmas in the aforementioned etch system show that damage can be minimized if the ion energy is kept below 10 eV. Layer-by-layer etch of Si is also demonstrated in this etch system using electrical and gas pulsing.

The directed self-assembly (DSA) of block copolymers offers a promising route for scaling feature sizes below 20 nm. At these small dimensions, plasmas are often used to define the initial patterns. It is imperative to understand how plasmas interact with each block in order to design processes with sufficient etch contrast and pattern fidelity. Symmetric lamella forming block copolymers including, polystyrene-b-poly(methyl methacrylate) and several high-χ silicon-containing and tin-containing block copolymers were synthesized, along with homopolymers of each block, and exposed to various oxidizing, reducing, and fluorine-based plasma processes. Etch rate kinetics were measured, and plasma modifications of the materials were characterized using XPS, AES, and FTIR. Mechanisms for achieving etch contrast were elucidated and were highly dependent on the block copolymer architecture. For several of the polymers, plasma photoemissions were observed to play an important role in modifying the materials and forming etch-resistant protective layers. Furthermore, it was observed for the silicon- and tin-containing polymers that an initial transient state exists, where the polymers exhibit an enhanced etch rate, prior to the formation of the etch-resistant protective layer. Plasma developed patterns were demonstrated for the differing block copolymer materials with feature sizes ranging from 20 nm down to approximately 5 nm.

In the Global 450mm Equipment Development Consortium (G450C), a 193i guided directed self-assembly (DSA) pattern has been used to create structures at the 14nm node and below. The first guided DSA patterned wafer was ready for etch process development within a month of the G450C’s first 193i patterned wafer availability with one litho pass. Etch processes were scaled up from 300mm to 450mm for a 28nm pitch STI stack and a 40nm pitch M1 BEOL stack. The effects of various process parameters were investigated to fine tune each process. Overall process window has been checked and compared. Excellent process stability results were shown for current etch chambers.

For the first time, process impact on line-edge roughness (LER) and line-width roughness (LWR) in a back-end-of-line (BEOL) self-aligned quadruple patterning (SAQP) flow has been systematically investigated through predictive 3D virtual fabrication. This frequency dependent LER study shows that both deposition and etching effectively reduce high frequency LER, while deposition is much more effective in reducing low frequency LER. Spacer-assisted patterning technology reduces LWR significantly by creating correlated edges, and further LWR improvement can be achieved by optimizing individual process effects on LER. Our study provides a guideline for the understanding and optimization of LER and LWR in advanced technology nodes.

Accurate prediction of etch bias has become more important as technology node shrinks. A simulation is not feasible solution in full chip level due to excessive runtime, so etch proximity correction (EPC) often relies on empirically obtained rules or models. However, simple rules alone cannot accurately correct various pattern shapes, and a few empirical parameters in model-based EPC is still not enough to achieve satisfactory OCV. We propose a new approach of etch bias modeling through machine learning (ML) technique. A segment of interest (and its surroundings) are characterized by some geometric and optical parameters, which are received by an artificial neural network (ANN), which then outputs predicted etch bias of the segment. The ANN is used as our etch bias model for new EPC, which we propose in this paper. The new etch bias model and EPC are implemented in commercial OPC tool and demonstrated using 20nm technology DRAM gate layer.

Directed self-assembly is a candidate process for sub-15-nm patterning applications. It will be necessary to develop the DSA process fully and consider process integration to adapt the DSA process for use in semiconductor manufacturing. We investigated the reactive ion etching (RIE) process for the fabrication of sub-10-nm metal wires using the DSA process and the process integration requirements for electrical yield verification. We evaluated the process using an organic high-chi block copolymer (BCP) with a lamellar structure. One critical issue during DSA pattern transfer involves the BCP bottom connection. The BCP bottom connections could be removed without BCP mask loss by using the optimum bias power and the optimum BCP film thickness. The sub-10-nm DSA line-and-space (L/S) patterns were successfully transferred to a SiO₂ layer with sufficient film thickness for the fabrication of the metal wire. We also evaluated the overlay technique used in the process. The connect patterns and cut patterns were overlaid on 10-nm trenches fabricated by the DSA process.

Critical back end of line (BEOL) Mx patterning at 7nm technology node and beyond requires sub-36nm pitch line/space pattern in order to meet the scaling requirements. This small pitch can be achieved by either extreme ultraviolet (EUV) lithography or 193nm-immersion-lithography based self-aligned quadruple patterning (SAQP). With enormous challenges being faced in production readiness of EUV lithography, SAQP is expected to be the front up approach for Mx grid patterning for most of industry. In contrast to the front end of line (FEOL) fin patterning, which has successfully deployed SAQP approach since 10nm node technology, BEOL Mx SAQP is challenging owing to the required usage of significantly lower temperature budgets for film stack deposition. This has an adverse impact on the material properties of the as-deposited films leading to emergence of several challenges for etch including selectivity, uniformity and roughness. In this presentation we will highlight those unique etch challenges associated with our BEOL Mx SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries & process steps for meeting the 7nm technology node targets. We will present comparison data on both organic and in-organic mandrel stacks with respect to LER/LWR & CDU. With LER being one of the most critical targets for 7nm BEOL Mx, we will outline our actions for optimization of our stack including resist material, mandrel material, spacer material and others. Finally, we would like to update our progress on achieving the target LER of 1.5 nm for 32nm pitch BEOL SAQP pattern.