Evaluation Of Multilayer Resists For Submicron Technology

Christoph Nolscher; Gunter Czech; Jurgen Karl; Klaus Koller

doi:10.1117/12.968345

1 January 1988 Evaluation Of Multilayer Resists For Submicron Technology

Christoph Nolscher, Gunter Czech, Jurgen Karl, Klaus Koller

Proceedings Volume 0920, Advances in Resist Technology and Processing V; (1988) https://doi.org/10.1117/12.968345
Event: Santa Clara Symposium on Microlithography, 1988, Santa Clara, CA, United States

Abstract

PCM-, trilevel-RIE- and singlelevel-RIE-resist systems are investigated for application in submicron technology. Simulation results of the PCM-technique are compared with experimental results using the K809/PMMA system. Gate and sub-micron contact hole etch results are presented for the Shipley PCM system using PMGI as the planarizing layer. For the trilevel technique using SOG or a-Si as intermediate layer, the loss of linewidth during bottom resist 02-RIE was of main interest. Finally, a dry developing technique, the DESIRE process using the PLASMASK resist, was studied and tested on device wafers.

Citation Download Citation

Christoph Nolscher, Gunter Czech, Jurgen Karl, and Klaus Koller "Evaluation Of Multilayer Resists For Submicron Technology", Proc. SPIE 0920, Advances in Resist Technology and Processing V, (1 January 1988); https://doi.org/10.1117/12.968345

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available