Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic

L. Liebmann; G. Northrop; M. Facchini; L. Riviere Cazaux; Z. Baum; N. Nakamoto; K. Sun; D. Chanemougame; G. Han; V. Gerousis

doi:10.1117/12.2297634

20 March 2018 Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic

L. Liebmann, G. Northrop, M. Facchini, L. Riviere Cazaux, Z. Baum, N. Nakamoto, K. Sun, D. Chanemougame, G. Han, V. Gerousis

Author Affiliations +

Proceedings Volume 10588, Design-Process-Technology Co-optimization for Manufacturability XII; 1058808 (2018) https://doi.org/10.1117/12.2297634
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

This paper describes a rigorous yet flexible standard cell place-and-route flow that is used to quantify block-level power, performance, and area trade-offs driven by two unique cell architectures and their associated design rule differences. The two architectures examined in this paper differ primarily in their use of different power-distribution-networks to achieve the desired circuit performance for high-performance logic designs. The paper shows the importance of incorporating block-level routability experiments in the early phases of design-technology co-optimization by reviewing a series of routing trials that explore different aspects of the technology definition. Since the electrical and physical parameters leading to critical process assumptions and design rules are unique to specific integration schemes and design objectives, it is understood that the goal of this work is not to promote one cell-architecture over another, but rather to convey the importance of exploring critical trade-offs long before the process details of the technology node are finalized to a point where a process design kit can be published.

Citation Download Citation

L. Liebmann, G. Northrop, M. Facchini, L. Riviere Cazaux, Z. Baum, N. Nakamoto, K. Sun, D. Chanemougame, G. Han, and V. Gerousis "Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058808 (20 March 2018); https://doi.org/10.1117/12.2297634

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