Nanosheet metrology opportunities for technology readiness

Mary A. Breton; Daniel Schmidt; Andrew Greene; Julien Frougier; Curtis Durfee; Indira Seshadri; Jennifer Church; Veeraraghavan Basker; Nelson Felix

doi:10.1117/12.2583636

22 February 2021 Nanosheet metrology opportunities for technology readiness

Mary A. Breton, Daniel Schmidt, Andrew Greene, Julien Frougier, Curtis Durfee, Indira Seshadri, Jennifer Church, Veeraraghavan Basker, Nelson Felix

Author Affiliations +

Proceedings Volume 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV; 116111R (2021) https://doi.org/10.1117/12.2583636
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of GAA devices requires new specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology continues through research and development cycles and looks to transition to manufacturing, there are many opportunities and challenges remaining for inline metrology. Especially valuable are measurement techniques which are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact to the frequency of cycles of learning. More than previous nodes, then, this node may be when some of these offline techniques jump from the lab to the fab, as certain critical measurements need to be monitored realtime. Thanks to the compute revolution this very industry enabled, machine learning has begun to permeate inline disposition, and hybrid metrology systems continue to advance. Metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness (LER), pitchwalk, and defectivity continue to be managed. This paper reviews related prior studies and advocates for future metrology development that ensures nanosheet technology has the inline data necessary for success.

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Citation Download Citation

Mary A. Breton, Daniel Schmidt, Andrew Greene, Julien Frougier, Curtis Durfee, Indira Seshadri, Jennifer Church, Veeraraghavan Basker, and Nelson Felix "Nanosheet metrology opportunities for technology readiness", Proc. SPIE 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV, 116111R (22 February 2021); https://doi.org/10.1117/12.2583636

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KEYWORDS

Metrology

Gallium arsenide

Line edge roughness

Logic

Machine learning

Manufacturing

Nanotechnology

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