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As an advanced form of optical proximity correction (OPC), Inverse Lithography Technology (ILT) calculates the desired shapes on a photomask in free-form curvilinear types. It has become one of the key computational lithography solutions for advanced technology nodes, which may enable the most challenging features in IC designs and produce mask output that results in better process latitude and CD control on wafer than the one using conventional OPC [1]. Although curvilinear ILT technology has taken root in limited cases such as in hot spot repairment and in memory [2], it still experiences difficulties to be adopted as a full-chip solution due to its long computation time and consistency issues. In this paper, we will leverage Siemens pxOPC and introduce a fast full-chip curvilinear ILT mask generation flow with Mentor Graphics Calibre SONR, a Machine Learning (ML) method [3]. Siemens pxOPC TM is pixel-based optimization product designed to maximize lithography quality in terms of EPE, Common Process Window, ILS/NILS, MEEF, etc. It uses image gradient to indicate the mask movement and minimize the gradient magnitude to achieve the final mask. Calibre SONR is a product built upon Mentor’s Machine Learning Platform (MLP) combining multiple related applications under one license. It uses feature vectors which are shown to correlate well with design and fab printing behavior. SONR implements fuzzy Pattern Matching (PM) in feature vector space, which is different from traditional PM (either exact or fuzzy) in topological space. For the case of pattern reduction, traditional fuzzy PM selects patterns which are close geometrically to a reference pattern, while SONR make further pattern reduction without loss in pattern coverage since different topological patterns may share similar feature vectors. In this paper, we build a flow to use SONR to analyze patterns across the full chip and make corresponding selections for the final pxOPC solutions. With comparable wafer performance, our preliminary results show that the flow may exceed the existing best practice in terms of runtime reduction, enhanced full-chip consistency, and robust full-chip run. Figure 1 shows that the run time is improved by 60%. This paper is organized as follows. pxOPC is introduced in Section I. Our proposed SONR pattern reduction flow is described in Section II, followed by the fast full-chip curvilinear mask generation flow in Section III. Then Section IV provides simulation results and discussion in Section IV. Section V conclusions the paper. Keyword: Curvilinear, ILT, pxOPC, mask, machine learning, pattern selection, layout reduction REFERENCES [1] Le Hong, Fan Jiang, Alexander Tritchkov, James Word, Dan Zhang, “Inverse Lithography Recipe Optimization Using Genetic Algorithm”, SPIE 105871H (2018). [2] Linyong (Leo) Pang, P. Jeffrey Ungar, Ali Bouaricha , Lu Sha, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Ryan Pearman, and Aki Fujimura "TrueMask ILT MWCO: full-chip curvilinear ILT in a day and full mask multi-beam and VSB writing in 12 hrs for 193i", Proc. SPIE 11327, Optical Microlithography XXXIII, 113270K (31 March 2020) [3] Yuansheng Ma, Le Hong, James Word, Fan Jiang, Vlad Liubich, Liang Cao, Srividya Jayaram, Doohwan Kwak, YoungChang Kim, Germain Fenger, Ananthan Raghunathan, Joerg Mellmann, “Reduction of Systematic Defects through Machine Learning from Design to Fab “, SPIE 11329-9 (2020)
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