Poster + Paper
26 May 2022 Process optimization by virtual target design in overlay metrology
Xiaolei Liu, Yoav Grauer, Raviv Yohanan, Mark Ghinovker, Diana Shaphirov, Iwata Yasuhisa, Imura Koichi, Ito Kosuke, Xindong Gao
Author Affiliations +
Conference Poster
Abstract
In modern DRAM processes, there are some critical layers that are particularly challenging for overlay (OVL) control. The conventional method of metrology target design for these challenging layers is to verify target performance using simulation based on the specific, final device process. After full simulations, target measurability issues can be encountered where the limited, available solutions (open hard mask, create topography, etc.) are costly and high risk. However, in DRAM new product R&D, there is always some tolerance for process tuning. The use of virtual Archer™ OVL measurements in metrology target design (MTD) can simulate metrology performance for these potential process splits, helping to find a good balance between process options and metrology performance. A significant improvement in target contrast for imaging-based overlay (IBO) is demonstrated by simulation on one of these challenging layers after process optimization as compared to the baseline (BSL) process. In this paper we will present the virtual MTD detailed flow and design considerations to achieve an optimized process and target design. The contrast of a key performance indicator (KPI) is improved by more than 30%, enabling OVL measurability of the challenging layer in new processes.
© (2022) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Xiaolei Liu, Yoav Grauer, Raviv Yohanan, Mark Ghinovker, Diana Shaphirov, Iwata Yasuhisa, Imura Koichi, Ito Kosuke, and Xindong Gao "Process optimization by virtual target design in overlay metrology", Proc. SPIE 12053, Metrology, Inspection, and Process Control XXXVI, 1205322 (26 May 2022); https://doi.org/10.1117/12.2614129
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KEYWORDS
Metrology

Overlay metrology

Semiconducting wafers

Tolerancing

Calibration

Device simulation

Photomasks

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