Optimization of a three-bit absolute value detector with domino logic and gate sizing

Kunlun Li; Junxiang Ma; Yixuan Zhang

doi:10.1117/12.2627237

14 February 2022 Optimization of a three-bit absolute value detector with domino logic and gate sizing

Kunlun Li, Junxiang Ma, Yixuan Zhang

Proceedings Volume 12161, 4th International Conference on Informatics Engineering & Information Science (ICIEIS2021); 121611A (2022) https://doi.org/10.1117/12.2627237
Event: 4th International Conference on Informatics Engineering and Information Science, 2021, Tianjin, China

Abstract

Microchips are widely used in a series of electronic products, such as integrated circuits, consumer electronics, industrial power supplies, household appliances and many other fields. To achieve the function of detecting and conversing electrical signals, it is of significance to design an absolute value detector. Compared with dynamic digital circuits, traditional analog circuits have the poor signal capability, along with large transmission delay and huge power consumption. Therefore, the content of this research is to modify a complementary metal-oxide semiconductor (CMOS) absolute value detector circuit by transforming it to a domino circuit and gate sizing. To verify the feasibility of the circuit, this research compares the performance of the modified circuit with the traditional circuit in terms of delay and energy, with methods mainly focusing on simulation and theoretical calculation.

Citation Download Citation

Kunlun Li, Junxiang Ma, and Yixuan Zhang "Optimization of a three-bit absolute value detector with domino logic and gate sizing", Proc. SPIE 12161, 4th International Conference on Informatics Engineering & Information Science (ICIEIS2021), 121611A (14 February 2022); https://doi.org/10.1117/12.2627237

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