Presentation
30 April 2023 The edge placement error characterization and optimization for advanced logic and DRAM nodes
Author Affiliations +
Abstract
As the term EPE was coined in the 1990ties, more recently a more inclusive definition of EPE has been proposed. Meanwhile semiconductor manufacturers see EPE as one of the main performance metrics enabling further shrink. In this paper we will give an update on the latest developments on EPE. Considering logic and memory use cases we will present evaluations of the EPE budget, including OPC model accuracy, overlay, CDU fingerprints for intra-field and inter field, overlay and local CD and placement error. The EPE fingerprint characterization is used to optimize scanner control for EPE performance on product. We will show how we can optimize the measured EPE fingerprints using scanner actuators.
Conference Presentation
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Harm Dillen, Wim Tel, Jaap Karssenberg, Jan Mulkens, Roy Anunciado, Yichen Zhang, Konstantin Nechaev, and Zuan Khalik "The edge placement error characterization and optimization for advanced logic and DRAM nodes", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124960O (30 April 2023); https://doi.org/10.1117/12.2658832
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KEYWORDS
Logic

Overlay metrology

Metrology

Optical proximity correction

Line edge roughness

Manufacturing

Scanners

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