Poster + Paper
27 April 2023 Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay
Author Affiliations +
Conference Poster
Abstract
In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nanotopography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Viorel Balan, Florent Michel, Ivanie Mendes, Celine Lapeyre, Lionel Vignoud, Ronald Otten, Orion Mouraille, Leon van Dijk, Blandine Minghetti, Jerome Depre, and Richard van Haren "Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 1249633 (27 April 2023); https://doi.org/10.1117/12.2658296
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KEYWORDS
Annealing

Semiconducting wafers

Distortion

Metrology

Overlay metrology

Chemical mechanical planarization

Deformation

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