Design and implementation of IEEE1588 clock synchronization system based on software and hardware collaboration

Chaosheng Lu; Xingzhong Xiong; Jianwu Wang

doi:10.1117/12.2673274

13 April 2023 Design and implementation of IEEE1588 clock synchronization system based on software and hardware collaboration

Chaosheng Lu, Xingzhong Xiong, Jianwu Wang

Author Affiliations +

Proceedings Volume 12605, 2022 2nd Conference on High Performance Computing and Communication Engineering (HPCCE 2022); 126050G (2023) https://doi.org/10.1117/12.2673274
Event: Second Conference on High Performance Computing and Communication Engineering, 2022, Harbin, China

Abstract

In this paper, the precise clock synchronization technology of IEEE1588 is studied, and a hardware and software co-implementation method based on the Zynq-7000 FPGA chip is proposed. In the aspect of hardware, the jitter delay of the protocol stack is shielded by stamping in the GMII interface and obtaining the timestamp information. In the aspect of the software, the protocol engine is transplanted in the user layer, at the same time, to realize register reading and writing and configuration, the driver is compiled into the Linux kernel in the driver layer. In addition, the real-time clock adjustment module of the slave clock is designed to adjust the clock quickly. The experimental results show that the clock synchronization method based on FPGA hardware and software co-implementation can realize the marking of the timestamp effectively, and the accuracy of clock synchronization reaches the level of sub-microsecond. In the meanwhile, the realizability and portability of synchronous system are also improved.

Citation Download Citation

Chaosheng Lu, Xingzhong Xiong, and Jianwu Wang "Design and implementation of IEEE1588 clock synchronization system based on software and hardware collaboration", Proc. SPIE 12605, 2022 2nd Conference on High Performance Computing and Communication Engineering (HPCCE 2022), 126050G (13 April 2023); https://doi.org/10.1117/12.2673274

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